Submitted By: Jim Gifford (patches at jg555 dot com) Date: 2005-10-02 Initial Package Version: 2.6.12 Origin: Various Upstream Status: Applied to Linux-MIPS.org Description: Makes changes needed for MIPS support diff -Naur linux-2.6.12.6.orig/Makefile linux-2.6.12.6/Makefile --- linux-2.6.12.6.orig/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/Makefile 2005-10-02 23:47:35.000000000 +0000 @@ -169,7 +169,8 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \ -e s/arm.*/arm/ -e s/sa110/arm/ \ - -e s/s390x/s390/ -e s/parisc64/parisc/ ) + -e s/s390x/s390/ -e s/parisc64/parisc/ \ + -e s/mips64/mips/ ) # Cross compiling and selecting different set of gcc/bin-utils # --------------------------------------------------------------------------- diff -Naur linux-2.6.12.6.orig/arch/mips/Makefile linux-2.6.12.6/arch/mips/Makefile --- linux-2.6.12.6.orig/arch/mips/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/Makefile 2005-10-02 23:47:35.000000000 +0000 @@ -16,7 +16,7 @@ -xassembler /dev/null > /dev/null 2>&1; then echo "$(1)"; \ else echo "$(2)"; fi ;) -cflags-y := +cflags-y := -ffreestanding # # Select the object file format to substitute into the linker script. @@ -52,13 +52,27 @@ CROSS_COMPILE := $(tool-prefix) endif +CHECKFLAGS-y += -D__linux__ -D__mips__ +CHECKFLAGS-$(CONFIG_MIPS32) += -D_MIPS_SZLONG=32 \ + -D__PTRDIFF_TYPE__=int +CHECKFLAGS-$(CONFIG_MIPS64) += -D_MIPS_SZLONG=64 \ + -D__PTRDIFF_TYPE__="long int" +CHECKFLAGS-$(CONFIG_CPU_BIG_ENDIAN) += -D__MIPSEB__ +CHECKFLAGS-$(CONFIG_CPU_LITTLE_ENDIAN) += -D__MIPSEL__ + +CHECKFLAGS = $(CHECKFLAGS-y) + ifdef CONFIG_BUILD_ELF64 gas-abi = 64 ld-emul = $(64bit-emul) vmlinux-32 = vmlinux.32 vmlinux-64 = vmlinux else +ifdef CONFIG_SGI_IP32 +gas-abi = o64 +else gas-abi = 32 +endif ld-emul = $(32bit-emul) vmlinux-32 = vmlinux vmlinux-64 = vmlinux.64 @@ -79,10 +93,11 @@ cflags-y += -I $(TOPDIR)/include/asm/gcc cflags-y += -G 0 -mno-abicalls -fno-pic -pipe cflags-y += $(call cc-option, -finline-limit=100000) -LDFLAGS_vmlinux += -G 0 -static -n +LDFLAGS_vmlinux += -G 0 -static -n -nostdlib MODFLAGS += -mlong-calls -cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer +cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \ + -fno-omit-frame-pointer # # Use: $(call set_gccflags,,,,,) @@ -118,7 +133,7 @@ else \ gcc_abi=; gcc_isa=-$(5); \ fi; \ -gas_abi=-Wa,-$(gcc-abi); gas_cpu=$$cpu; gas_isa=-Wa,$$isa; \ +gas_abi=-Wa,-mabi=$(gcc-abi); gas_cpu=$$cpu; gas_isa=-Wa,$$isa; \ while :; do \ for gas_opt in -Wa,-march= -Wa,-mcpu=; do \ $(CC) $$gas_abi $$gas_opt$$cpu $$gas_isa -Wa,-Z -c \ @@ -129,7 +144,7 @@ break; \ done; \ if test "$(gcc-abi)" != "$(gas-abi)"; then \ - gas_abi="-Wa,-$(gas-abi) -Wa,-mgp$(gcc-abi)"; \ + gas_abi="-Wa,-mabi=$(gas-abi) -Wa,-mgp$(gcc-abi)"; \ fi; \ if test "$$gcc_opt" = -march= && test -n "$$gcc_abi"; then \ $(CC) $$gcc_abi $$gcc_opt$$gcc_cpu -S -o /dev/null \ @@ -266,6 +281,13 @@ load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 # +# AMD Alchemy Pb1200 eval board +# +libs-$(CONFIG_MIPS_PB1200) += arch/mips/au1000/pb1200/ +cflags-$(CONFIG_MIPS_PB1200) += -Iinclude/asm-mips/mach-pb1x00 +load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000 + +# # AMD Alchemy Db1000 eval board # libs-$(CONFIG_MIPS_DB1000) += arch/mips/au1000/db1x00/ @@ -294,6 +316,13 @@ load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 # +# AMD Alchemy Db1200 eval board +# +libs-$(CONFIG_MIPS_DB1200) += arch/mips/au1000/pb1200/ +cflags-$(CONFIG_MIPS_DB1200) += -Iinclude/asm-mips/mach-db1x00 +load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 + +# # AMD Alchemy Bosporus eval board # libs-$(CONFIG_MIPS_BOSPORUS) += arch/mips/au1000/db1x00/ @@ -323,6 +352,7 @@ # Cobalt Server # core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/ +cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/cobalt load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000 # @@ -469,13 +499,6 @@ load-$(CONFIG_LASAT) += 0xffffffff80000000 # -# NEC Osprey (vr4181) board -# -core-$(CONFIG_NEC_OSPREY) += arch/mips/vr4181/common/ \ - arch/mips/vr4181/osprey/ -load-$(CONFIG_NEC_OSPREY) += 0xffffffff80002000 - -# # Common VR41xx # core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ @@ -711,6 +734,18 @@ all: $(vmlinux-64) endif +ifdef CONFIG_MIPS_ATLAS +all: vmlinux.srec +endif + +ifdef CONFIG_MIPS_MALTA +all: vmlinux.srec +endif + +ifdef CONFIG_MIPS_SEAD +all: vmlinux.srec +endif + ifdef CONFIG_SNI_RM200_PCI all: vmlinux.ecoff endif diff -Naur linux-2.6.12.6.orig/arch/mips/arc/Makefile linux-2.6.12.6/arch/mips/arc/Makefile --- linux-2.6.12.6.orig/arch/mips/arc/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/arc/Makefile 2005-10-02 23:47:35.000000000 +0000 @@ -3,7 +3,7 @@ # lib-y += cmdline.o env.o file.o identify.o init.o \ - misc.o time.o tree.o + misc.o salone.o time.o tree.o lib-$(CONFIG_ARC_MEMORY) += memory.o lib-$(CONFIG_ARC_CONSOLE) += arc_con.o diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/common/au1xxx_irqmap.c linux-2.6.12.6/arch/mips/au1000/common/au1xxx_irqmap.c --- linux-2.6.12.6.orig/arch/mips/au1000/common/au1xxx_irqmap.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/common/au1xxx_irqmap.c 2005-10-02 23:47:35.000000000 +0000 @@ -173,14 +173,14 @@ { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0}, { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0}, - { AU1550_TOY_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, - { AU1550_RTC_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1550_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, + { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0}, { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, @@ -201,14 +201,14 @@ { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0}, { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0}, - { AU1200_TOY_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, - { AU1200_RTC_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, - { AU1200_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, + { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0}, { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 }, { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0}, diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/common/cputable.c linux-2.6.12.6/arch/mips/au1000/common/cputable.c --- linux-2.6.12.6.orig/arch/mips/au1000/common/cputable.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/common/cputable.c 2005-10-02 23:47:35.000000000 +0000 @@ -37,7 +37,8 @@ { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 }, { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 }, { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 }, - { 0xffffffff, 0x04030200, "Au1200 AA", 0, 1 }, + { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 }, + { 0xffffffff, 0x04030201, "Au1200 AC", 0, 1 }, { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 }, }; diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/common/dbdma.c linux-2.6.12.6/arch/mips/au1000/common/dbdma.c --- linux-2.6.12.6.orig/arch/mips/au1000/common/dbdma.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/common/dbdma.c 2005-10-02 23:47:35.000000000 +0000 @@ -29,6 +29,7 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. * */ + #include #include #include @@ -38,10 +39,12 @@ #include #include #include +#include #include #include #include + #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) /* @@ -55,43 +58,16 @@ * functions. The drivers allocate the data buffers and assign them * to the descriptors. */ -static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock); +static spinlock_t au1xxx_dbdma_spin_lock = SPIN_LOCK_UNLOCKED; /* I couldn't find a macro that did this...... */ #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) -static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; -static int dbdma_initialized; +static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; +static int dbdma_initialized=0; static void au1xxx_dbdma_init(void); -typedef struct dbdma_device_table { - u32 dev_id; - u32 dev_flags; - u32 dev_tsize; - u32 dev_devwidth; - u32 dev_physaddr; /* If FIFO */ - u32 dev_intlevel; - u32 dev_intpolarity; -} dbdev_tab_t; - -typedef struct dbdma_chan_config { - u32 chan_flags; - u32 chan_index; - dbdev_tab_t *chan_src; - dbdev_tab_t *chan_dest; - au1x_dma_chan_t *chan_ptr; - au1x_ddma_desc_t *chan_desc_base; - au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; - void *chan_callparam; - void (*chan_callback)(int, void *, struct pt_regs *); -} chan_tab_t; - -#define DEV_FLAGS_INUSE (1 << 0) -#define DEV_FLAGS_ANYUSE (1 << 1) -#define DEV_FLAGS_OUT (1 << 2) -#define DEV_FLAGS_IN (1 << 3) - static dbdev_tab_t dbdev_tab[] = { #ifdef CONFIG_SOC_AU1550 /* UARTS */ @@ -157,13 +133,13 @@ { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 }, + { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 }, - { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, @@ -173,9 +149,9 @@ { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, - { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 }, + { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 }, + { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 }, { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, @@ -184,6 +160,24 @@ { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + + /* Provide 16 user definable device types */ + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0 }, }; #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t)) @@ -203,6 +197,30 @@ return NULL; } +u32 +au1xxx_ddma_add_device(dbdev_tab_t *dev) +{ + u32 ret = 0; + dbdev_tab_t *p=NULL; + static u16 new_id=0x1000; + + p = find_dbdev_id(0); + if ( NULL != p ) + { + memcpy(p, dev, sizeof(dbdev_tab_t)); + p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id); + ret = p->dev_id; + new_id++; +#if 0 + printk("add_device: id:%x flags:%x padd:%x\n", + p->dev_id, p->dev_flags, p->dev_physaddr ); +#endif + } + + return ret; +} +EXPORT_SYMBOL(au1xxx_ddma_add_device); + /* Allocate a channel and return a non-zero descriptor if successful. */ u32 @@ -215,7 +233,7 @@ int i; dbdev_tab_t *stp, *dtp; chan_tab_t *ctp; - volatile au1x_dma_chan_t *cp; + au1x_dma_chan_t *cp; /* We do the intialization on the first channel allocation. * We have to wait because of the interrupt handler initialization @@ -225,9 +243,6 @@ au1xxx_dbdma_init(); dbdma_initialized = 1; - if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS)) - return 0; - if ((stp = find_dbdev_id(srcid)) == NULL) return 0; if ((dtp = find_dbdev_id(destid)) == NULL) return 0; @@ -269,9 +284,9 @@ /* If kmalloc fails, it is caught below same * as a channel not available. */ - ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL); + ctp = (chan_tab_t *) + kmalloc(sizeof(chan_tab_t), GFP_KERNEL); chan_tab_ptr[i] = ctp; - ctp->chan_index = chan = i; break; } } @@ -279,10 +294,11 @@ if (ctp != NULL) { memset(ctp, 0, sizeof(chan_tab_t)); + ctp->chan_index = chan = i; dcp = DDMA_CHANNEL_BASE; dcp += (0x0100 * chan); ctp->chan_ptr = (au1x_dma_chan_t *)dcp; - cp = (volatile au1x_dma_chan_t *)dcp; + cp = (au1x_dma_chan_t *)dcp; ctp->chan_src = stp; ctp->chan_dest = dtp; ctp->chan_callback = callback; @@ -299,6 +315,9 @@ i |= DDMA_CFG_DED; if (dtp->dev_intpolarity) i |= DDMA_CFG_DP; + if ((stp->dev_flags & DEV_FLAGS_SYNC) || + (dtp->dev_flags & DEV_FLAGS_SYNC)) + i |= DDMA_CFG_SYNC; cp->ddma_cfg = i; au_sync(); @@ -309,14 +328,14 @@ rv = (u32)(&chan_tab_ptr[chan]); } else { - /* Release devices. - */ + /* Release devices */ stp->dev_flags &= ~DEV_FLAGS_INUSE; dtp->dev_flags &= ~DEV_FLAGS_INUSE; } } return rv; } +EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc); /* Set the device width if source or destination is a FIFO. * Should be 8, 16, or 32 bits. @@ -344,6 +363,7 @@ return rv; } +EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth); /* Allocate a descriptor ring, initializing as much as possible. */ @@ -370,7 +390,8 @@ * and if we try that first we are likely to not waste larger * slabs of memory. */ - desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), GFP_KERNEL); + desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), + GFP_KERNEL|GFP_DMA); if (desc_base == 0) return 0; @@ -381,7 +402,7 @@ kfree((const void *)desc_base); i = entries * sizeof(au1x_ddma_desc_t); i += (sizeof(au1x_ddma_desc_t) - 1); - if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0) + if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0) return 0; desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t)); @@ -461,9 +482,14 @@ /* If source input is fifo, set static address. */ if (stp->dev_flags & DEV_FLAGS_IN) { - src0 = stp->dev_physaddr; + if ( stp->dev_flags & DEV_FLAGS_BURSTABLE ) + src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST); + else src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC); + } + if (stp->dev_physaddr) + src0 = stp->dev_physaddr; /* Set up dest1. For now, assume no stride and increment. * A channel attribute update can change this later. @@ -487,10 +513,18 @@ /* If destination output is fifo, set static address. */ if (dtp->dev_flags & DEV_FLAGS_OUT) { - dest0 = dtp->dev_physaddr; + if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE ) + dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST); + else dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC); } + if (dtp->dev_physaddr) + dest0 = dtp->dev_physaddr; +#if 0 + printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", + dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 ); +#endif for (i=0; idscr_cmd0 = cmd0; dp->dscr_cmd1 = cmd1; @@ -499,6 +533,7 @@ dp->dscr_dest0 = dest0; dp->dscr_dest1 = dest1; dp->dscr_stat = 0; + dp->sw_context = dp->sw_status = 0; dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1)); dp++; } @@ -511,13 +546,14 @@ return (u32)(ctp->chan_desc_base); } +EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc); /* Put a source buffer into the DMA ring. * This updates the source pointer and byte count. Normally used * for memory to fifo transfers. */ u32 -au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes) +_au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags) { chan_tab_t *ctp; au1x_ddma_desc_t *dp; @@ -544,24 +580,40 @@ */ dp->dscr_source0 = virt_to_phys(buf); dp->dscr_cmd1 = nbytes; - dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ - ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */ - + /* Check flags */ + if (flags & DDMA_FLAGS_IE) + dp->dscr_cmd0 |= DSCR_CMD0_IE; + if (flags & DDMA_FLAGS_NOIE) + dp->dscr_cmd0 &= ~DSCR_CMD0_IE; /* Get next descriptor pointer. */ ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); + /* + * There is an errata on the Au1200/Au1550 parts that could result + * in "stale" data being DMA'd. It has to do with the snoop logic on + * the dache eviction buffer. NONCOHERENT_IO is on by default for + * these parts. If it is fixedin the future, these dma_cache_inv will + * just be nothing more than empty macros. See io.h. + * */ + dma_cache_wback_inv((unsigned long)buf, nbytes); + dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ + au_sync(); + dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); + ctp->chan_ptr->ddma_dbell = 0; + /* return something not zero. */ return nbytes; } +EXPORT_SYMBOL(_au1xxx_dbdma_put_source); /* Put a destination buffer into the DMA ring. * This updates the destination pointer and byte count. Normally used * to place an empty buffer into the ring for fifo to memory transfers. */ u32 -au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes) +_au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags) { chan_tab_t *ctp; au1x_ddma_desc_t *dp; @@ -583,11 +635,33 @@ if (dp->dscr_cmd0 & DSCR_CMD0_V) return 0; - /* Load up buffer address and byte count. - */ + /* Load up buffer address and byte count */ + + /* Check flags */ + if (flags & DDMA_FLAGS_IE) + dp->dscr_cmd0 |= DSCR_CMD0_IE; + if (flags & DDMA_FLAGS_NOIE) + dp->dscr_cmd0 &= ~DSCR_CMD0_IE; + dp->dscr_dest0 = virt_to_phys(buf); dp->dscr_cmd1 = nbytes; +#if 0 + printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", + dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0, + dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 ); +#endif + /* + * There is an errata on the Au1200/Au1550 parts that could result in + * "stale" data being DMA'd. It has to do with the snoop logic on the + * dache eviction buffer. NONCOHERENT_IO is on by default for these + * parts. If it is fixedin the future, these dma_cache_inv will just + * be nothing more than empty macros. See io.h. + * */ + dma_cache_inv((unsigned long)buf,nbytes); dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ + au_sync(); + dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); + ctp->chan_ptr->ddma_dbell = 0; /* Get next descriptor pointer. */ @@ -597,6 +671,7 @@ */ return nbytes; } +EXPORT_SYMBOL(_au1xxx_dbdma_put_dest); /* Get a destination buffer into the DMA ring. * Normally used to get a full buffer from the ring during fifo @@ -646,7 +721,7 @@ au1xxx_dbdma_stop(u32 chanid) { chan_tab_t *ctp; - volatile au1x_dma_chan_t *cp; + au1x_dma_chan_t *cp; int halt_timeout = 0; ctp = *((chan_tab_t **)chanid); @@ -666,6 +741,7 @@ cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V); au_sync(); } +EXPORT_SYMBOL(au1xxx_dbdma_stop); /* Start using the current descriptor pointer. If the dbdma encounters * a not valid descriptor, it will stop. In this case, we can just @@ -675,17 +751,17 @@ au1xxx_dbdma_start(u32 chanid) { chan_tab_t *ctp; - volatile au1x_dma_chan_t *cp; + au1x_dma_chan_t *cp; ctp = *((chan_tab_t **)chanid); - cp = ctp->chan_ptr; cp->ddma_desptr = virt_to_phys(ctp->cur_ptr); cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */ au_sync(); - cp->ddma_dbell = 0xffffffff; /* Make it go */ + cp->ddma_dbell = 0; au_sync(); } +EXPORT_SYMBOL(au1xxx_dbdma_start); void au1xxx_dbdma_reset(u32 chanid) @@ -704,15 +780,21 @@ do { dp->dscr_cmd0 &= ~DSCR_CMD0_V; + /* reset our SW status -- this is used to determine + * if a descriptor is in use by upper level SW. Since + * posting can reset 'V' bit. + */ + dp->sw_status = 0; dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); } while (dp != ctp->chan_desc_base); } +EXPORT_SYMBOL(au1xxx_dbdma_reset); u32 au1xxx_get_dma_residue(u32 chanid) { chan_tab_t *ctp; - volatile au1x_dma_chan_t *cp; + au1x_dma_chan_t *cp; u32 rv; ctp = *((chan_tab_t **)chanid); @@ -739,7 +821,7 @@ au1xxx_dbdma_stop(chanid); if (ctp->chan_desc_base != NULL) - kfree(ctp->chan_desc_base); + kfree((void *)ctp->chan_desc_base); stp->dev_flags &= ~DEV_FLAGS_INUSE; dtp->dev_flags &= ~DEV_FLAGS_INUSE; @@ -747,15 +829,16 @@ kfree(ctp); } +EXPORT_SYMBOL(au1xxx_dbdma_chan_free); static irqreturn_t dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs) { - u32 intstat; - u32 chan_index; + u32 intstat; + u32 chan_index; chan_tab_t *ctp; au1x_ddma_desc_t *dp; - volatile au1x_dma_chan_t *cp; + au1x_dma_chan_t *cp; intstat = dbdma_gptr->ddma_intstat; au_sync(); @@ -774,19 +857,27 @@ (ctp->chan_callback)(irq, ctp->chan_callparam, regs); ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); - - return IRQ_HANDLED; + return IRQ_RETVAL(1); } -static void -au1xxx_dbdma_init(void) +static void au1xxx_dbdma_init(void) { + int irq_nr; + dbdma_gptr->ddma_config = 0; dbdma_gptr->ddma_throttle = 0; dbdma_gptr->ddma_inten = 0xffff; au_sync(); - if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT, +#if defined(CONFIG_SOC_AU1550) + irq_nr = AU1550_DDMA_INT; +#elif defined(CONFIG_SOC_AU1200) + irq_nr = AU1200_DDMA_INT; +#else + #error Unknown Au1x00 SOC +#endif + + if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT, "Au1xxx dbdma", (void *)dbdma_gptr)) printk("Can't get 1550 dbdma irq"); } @@ -797,7 +888,8 @@ chan_tab_t *ctp; au1x_ddma_desc_t *dp; dbdev_tab_t *stp, *dtp; - volatile au1x_dma_chan_t *cp; + au1x_dma_chan_t *cp; + u32 i = 0; ctp = *((chan_tab_t **)chanid); stp = ctp->chan_src; @@ -822,15 +914,64 @@ dp = ctp->chan_desc_base; do { - printk("dp %08x, cmd0 %08x, cmd1 %08x\n", - (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); - printk("src0 %08x, src1 %08x, dest0 %08x\n", - dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0); - printk("dest1 %08x, stat %08x, nxtptr %08x\n", - dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr); + printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n", + i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); + printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n", + dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1); + printk("stat %08x, nxtptr %08x\n", + dp->dscr_stat, dp->dscr_nxtptr); dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); } while (dp != ctp->chan_desc_base); } +/* Put a descriptor into the DMA ring. + * This updates the source/destination pointers and byte count. + */ +u32 +au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr ) +{ + chan_tab_t *ctp; + au1x_ddma_desc_t *dp; + u32 nbytes=0; + + /* I guess we could check this to be within the + * range of the table...... + */ + ctp = *((chan_tab_t **)chanid); + + /* We should have multiple callers for a particular channel, + * an interrupt doesn't affect this pointer nor the descriptor, + * so no locking should be needed. + */ + dp = ctp->put_ptr; + + /* If the descriptor is valid, we are way ahead of the DMA + * engine, so just return an error condition. + */ + if (dp->dscr_cmd0 & DSCR_CMD0_V) + return 0; + + /* Load up buffer addresses and byte count. + */ + dp->dscr_dest0 = dscr->dscr_dest0; + dp->dscr_source0 = dscr->dscr_source0; + dp->dscr_dest1 = dscr->dscr_dest1; + dp->dscr_source1 = dscr->dscr_source1; + dp->dscr_cmd1 = dscr->dscr_cmd1; + nbytes = dscr->dscr_cmd1; + /* Allow the caller to specifiy if an interrupt is generated */ + dp->dscr_cmd0 &= ~DSCR_CMD0_IE; + dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; + ctp->chan_ptr->ddma_dbell = 0; + + /* Get next descriptor pointer. + */ + ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); + + /* return something not zero. + */ + return nbytes; +} + #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/common/dma.c linux-2.6.12.6/arch/mips/au1000/common/dma.c --- linux-2.6.12.6.orig/arch/mips/au1000/common/dma.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/common/dma.c 2005-10-02 23:47:35.000000000 +0000 @@ -39,7 +39,6 @@ #include #include #include -#include #include #include #include diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/common/irq.c linux-2.6.12.6/arch/mips/au1000/common/irq.c --- linux-2.6.12.6.orig/arch/mips/au1000/common/irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/common/irq.c 2005-10-02 23:47:35.000000000 +0000 @@ -253,52 +253,70 @@ static struct hw_interrupt_type rise_edge_irq_type = { - "Au1000 Rise Edge", - startup_irq, - shutdown_irq, - local_enable_irq, - local_disable_irq, - mask_and_ack_rise_edge_irq, - end_irq, - NULL + .typename = "Au1000 Rise Edge", + .startup = startup_irq, + .shutdown = shutdown_irq, + .enable = local_enable_irq, + .disable = local_disable_irq, + .ack = mask_and_ack_rise_edge_irq, + .end = end_irq, }; static struct hw_interrupt_type fall_edge_irq_type = { - "Au1000 Fall Edge", - startup_irq, - shutdown_irq, - local_enable_irq, - local_disable_irq, - mask_and_ack_fall_edge_irq, - end_irq, - NULL + .typename = "Au1000 Fall Edge", + .startup = startup_irq, + .shutdown = shutdown_irq, + .enable = local_enable_irq, + .disable = local_disable_irq, + .ack = mask_and_ack_fall_edge_irq, + .end = end_irq, }; static struct hw_interrupt_type either_edge_irq_type = { - "Au1000 Rise or Fall Edge", - startup_irq, - shutdown_irq, - local_enable_irq, - local_disable_irq, - mask_and_ack_either_edge_irq, - end_irq, - NULL + .typename = "Au1000 Rise or Fall Edge", + .startup = startup_irq, + .shutdown = shutdown_irq, + .enable = local_enable_irq, + .disable = local_disable_irq, + .ack = mask_and_ack_either_edge_irq, + .end = end_irq, }; static struct hw_interrupt_type level_irq_type = { - "Au1000 Level", - startup_irq, - shutdown_irq, - local_enable_irq, - local_disable_irq, - mask_and_ack_level_irq, - end_irq, - NULL + .typename = "Au1000 Level", + .startup = startup_irq, + .shutdown = shutdown_irq, + .enable = local_enable_irq, + .disable = local_disable_irq, + .ack = mask_and_ack_level_irq, + .end = end_irq, }; #ifdef CONFIG_PM -void startup_match20_interrupt(void) +void startup_match20_interrupt(void (*handler)(int, void *, struct pt_regs *)) { + static struct irqaction action; + /* This is a big problem.... since we didn't use request_irq + when kernel/irq.c calls probe_irq_xxx this interrupt will + be probed for usage. This will end up disabling the device :( + + Give it a bogus "action" pointer -- this will keep it from + getting auto-probed! + + By setting the status to match that of request_irq() we + can avoid it. --cgray + */ + action.dev_id = handler; + action.flags = 0; + action.mask = 0; + action.name = "Au1xxx TOY"; + action.handler = handler; + action.next = NULL; + + irq_desc[AU1000_TOY_MATCH2_INT].action = &action; + irq_desc[AU1000_TOY_MATCH2_INT].status + &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS); + local_enable_irq(AU1000_TOY_MATCH2_INT); } #endif @@ -492,7 +510,7 @@ intc0_req0 |= au_readl(IC0_REQ0INT); if (!intc0_req0) return; - +#ifdef AU1000_USB_DEV_REQ_INT /* * Because of the tight timing of SETUP token to reply * transactions, the USB devices-side packet complete @@ -503,7 +521,7 @@ do_IRQ(AU1000_USB_DEV_REQ_INT, regs); return; } - +#endif irq = au_ffs(intc0_req0) - 1; intc0_req0 &= ~(1< #include #include #include @@ -41,8 +42,42 @@ .resource = au1xxx_usb_ohci_resources, }; +/*** AU1100 LCD controller ***/ + +#ifdef CONFIG_FB_AU1100 +static struct resource au1100_lcd_resources[] = { + [0] = { + .start = LCD_PHYS_ADDR, + .end = LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_LCD_INT, + .end = AU1100_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1100_lcd_dmamask = ~(u32)0; + +static struct platform_device au1100_lcd_device = { + .name = "au1100-lcd", + .id = 0, + .dev = { + .dma_mask = &au1100_lcd_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(au1100_lcd_resources), + .resource = au1100_lcd_resources, +}; +#endif + + static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xxx_usb_ohci_device, +#ifdef CONFIG_FB_AU1100 + &au1100_lcd_device, +#endif }; int au1xxx_platform_init(void) diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/common/power.c linux-2.6.12.6/arch/mips/au1000/common/power.c --- linux-2.6.12.6.orig/arch/mips/au1000/common/power.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/common/power.c 2005-10-02 23:47:35.000000000 +0000 @@ -297,7 +297,6 @@ void *buffer, size_t * len) { int retval = 0; - void au1k_wait(void); if (!write) { *len = 0; @@ -306,7 +305,7 @@ if (retval) return retval; suspend_mode = 1; - au1k_wait(); + retval = pm_send_all(PM_RESUME, (void *) 0); } return retval; diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/common/setup.c linux-2.6.12.6/arch/mips/au1000/common/setup.c --- linux-2.6.12.6.orig/arch/mips/au1000/common/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/common/setup.c 2005-10-02 23:47:35.000000000 +0000 @@ -57,7 +57,7 @@ extern void au1xxx_timer_setup(struct irqaction *irq); extern void set_cpuspec(void); -static int __init au1x00_setup(void) +void __init plat_setup(void) { struct cpu_spec *sp; char *argptr; @@ -106,8 +106,6 @@ /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ #ifdef CONFIG_MIPS_HYDROGEN3 strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor"); -#else - strcat(argptr, " video=au1100fb:panel:s10,nohwcursor"); #endif } #endif @@ -153,15 +151,11 @@ au_sync(); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); au_writel(0, SYS_TOYTRIM); - - return 0; } -early_initcall(au1x00_setup); - #if defined(CONFIG_64BIT_PHYS_ADDR) /* This routine should be valid for all Au1x based boards */ -phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) +phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) { u32 start, end; diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/common/time.c linux-2.6.12.6/arch/mips/au1000/common/time.c --- linux-2.6.12.6.orig/arch/mips/au1000/common/time.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/common/time.c 2005-10-02 23:47:35.000000000 +0000 @@ -50,7 +50,6 @@ #include #include -extern void startup_match20_interrupt(void); extern void do_softirq(void); extern volatile unsigned long wall_jiffies; unsigned long missed_heart_beats = 0; @@ -58,14 +57,14 @@ static unsigned long r4k_offset; /* Amount to increment compare reg each time */ static unsigned long r4k_cur; /* What counter should be at next timer irq */ int no_au1xxx_32khz; -void (*au1k_wait_ptr)(void); +extern int allow_au1k_wait; /* default off for CP0 Counter */ /* Cycle counter value at the previous timer interrupt.. */ static unsigned int timerhi = 0, timerlo = 0; #ifdef CONFIG_PM #define MATCH20_INC 328 -extern void startup_match20_interrupt(void); +extern void startup_match20_interrupt(void (*handler)(int, void *, struct pt_regs *)); static unsigned long last_pc0, last_match20; #endif @@ -388,7 +387,6 @@ { unsigned int est_freq; extern unsigned long (*do_gettimeoffset)(void); - extern void au1k_wait(void); printk("calculating r4koff... "); r4k_offset = cal_r4koff(); @@ -446,13 +444,13 @@ au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); au_sync(); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); - startup_match20_interrupt(); + startup_match20_interrupt(counter0_irq); do_gettimeoffset = do_fast_pm_gettimeoffset; /* We can use the real 'wait' instruction. */ - au1k_wait_ptr = au1k_wait; + allow_au1k_wait = 1; } #else diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/csb250/init.c linux-2.6.12.6/arch/mips/au1000/csb250/init.c --- linux-2.6.12.6.orig/arch/mips/au1000/csb250/init.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/csb250/init.c 2005-10-02 23:47:35.000000000 +0000 @@ -35,7 +35,6 @@ #include #include #include -#include int prom_argc; char **prom_argv, **prom_envp; diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/db1x00/irqmap.c linux-2.6.12.6/arch/mips/au1000/db1x00/irqmap.c --- linux-2.6.12.6.orig/arch/mips/au1000/db1x00/irqmap.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/db1x00/irqmap.c 2005-10-02 23:47:35.000000000 +0000 @@ -48,6 +48,38 @@ #include #include +#ifdef CONFIG_MIPS_DB1500 +char irq_tab_alchemy[][5] __initdata = { + [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT371 */ + [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ +}; +#endif + +#ifdef CONFIG_MIPS_BOSPORUS +char irq_tab_alchemy[][5] __initdata = { + [11] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 11 - miniPCI */ + [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - SN1741 */ + [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ +}; +#endif + +#ifdef CONFIG_MIPS_MIRAGE +char irq_tab_alchemy[][5] __initdata = { + [11] = { -1, INTD, INTX, INTX, INTX}, /* IDSEL 11 - SMI VGX */ + [12] = { -1, INTX, INTX, INTC, INTX}, /* IDSEL 12 - PNX1300 */ + [13] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 13 - miniPCI */ +}; +#endif + +#ifdef CONFIG_MIPS_DB1550 +char irq_tab_alchemy[][5] __initdata = { + [11] = { -1, INTC, INTX, INTX, INTX}, /* IDSEL 11 - on-board HPT371 */ + [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */ + [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */ +}; +#endif + + au1xxx_irq_map_t au1xxx_irq_map[] = { #ifndef CONFIG_MIPS_MIRAGE diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/db1x00/mirage_ts.c linux-2.6.12.6/arch/mips/au1000/db1x00/mirage_ts.c --- linux-2.6.12.6.orig/arch/mips/au1000/db1x00/mirage_ts.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/db1x00/mirage_ts.c 2005-10-02 23:47:35.000000000 +0000 @@ -102,15 +102,15 @@ } mirage_ts_cal = { #if 0 - xscale: 84, - xtrans: -157, - yscale: 66, - ytrans: -150, + .xscale = 84, + .xtrans = -157, + .yscale = 66, + .ytrans = -150, #else - xscale: 84, - xtrans: -150, - yscale: 66, - ytrans: -146, + .xscale = 84, + .xtrans = -150, + .yscale = 66, + .ytrans = -146, #endif }; diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/hydrogen3/init.c linux-2.6.12.6/arch/mips/au1000/hydrogen3/init.c --- linux-2.6.12.6.orig/arch/mips/au1000/hydrogen3/init.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/hydrogen3/init.c 2005-10-02 23:47:35.000000000 +0000 @@ -37,7 +37,6 @@ #include #include #include -#include int prom_argc; char **prom_argv, **prom_envp; diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/mtx-1/init.c linux-2.6.12.6/arch/mips/au1000/mtx-1/init.c --- linux-2.6.12.6.orig/arch/mips/au1000/mtx-1/init.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/mtx-1/init.c 2005-10-02 23:47:35.000000000 +0000 @@ -33,7 +33,6 @@ #include #include #include -#include #include #include #include @@ -59,7 +58,7 @@ mips_machgroup = MACH_GROUP_ALCHEMY; mips_machtype = MACH_MTX1; /* set the platform # */ - + prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/mtx-1/irqmap.c linux-2.6.12.6/arch/mips/au1000/mtx-1/irqmap.c --- linux-2.6.12.6.orig/arch/mips/au1000/mtx-1/irqmap.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/mtx-1/irqmap.c 2005-10-02 23:47:35.000000000 +0000 @@ -47,6 +47,17 @@ #include #include +char irq_tab_alchemy[][5] __initdata = { + [0] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 00 - AdapterA-Slot0 (top) */ + [1] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 01 - AdapterA-Slot1 (bottom) */ + [2] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 02 - AdapterB-Slot0 (top) */ + [3] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 03 - AdapterB-Slot1 (bottom) */ + [4] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 04 - AdapterC-Slot0 (top) */ + [5] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 05 - AdapterC-Slot1 (bottom) */ + [6] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 06 - AdapterD-Slot0 (top) */ + [7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */ +}; + au1xxx_irq_map_t au1xxx_irq_map[] = { { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/pb1200/Makefile linux-2.6.12.6/arch/mips/au1000/pb1200/Makefile --- linux-2.6.12.6.orig/arch/mips/au1000/pb1200/Makefile 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/pb1200/Makefile 2005-10-02 23:47:35.000000000 +0000 @@ -0,0 +1,5 @@ +# +# Makefile for the Alchemy Semiconductor PB1200 board. +# + +lib-y := init.o board_setup.o irqmap.o diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/pb1200/board_setup.c linux-2.6.12.6/arch/mips/au1000/pb1200/board_setup.c --- linux-2.6.12.6.orig/arch/mips/au1000/pb1200/board_setup.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/pb1200/board_setup.c 2005-10-02 23:47:35.000000000 +0000 @@ -0,0 +1,183 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Alchemy Pb1200/Db1200 board setup. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_MIPS_PB1200 +#include +#endif + +#ifdef CONFIG_MIPS_DB1200 +#include +#define PB1200_ETH_INT DB1200_ETH_INT +#define PB1200_IDE_INT DB1200_IDE_INT +#endif + +extern void _board_init_irq(void); +extern void (*board_init_irq)(void); + +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX +extern u32 au1xxx_ide_virtbase; +extern u64 au1xxx_ide_physbase; +extern int au1xxx_ide_irq; + +u32 led_base_addr; +/* Ddma */ +chan_tab_t *ide_read_ch, *ide_write_ch; +u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma + +dbdev_tab_t new_dbdev_tab_element = { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }; +#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */ + +void board_reset (void) +{ + bcsr->resets = 0; +} + +void __init board_setup(void) +{ + char *argptr = NULL; + u32 pin_func; + +#if 0 + /* Enable PSC1 SYNC for AC97. Normaly done in audio driver, + * but it is board specific code, so put it here. + */ + pin_func = au_readl(SYS_PINFUNC); + au_sync(); + pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; + au_writel(pin_func, SYS_PINFUNC); + + au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */ + au_sync(); +#endif + +#if defined( CONFIG_I2C_ALGO_AU1550 ) + { + u32 freq0, clksrc; + + /* Select SMBUS in CPLD */ + bcsr->resets &= ~(BCSR_RESETS_PCS0MUX); + + pin_func = au_readl(SYS_PINFUNC); + au_sync(); + pin_func &= ~(3<<17 | 1<<4); + /* Set GPIOs correctly */ + pin_func |= 2<<17; + au_writel(pin_func, SYS_PINFUNC); + au_sync(); + + /* The i2c driver depends on 50Mhz clock */ + freq0 = au_readl(SYS_FREQCTRL0); + au_sync(); + freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); + freq0 |= (3<resets bit 12: 0=SMB 1=SPI + */ +#if defined(CONFIG_AU1550_PSC_SPI) && defined(CONFIG_I2C_ALGO_AU1550) + #error I2C and SPI are mutually exclusive. Both are physically connected to PSC0.\ + Refer to Pb1200/Db1200 documentation. +#elif defined( CONFIG_AU1550_PSC_SPI ) + bcsr->resets |= BCSR_RESETS_PCS0MUX; +#elif defined( CONFIG_I2C_ALGO_AU1550 ) + bcsr->resets &= (~BCSR_RESETS_PCS0MUX); +#endif + au_sync(); + +#ifdef CONFIG_MIPS_PB1200 + printk("AMD Alchemy Pb1200 Board\n"); +#endif +#ifdef CONFIG_MIPS_DB1200 + printk("AMD Alchemy Db1200 Board\n"); +#endif + + /* Setup Pb1200 External Interrupt Controller */ + { + extern void (*board_init_irq)(void); + extern void _board_init_irq(void); + board_init_irq = _board_init_irq; + } +} diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/pb1200/init.c linux-2.6.12.6/arch/mips/au1000/pb1200/init.c --- linux-2.6.12.6.orig/arch/mips/au1000/pb1200/init.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/pb1200/init.c 2005-10-02 23:47:35.000000000 +0000 @@ -0,0 +1,69 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * PB1200 board setup + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "Alchemy Pb1200"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = (int) fw_arg0; + prom_argv = (char **) fw_arg1; + prom_envp = (char **) fw_arg2; + + mips_machgroup = MACH_GROUP_ALCHEMY; + mips_machtype = MACH_PB1200; + + prom_init_cmdline(); + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + memsize = 0x08000000; + } else { + memsize = simple_strtol(memsize_str, NULL, 0); + } + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/pb1200/irqmap.c linux-2.6.12.6/arch/mips/au1000/pb1200/irqmap.c --- linux-2.6.12.6.orig/arch/mips/au1000/pb1200/irqmap.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/pb1200/irqmap.c 2005-10-02 23:47:35.000000000 +0000 @@ -0,0 +1,181 @@ +/* + * BRIEF MODULE DESCRIPTION + * Au1xxx irq map table + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_MIPS_PB1200 +#include +#endif + +#ifdef CONFIG_MIPS_DB1200 +#include +#define PB1200_INT_BEGIN DB1200_INT_BEGIN +#define PB1200_INT_END DB1200_INT_END +#endif + +au1xxx_irq_map_t au1xxx_irq_map[] = { + { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade +}; + +int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); + +/* + * Support for External interrupts on the PbAu1200 Development platform. + */ +static volatile int pb1200_cascade_en=0; + +void pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs) +{ + unsigned short bisr = bcsr->int_status; + int extirq_nr = 0; + + /* Clear all the edge interrupts. This has no effect on level */ + bcsr->int_status = bisr; + for( ; bisr; bisr &= (bisr-1) ) + { + extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr); + /* Ack and dispatch IRQ */ + do_IRQ(extirq_nr,regs); + } +} + +inline void pb1200_enable_irq(unsigned int irq_nr) +{ + bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN); + bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN); +} + +inline void pb1200_disable_irq(unsigned int irq_nr) +{ + bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN); + bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN); +} + +static unsigned int pb1200_startup_irq( unsigned int irq_nr ) +{ + if (++pb1200_cascade_en == 1) + { + request_irq(AU1000_GPIO_7, &pb1200_cascade_handler, + 0, "Pb1200 Cascade", &pb1200_cascade_handler ); +#ifdef CONFIG_MIPS_PB1200 + /* We have a problem with CPLD rev3. Enable a workaround */ + if( ((bcsr->whoami & BCSR_WHOAMI_CPLD)>>4) <= 3) + { + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n"); + printk("updated to latest revision. This software will not\n"); + printk("work on anything less than CPLD rev4\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + printk("\nWARNING!!!\n"); + while(1); + } +#endif + } + pb1200_enable_irq(irq_nr); + return 0; +} + +static void pb1200_shutdown_irq( unsigned int irq_nr ) +{ + pb1200_disable_irq(irq_nr); + if (--pb1200_cascade_en == 0) + { + free_irq(AU1000_GPIO_7,&pb1200_cascade_handler ); + } + return; +} + +static inline void pb1200_mask_and_ack_irq(unsigned int irq_nr) +{ + pb1200_disable_irq( irq_nr ); +} + +static void pb1200_end_irq(unsigned int irq_nr) +{ + if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { + pb1200_enable_irq(irq_nr); + } +} + +static struct hw_interrupt_type external_irq_type = +{ +#ifdef CONFIG_MIPS_PB1200 + "Pb1200 Ext", +#endif +#ifdef CONFIG_MIPS_DB1200 + "Db1200 Ext", +#endif + pb1200_startup_irq, + pb1200_shutdown_irq, + pb1200_enable_irq, + pb1200_disable_irq, + pb1200_mask_and_ack_irq, + pb1200_end_irq, + NULL +}; + +void _board_init_irq(void) +{ + int irq_nr; + + for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++) + { + irq_desc[irq_nr].handler = &external_irq_type; + pb1200_disable_irq(irq_nr); + } + + /* GPIO_7 can not be hooked here, so it is hooked upon first + request of any source attached to the cascade */ +} + diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/pb1500/irqmap.c linux-2.6.12.6/arch/mips/au1000/pb1500/irqmap.c --- linux-2.6.12.6.orig/arch/mips/au1000/pb1500/irqmap.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/pb1500/irqmap.c 2005-10-02 23:47:35.000000000 +0000 @@ -47,6 +47,11 @@ #include #include +char irq_tab_alchemy[][5] __initdata = { + [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT370 */ + [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ +}; + au1xxx_irq_map_t au1xxx_irq_map[] = { { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, diff -Naur linux-2.6.12.6.orig/arch/mips/au1000/pb1550/irqmap.c linux-2.6.12.6/arch/mips/au1000/pb1550/irqmap.c --- linux-2.6.12.6.orig/arch/mips/au1000/pb1550/irqmap.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/au1000/pb1550/irqmap.c 2005-10-02 23:47:35.000000000 +0000 @@ -47,6 +47,11 @@ #include #include +char irq_tab_alchemy[][5] __initdata = { + [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */ + [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */ +}; + au1xxx_irq_map_t au1xxx_irq_map[] = { { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, diff -Naur linux-2.6.12.6.orig/arch/mips/cobalt/Makefile linux-2.6.12.6/arch/mips/cobalt/Makefile --- linux-2.6.12.6.orig/arch/mips/cobalt/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/cobalt/Makefile 2005-10-02 23:47:35.000000000 +0000 @@ -2,6 +2,6 @@ # Makefile for the Cobalt micro systems family specific parts of the kernel # -obj-y := irq.o int-handler.o reset.o setup.o promcon.o +obj-y := irq.o int-handler.o reset.o setup.o EXTRA_AFLAGS := $(CFLAGS) diff -Naur linux-2.6.12.6.orig/arch/mips/cobalt/int-handler.S linux-2.6.12.6/arch/mips/cobalt/int-handler.S --- linux-2.6.12.6.orig/arch/mips/cobalt/int-handler.S 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/cobalt/int-handler.S 2005-10-02 23:47:35.000000000 +0000 @@ -18,8 +18,8 @@ SAVE_ALL CLI - la ra, ret_from_irq - move a1, sp + PTR_LA ra, ret_from_irq + move a0, sp j cobalt_irq END(cobalt_handle_int) diff -Naur linux-2.6.12.6.orig/arch/mips/cobalt/irq.c linux-2.6.12.6/arch/mips/cobalt/irq.c --- linux-2.6.12.6.orig/arch/mips/cobalt/irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/cobalt/irq.c 2005-10-02 23:47:35.000000000 +0000 @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include #include @@ -25,8 +27,8 @@ * the CPU interrupt lines, and ones that come in on the via chip. The CPU * mappings are: * - * 16, - Software interrupt 0 (unused) IE_SW0 - * 17 - Software interrupt 1 (unused) IE_SW0 + * 16 - Software interrupt 0 (unused) IE_SW0 + * 17 - Software interrupt 1 (unused) IE_SW1 * 18 - Galileo chip (timer) IE_IRQ0 * 19 - Tulip 0 + NCR SCSI IE_IRQ1 * 20 - Tulip 1 IE_IRQ2 @@ -42,61 +44,94 @@ * 15 - IDE1 */ -asmlinkage void cobalt_irq(struct pt_regs *regs) +static inline void galileo_irq(struct pt_regs *regs) { - unsigned int pending = read_c0_status() & read_c0_cause(); + unsigned int mask, pending, devfn; - if (pending & CAUSEF_IP2) { /* int 18 */ - unsigned long irq_src = GALILEO_INL(GT_INTRCAUSE_OFS); + mask = GALILEO_INL(GT_INTRMASK_OFS); + pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask; - /* Check for timer irq ... */ - if (irq_src & GALILEO_T0EXP) { - /* Clear the int line */ - GALILEO_OUTL(0, GT_INTRCAUSE_OFS); - do_IRQ(COBALT_TIMER_IRQ, regs); - } - return; - } + if (pending & GALILEO_INTR_T0EXP) { - if (pending & CAUSEF_IP6) { /* int 22 */ - int irq = i8259_irq(); + GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS); + do_IRQ(COBALT_GALILEO_IRQ, regs); - if (irq >= 0) - do_IRQ(irq, regs); - return; - } + } else if (pending & GALILEO_INTR_RETRY_CTR) { - if (pending & CAUSEF_IP3) { /* int 19 */ - do_IRQ(COBALT_ETH0_IRQ, regs); - return; - } + devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8; + GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS); + printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n", + PCI_SLOT(devfn), PCI_FUNC(devfn)); - if (pending & CAUSEF_IP4) { /* int 20 */ - do_IRQ(COBALT_ETH1_IRQ, regs); - return; - } + } else { - if (pending & CAUSEF_IP5) { /* int 21 */ - do_IRQ(COBALT_SERIAL_IRQ, regs); - return; + GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS); + printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending); } +} - if (pending & CAUSEF_IP7) { /* int 23 */ - do_IRQ(COBALT_QUBE_SLOT_IRQ, regs); - return; - } +static inline void via_pic_irq(struct pt_regs *regs) +{ + int irq; + + irq = i8259_irq(); + if (irq >= 0) + do_IRQ(irq, regs); +} + +asmlinkage void cobalt_irq(struct pt_regs *regs) +{ + unsigned pending; + + pending = read_c0_status() & read_c0_cause(); + + if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */ + + galileo_irq(regs); + + else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */ + + via_pic_irq(regs); + + else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */ + + do_IRQ(COBALT_CPU_IRQ + 3, regs); + + else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */ + + do_IRQ(COBALT_CPU_IRQ + 4, regs); + + else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */ + + do_IRQ(COBALT_CPU_IRQ + 5, regs); + + else if (pending & CAUSEF_IP7) /* IRQ 23 */ + + do_IRQ(COBALT_CPU_IRQ + 7, regs); } +static struct irqaction irq_via = { + no_action, 0, { { 0, } }, "cascade", NULL, NULL +}; + void __init arch_init_irq(void) { + /* + * Mask all Galileo interrupts. The Galileo + * handler is set in cobalt_timer_setup() + */ + GALILEO_OUTL(0, GT_INTRMASK_OFS); + set_except_vector(0, cobalt_handle_int); init_i8259_irqs(); /* 0 ... 15 */ - mips_cpu_irq_init(16); /* 16 ... 23 */ + mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */ /* * Mask all cpu interrupts * (except IE4, we already masked those at VIA level) */ change_c0_status(ST0_IM, IE_IRQ4); + + setup_irq(COBALT_VIA_IRQ, &irq_via); } diff -Naur linux-2.6.12.6.orig/arch/mips/cobalt/promcon.c linux-2.6.12.6/arch/mips/cobalt/promcon.c --- linux-2.6.12.6.orig/arch/mips/cobalt/promcon.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/cobalt/promcon.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,87 +0,0 @@ -/* - * PROM console for Cobalt Raq2 - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 1997 by Ralf Baechle - * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv) - * - */ - -#include -#include -#include -#include - -#include -#include -#include - -static unsigned long port = 0xc800000; - -static __inline__ void ns16550_cons_put_char(char ch, unsigned long ioaddr) -{ - char lsr; - - do { - lsr = inb(ioaddr + UART_LSR); - } while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE)); - outb(ch, ioaddr + UART_TX); -} - -static __inline__ char ns16550_cons_get_char(unsigned long ioaddr) -{ - while ((inb(ioaddr + UART_LSR) & UART_LSR_DR) == 0) - udelay(1); - return inb(ioaddr + UART_RX); -} - -void ns16550_console_write(struct console *co, const char *s, unsigned count) -{ - char lsr, ier; - unsigned i; - - ier = inb(port + UART_IER); - outb(0x00, port + UART_IER); - for (i=0; i < count; i++, s++) { - - if(*s == '\n') - ns16550_cons_put_char('\r', port); - ns16550_cons_put_char(*s, port); - } - - do { - lsr = inb(port + UART_LSR); - } while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE)); - - outb(ier, port + UART_IER); -} - -char getDebugChar(void) -{ - return ns16550_cons_get_char(port); -} - -void putDebugChar(char kgdb_char) -{ - ns16550_cons_put_char(kgdb_char, port); -} - -static struct console ns16550_console = { - .name = "prom", - .setup = NULL, - .write = ns16550_console_write, - .flags = CON_PRINTBUFFER, - .index = -1, -}; - -static int __init ns16550_setup_console(void) -{ - register_console(&ns16550_console); - - return 0; -} - -console_initcall(ns16550_setup_console); diff -Naur linux-2.6.12.6.orig/arch/mips/cobalt/reset.c linux-2.6.12.6/arch/mips/cobalt/reset.c --- linux-2.6.12.6.orig/arch/mips/cobalt/reset.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/cobalt/reset.c 2005-10-02 23:47:35.000000000 +0000 @@ -16,48 +16,45 @@ #include #include #include +#include -void cobalt_machine_restart(char *command) +void cobalt_machine_halt(void) { - *(volatile char *)0xbc000000 = 0x0f; + int state, last, diff; + unsigned long mark; /* - * Ouch, we're still alive ... This time we take the silver bullet ... - * ... and find that we leave the hardware in a state in which the - * kernel in the flush locks up somewhen during of after the PCI - * detection stuff. + * turn off bar on Qube, flash power off LED on RaQ (0.5Hz) + * + * restart if ENTER and SELECT are pressed */ - set_c0_status(ST0_BEV | ST0_ERL); - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_c0_wired(0); - __asm__ __volatile__( - "jr\t%0" - : - : "r" (0xbfc00000)); -} -extern int led_state; -#define kLED 0xBC000000 -#define LEDSet(x) (*(volatile unsigned char *) kLED) = (( unsigned char)x) + last = COBALT_KEY_PORT; -void cobalt_machine_halt(void) -{ - int mark; + for (state = 0;;) { + + state ^= COBALT_LED_POWER_OFF; + COBALT_LED_PORT = state; + + diff = COBALT_KEY_PORT ^ last; + last ^= diff; - /* Blink our cute? little LED (number 3)... */ - while (1) { - led_state = led_state | ( 1 << 3 ); - LEDSet(led_state); - mark = jiffies; - while (jiffies<(mark+HZ)); - led_state = led_state & ~( 1 << 3 ); - LEDSet(led_state); - mark = jiffies; - while (jiffies<(mark+HZ)); + if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT))) + COBALT_LED_PORT = COBALT_LED_RESET; + + for (mark = jiffies; jiffies - mark < HZ;) + ; } } +void cobalt_machine_restart(char *command) +{ + COBALT_LED_PORT = COBALT_LED_RESET; + + /* we should never get here */ + cobalt_machine_halt(); +} + /* * This triggers the luser mode device driver for the power switch ;-) */ diff -Naur linux-2.6.12.6.orig/arch/mips/cobalt/setup.c linux-2.6.12.6/arch/mips/cobalt/setup.c --- linux-2.6.12.6.orig/arch/mips/cobalt/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/cobalt/setup.c 2005-10-02 23:47:35.000000000 +0000 @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include @@ -21,6 +23,7 @@ #include #include #include +#include #include @@ -30,45 +33,44 @@ int cobalt_board_id; -static char my_cmdline[CL_SIZE] = { - "console=ttyS0,115200 " -#ifdef CONFIG_IP_PNP - "ip=on " -#endif -#ifdef CONFIG_ROOT_NFS - "root=/dev/nfs " -#else - "root=/dev/hda1 " -#endif - }; - const char *get_system_type(void) { + switch (cobalt_board_id) { + case COBALT_BRD_ID_QUBE1: + return "Cobalt Qube"; + case COBALT_BRD_ID_RAQ1: + return "Cobalt RaQ"; + case COBALT_BRD_ID_QUBE2: + return "Cobalt Qube2"; + case COBALT_BRD_ID_RAQ2: + return "Cobalt RaQ2"; + } return "MIPS Cobalt"; } static void __init cobalt_timer_setup(struct irqaction *irq) { - /* Load timer value for 150 Hz */ - GALILEO_OUTL(500000, GT_TC0_OFS); + /* Load timer value for 1KHz (TCLK is 50MHz) */ + GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS); + + /* Enable timer */ + GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS); - /* Register our timer interrupt */ - setup_irq(COBALT_TIMER_IRQ, irq); + /* Register interrupt */ + setup_irq(COBALT_GALILEO_IRQ, irq); - /* Enable timer ints */ - GALILEO_OUTL((GALILEO_ENTC0 | GALILEO_SELTC0), GT_TC_CONTROL_OFS); - /* Unmask timer int */ - GALILEO_OUTL(0x100, GT_INTRMASK_OFS); + /* Enable interrupt */ + GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); } extern struct pci_ops gt64111_pci_ops; static struct resource cobalt_mem_resource = { - "GT64111 PCI MEM", GT64111_IO_BASE, 0xffffffffUL, IORESOURCE_MEM + "PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM }; static struct resource cobalt_io_resource = { - "GT64111 IO MEM", 0x00001000UL, 0x0fffffffUL, IORESOURCE_IO + "PCI I/O", 0x1000, 0xffff, IORESOURCE_IO }; static struct resource cobalt_io_resources[] = { @@ -86,11 +88,12 @@ .mem_resource = &cobalt_mem_resource, .mem_offset = 0, .io_resource = &cobalt_io_resource, - .io_offset = 0x00001000UL - GT64111_IO_BASE + .io_offset = 0 - GT64111_IO_BASE }; -static void __init cobalt_setup(void) +int __init plat_setup(void) { + static struct uart_port uart; unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0); int i; @@ -100,7 +103,10 @@ board_timer_setup = cobalt_timer_setup; - set_io_port_base(KSEG1ADDR(GT64111_IO_BASE)); + set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE)); + + /* I/O port resource must include UART and LCD/buttons */ + ioport_resource.end = 0x0fffffff; /* * This is a prom style console. We just poke at the @@ -120,27 +126,61 @@ cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8); cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); + printk("Cobalt board ID: %d\n", cobalt_board_id); + #ifdef CONFIG_PCI register_pci_controller(&cobalt_pci_controller); #endif -} -early_initcall(cobalt_setup); +#ifdef CONFIG_SERIAL_8250 + if (cobalt_board_id > COBALT_BRD_ID_RAQ1) { + + uart.line = 0; + uart.type = PORT_UNKNOWN; + uart.uartclk = 18432000; + uart.irq = COBALT_SERIAL_IRQ; + uart.flags = STD_COM_FLAGS; + uart.iobase = 0xc800000; + uart.iotype = UPIO_PORT; + + early_serial_setup(&uart); + } +#endif +} /* * Prom init. We read our one and only communication with the firmware. - * Grab the amount of installed memory + * Grab the amount of installed memory. + * Better boot loaders (CoLo) pass a command line too :-) */ void __init prom_init(void) { - int argc = fw_arg0; - - strcpy(arcs_cmdline, my_cmdline); + int narg, indx, posn, nchr; + unsigned long memsz; + char **argv; mips_machgroup = MACH_GROUP_COBALT; - add_memory_region(0x0, argc & 0x7fffffff, BOOT_MEM_RAM); + memsz = fw_arg0 & 0x7fff0000; + narg = fw_arg0 & 0x0000ffff; + + if (narg) { + arcs_cmdline[0] = '\0'; + argv = (char **) fw_arg1; + posn = 0; + for (indx = 1; indx < narg; ++indx) { + nchr = strlen(argv[indx]); + if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline)) + break; + if (posn) + arcs_cmdline[posn++] = ' '; + strcpy(arcs_cmdline + posn, argv[indx]); + posn += nchr; + } + } + + add_memory_region(0x0, memsz, BOOT_MEM_RAM); } unsigned long __init prom_free_prom_memory(void) diff -Naur linux-2.6.12.6.orig/arch/mips/configs/atlas_defconfig linux-2.6.12.6/arch/mips/configs/atlas_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/atlas_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/atlas_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:00 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:01 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,33 +57,54 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set CONFIG_MIPS_ATLAS=y # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y @@ -90,7 +112,10 @@ CONFIG_DMA_NONCOHERENT=y CONFIG_MIPS_BONITO64=y CONFIG_MIPS_MSC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_MIPS_BOARDS_GEN=y CONFIG_MIPS_GT64120=y CONFIG_SWAP_IO_SPACE=y @@ -117,10 +142,22 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +CONFIG_BOARD_SCACHE=y +CONFIG_RM7000_CPU_SCACHE=y CONFIG_CPU_HAS_PREFETCH=y # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set @@ -143,10 +180,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -287,12 +320,8 @@ # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set @@ -302,7 +331,6 @@ CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 # CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set # CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set CONFIG_SCSI_QLA2XXX=y @@ -311,6 +339,7 @@ # CONFIG_SCSI_QLA2300 is not set # CONFIG_SCSI_QLA2322 is not set # CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set @@ -334,6 +363,8 @@ CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_EMC=m # # Fusion MPT device support @@ -360,7 +391,6 @@ # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -369,6 +399,7 @@ CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_FWMARK=y CONFIG_IP_ROUTE_MULTIPATH=y +# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y @@ -502,7 +533,7 @@ CONFIG_IP_NF_ARP_MANGLE=m # -# IPv6: Netfilter Configuration +# IPv6: Netfilter Configuration (EXPERIMENTAL) # CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m @@ -601,6 +632,7 @@ CONFIG_NET_QOS=y CONFIG_NET_ESTIMATOR=y CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_ROUTE=y @@ -611,6 +643,7 @@ # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_CLS_POLICE=y @@ -628,7 +661,6 @@ CONFIG_BONDING=m CONFIG_EQUALIZER=m CONFIG_TUN=m -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -683,6 +715,7 @@ # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -740,19 +773,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -765,6 +785,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -785,6 +816,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -811,6 +843,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -844,7 +881,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -854,13 +890,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -901,7 +933,12 @@ # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# CONFIG_XFS_FS=m +CONFIG_XFS_EXPORT=y # CONFIG_XFS_RT is not set CONFIG_XFS_QUOTA=y CONFIG_XFS_SECURITY=y @@ -1050,7 +1087,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -1072,6 +1111,7 @@ CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_TWOFISH=m diff -Naur linux-2.6.12.6.orig/arch/mips/configs/capcella_defconfig linux-2.6.12.6/arch/mips/configs/capcella_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/capcella_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/capcella_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:00 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:01 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,48 +57,72 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_VR41XX=y -# CONFIG_NEC_CMBVR4133 is not set -# CONFIG_CASIO_E55 is not set -# CONFIG_IBM_WORKPAD is not set -# CONFIG_TANBAC_TB0226 is not set -# CONFIG_TANBAC_TB0229 is not set -# CONFIG_VICTOR_MPC30X is not set -CONFIG_ZAO_CAPCELLA=y -CONFIG_PCI_VR41XX=y -CONFIG_VRC4173=y -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +CONFIG_MACH_VR41XX=y +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_NEC_CMBVR4133 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_VICTOR_MPC30X is not set +CONFIG_ZAO_CAPCELLA=y +CONFIG_PCI_VR41XX=y +# CONFIG_GPIO_VR41XX is not set +CONFIG_VRC4173=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -121,6 +146,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -144,10 +180,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -274,7 +306,6 @@ # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -337,7 +368,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -372,6 +402,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -428,19 +459,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=m -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -450,6 +468,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=m +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -470,6 +499,8 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_VR41XX is not set +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -508,6 +539,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -541,7 +577,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -551,13 +586,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -583,6 +614,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -675,7 +710,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/cobalt_defconfig linux-2.6.12.6/arch/mips/configs/cobalt_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/cobalt_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/cobalt_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:00 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:02 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,49 +41,78 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support # -# CONFIG_MODULES is not set +CONFIG_MODULES=y +# CONFIG_MODULE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set CONFIG_MIPS_COBALT=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_I8259=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_GT64111=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -108,6 +137,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -133,10 +173,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -157,7 +193,7 @@ # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y +# CONFIG_FW_LOADER is not set # # Memory Technology Devices (MTD) @@ -182,17 +218,14 @@ # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_CDROM_PKTCDVD is not set # # IO Schedulers @@ -201,7 +234,7 @@ CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -CONFIG_ATA_OVER_ETH=y +# CONFIG_ATA_OVER_ETH is not set # # ATA/ATAPI/MFM/RLL support @@ -224,9 +257,37 @@ # IDE chipset support/bugfixes # CONFIG_IDE_GENERIC=y -# CONFIG_BLK_DEV_IDEPCI is not set +CONFIG_BLK_DEV_IDEPCI=y +CONFIG_IDEPCI_SHARE_IRQ=y +# CONFIG_BLK_DEV_OFFBOARD is not set +# CONFIG_BLK_DEV_GENERIC is not set +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_IDEDMA_FORCED is not set +# CONFIG_IDEDMA_PCI_AUTO is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT34X is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +CONFIG_BLK_DEV_VIA82CXXX=y # CONFIG_IDE_ARM is not set -# CONFIG_BLK_DEV_IDEDMA is not set +CONFIG_BLK_DEV_IDEDMA=y +# CONFIG_IDEDMA_IVB is not set # CONFIG_IDEDMA_AUTO is not set # CONFIG_BLK_DEV_HD is not set @@ -264,7 +325,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -279,7 +339,7 @@ # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set CONFIG_INET_TUNNEL=y -CONFIG_IP_TCPDIAG=y +# CONFIG_IP_TCPDIAG is not set # CONFIG_IP_TCPDIAG_IPV6 is not set # CONFIG_IPV6 is not set # CONFIG_NETFILTER is not set @@ -313,8 +373,10 @@ # Network testing # # CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set +CONFIG_NETPOLL=y +# CONFIG_NETPOLL_RX is not set +# CONFIG_NETPOLL_TRAP is not set +CONFIG_NET_POLL_CONTROLLER=y # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set @@ -323,7 +385,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -342,7 +403,15 @@ # # Tulip family network device support # -# CONFIG_NET_TULIP is not set +CONFIG_NET_TULIP=y +CONFIG_DE2104X=y +CONFIG_TULIP=y +# CONFIG_TULIP_MWI is not set +# CONFIG_TULIP_MMIO is not set +# CONFIG_TULIP_NAPI is not set +# CONFIG_DE4X5 is not set +# CONFIG_WINBOND_840 is not set +# CONFIG_DM9102 is not set # CONFIG_HP100 is not set # CONFIG_NET_PCI is not set @@ -358,6 +427,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -384,7 +454,7 @@ # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set +CONFIG_NETCONSOLE=y # # ISDN subsystem @@ -404,29 +474,16 @@ # # Userland interfaces # -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +# CONFIG_INPUT_MOUSEDEV_SCREEN_X is not set +# CONFIG_INPUT_MOUSEDEV_SCREEN_Y is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -436,11 +493,22 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# # Character devices # -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y +# CONFIG_VT is not set +# CONFIG_VT_CONSOLE is not set +# CONFIG_HW_CONSOLE is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -456,6 +524,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -482,6 +551,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -511,13 +585,6 @@ # CONFIG_FB is not set # -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# # Sound # # CONFIG_SOUND is not set @@ -525,13 +592,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -552,20 +615,22 @@ # File systems # CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -CONFIG_FS_MBCACHE=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y +# CONFIG_DNOTIFY is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set @@ -591,7 +656,8 @@ # CONFIG_DEVFS_FS is not set CONFIG_DEVPTS_FS_XATTR=y CONFIG_DEVPTS_FS_SECURITY=y -# CONFIG_TMPFS is not set +CONFIG_TMPFS=y +# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y @@ -615,16 +681,8 @@ # # Network File Systems # -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFS_FS is not set # CONFIG_NFSD is not set -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set @@ -650,15 +708,16 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_CROSSCOMPILE=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CROSSCOMPILE is not set CONFIG_CMDLINE="" # # Security options # -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_KEYS is not set # CONFIG_SECURITY is not set # @@ -674,7 +733,7 @@ # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set +CONFIG_CRC32=y # CONFIG_LIBCRC32C is not set CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y diff -Naur linux-2.6.12.6.orig/arch/mips/configs/db1000_defconfig linux-2.6.12.6/arch/mips/configs/db1000_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/db1000_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/db1000_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:01 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:02 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,55 +57,64 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +CONFIG_MIPS_DB1000=y +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -CONFIG_SOC_AU1000=y -# CONFIG_SOC_AU1100 is not set -# CONFIG_SOC_AU1500 is not set -# CONFIG_SOC_AU1550 is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -CONFIG_MIPS_DB1000=y -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1000=y +CONFIG_SOC_AU1X00=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # @@ -127,6 +137,15 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -168,6 +187,7 @@ CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set # # Device Drivers @@ -183,7 +203,75 @@ # # Memory Technology Devices (MTD) # -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_AMDSTD_RETRY=0 +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_ALCHEMY=y + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set # # Parallel port support @@ -256,7 +344,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -334,7 +421,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) @@ -417,18 +503,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -438,6 +512,16 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -472,7 +556,8 @@ # Watchdog Cards # # CONFIG_WATCHDOG is not set -CONFIG_RTC=y +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set @@ -488,6 +573,10 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -521,7 +610,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -531,12 +619,9 @@ # # USB support # -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB is not set # # USB Gadget Support @@ -575,6 +660,10 @@ CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -620,6 +709,8 @@ # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=m # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set @@ -708,7 +799,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -731,6 +824,7 @@ # CONFIG_CRYPTO_SHA256 is not set CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m # CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_BLOWFISH is not set CONFIG_CRYPTO_TWOFISH=y diff -Naur linux-2.6.12.6.orig/arch/mips/configs/db1100_defconfig linux-2.6.12.6/arch/mips/configs/db1100_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/db1100_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/db1100_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:01 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:03 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,55 +57,64 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +CONFIG_MIPS_DB1100=y +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -# CONFIG_SOC_AU1000 is not set -CONFIG_SOC_AU1100=y -# CONFIG_SOC_AU1500 is not set -# CONFIG_SOC_AU1550 is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_DB1000 is not set -CONFIG_MIPS_DB1100=y -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1100=y +CONFIG_SOC_AU1X00=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # @@ -127,12 +137,21 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -# CONFIG_64BIT_PHYS_ADDR is not set +CONFIG_64BIT_PHYS_ADDR=y # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y @@ -146,15 +165,7 @@ # # PCCARD (PCMCIA/CardBus) support # -CONFIG_PCCARD=m -# CONFIG_PCMCIA_DEBUG is not set -CONFIG_PCMCIA=m - -# -# PC-card bridges -# -# CONFIG_TCIC is not set -# CONFIG_PCMCIA_AU1X00 is not set +# CONFIG_PCCARD is not set # # PCI Hotplug Support @@ -166,6 +177,7 @@ CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set # # Device Drivers @@ -181,7 +193,75 @@ # # Memory Technology Devices (MTD) # -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_AMDSTD_RETRY=0 +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_ALCHEMY=y + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set # # Parallel port support @@ -254,7 +334,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -332,14 +411,13 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y CONFIG_MII=m -# CONFIG_MIPS_AU1X00_ENET is not set +CONFIG_MIPS_AU1X00_ENET=y # # Ethernet (1000 Mbit) @@ -359,19 +437,6 @@ # CONFIG_NET_RADIO is not set # -# PCMCIA network device support -# -CONFIG_NET_PCMCIA=y -CONFIG_PCMCIA_3C589=m -CONFIG_PCMCIA_3C574=m -CONFIG_PCMCIA_FMVJ18X=m -CONFIG_PCMCIA_PCNET=m -CONFIG_PCMCIA_NMCLAN=m -CONFIG_PCMCIA_SMC91C92=m -CONFIG_PCMCIA_XIRC2PS=m -CONFIG_PCMCIA_AXNET=m - -# # Wan interfaces # # CONFIG_WAN is not set @@ -415,18 +480,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -CONFIG_SERIO_LIBPS2=m -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -436,6 +489,16 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=m +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -453,7 +516,10 @@ # # Non-8250 serial port support # -# CONFIG_SERIAL_AU1X00 is not set +CONFIG_SERIAL_AU1X00=y +CONFIG_SERIAL_AU1X00_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -467,7 +533,8 @@ # Watchdog Cards # # CONFIG_WATCHDOG is not set -CONFIG_RTC=y +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set @@ -475,12 +542,11 @@ # Ftape, the floppy tape device driver # # CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set # -# PCMCIA character devices +# TPM devices # -CONFIG_SYNCLINK_CS=m -# CONFIG_RAW_DRIVER is not set # # I2C support @@ -509,13 +575,41 @@ # # Graphics support # -# CONFIG_FB is not set +CONFIG_FB=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SOFT_CURSOR=y +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set +CONFIG_FB_AU1100=y +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set # # Console display driver support # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set + +# +# Logo configuration +# +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -526,12 +620,9 @@ # # USB support # -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB is not set # # USB Gadget Support @@ -570,6 +661,10 @@ CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -615,6 +710,8 @@ # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=m # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set @@ -703,7 +800,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -726,6 +825,7 @@ # CONFIG_CRYPTO_SHA256 is not set CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_WP512=m +# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_BLOWFISH is not set CONFIG_CRYPTO_TWOFISH=y diff -Naur linux-2.6.12.6.orig/arch/mips/configs/db1500_defconfig linux-2.6.12.6/arch/mips/configs/db1500_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/db1500_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/db1500_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:01 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:03 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,56 +57,66 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +CONFIG_MIPS_DB1500=y +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -# CONFIG_SOC_AU1000 is not set -# CONFIG_SOC_AU1100 is not set -CONFIG_SOC_AU1500=y -# CONFIG_SOC_AU1550 is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -CONFIG_MIPS_DB1500=y -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y -CONFIG_DMA_COHERENT=y +CONFIG_DMA_NONCOHERENT=y CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1500=y +CONFIG_SOC_AU1X00=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # @@ -128,6 +139,15 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -176,6 +196,7 @@ CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set # # Device Drivers @@ -193,8 +214,8 @@ # CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set @@ -239,9 +260,7 @@ # # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_DB1X00=y -CONFIG_MTD_DB1X00_BOOT=y -CONFIG_MTD_DB1X00_USER=y +CONFIG_MTD_ALCHEMY=y # # Self-contained MTD device drivers @@ -367,7 +386,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -445,7 +463,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -481,6 +498,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -549,19 +567,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -571,6 +576,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # # CONFIG_VT is not set @@ -590,6 +606,7 @@ CONFIG_SERIAL_AU1X00_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -603,7 +620,8 @@ # Watchdog Cards # # CONFIG_WATCHDOG is not set -CONFIG_RTC=y +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set @@ -620,6 +638,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -647,7 +670,6 @@ # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -689,6 +711,8 @@ # # USB support # +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB=y # CONFIG_USB_DEBUG is not set @@ -699,14 +723,14 @@ # CONFIG_USB_BANDWIDTH is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y # # USB Host Controller Drivers # # CONFIG_USB_EHCI_HCD is not set CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set @@ -762,6 +786,7 @@ # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set +CONFIG_USB_MON=m # # USB port drivers @@ -828,6 +853,10 @@ CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -963,7 +992,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -986,6 +1017,7 @@ # CONFIG_CRYPTO_SHA256 is not set CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m # CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_BLOWFISH is not set CONFIG_CRYPTO_TWOFISH=y diff -Naur linux-2.6.12.6.orig/arch/mips/configs/db1550_defconfig linux-2.6.12.6/arch/mips/configs/db1550_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/db1550_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/db1550_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:02 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:04 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,56 +57,65 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +CONFIG_MIPS_DB1550=y +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -# CONFIG_SOC_AU1000 is not set -# CONFIG_SOC_AU1100 is not set -# CONFIG_SOC_AU1500 is not set -CONFIG_SOC_AU1550=y -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -CONFIG_MIPS_DB1550=y -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y -CONFIG_DMA_COHERENT=y +CONFIG_DMA_NONCOHERENT=y CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1550=y +CONFIG_SOC_AU1X00=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # @@ -128,6 +138,15 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -176,6 +195,7 @@ CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set # # Device Drivers @@ -193,8 +213,8 @@ # CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set @@ -238,9 +258,7 @@ # # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_DB1550=y -CONFIG_MTD_DB1550_BOOT=y -CONFIG_MTD_DB1550_USER=y +CONFIG_MTD_ALCHEMY=y # # Self-contained MTD device drivers @@ -398,7 +416,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -476,7 +493,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -512,6 +528,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -588,19 +605,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -610,6 +614,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # # CONFIG_VT is not set @@ -629,6 +644,7 @@ CONFIG_SERIAL_AU1X00_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -660,6 +676,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -687,7 +708,6 @@ # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -697,13 +717,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -742,6 +758,10 @@ CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -877,7 +897,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -900,6 +922,7 @@ # CONFIG_CRYPTO_SHA256 is not set CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m # CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_BLOWFISH is not set CONFIG_CRYPTO_TWOFISH=y diff -Naur linux-2.6.12.6.orig/arch/mips/configs/ddb5476_defconfig linux-2.6.12.6/arch/mips/configs/ddb5476_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/ddb5476_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/ddb5476_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:02 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:04 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -50,40 +51,63 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set CONFIG_DDB5476=y # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_I8259=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_DDB5XXX_COMMON=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -109,6 +133,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -135,11 +170,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# -CONFIG_PCMCIA_PROBE=y - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -181,7 +211,6 @@ # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -274,7 +303,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -336,7 +364,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -351,7 +378,6 @@ # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set @@ -378,6 +404,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -434,19 +461,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -456,6 +470,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -476,6 +501,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -502,6 +528,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -529,6 +560,11 @@ # Graphics support # CONFIG_FB=y +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_SOFT_CURSOR is not set +# CONFIG_FB_MACMODES is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set # CONFIG_FB_CIRRUS is not set @@ -536,6 +572,7 @@ # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set +# CONFIG_FB_NVIDIA is not set # CONFIG_FB_RIVA is not set # CONFIG_FB_MATROX is not set # CONFIG_FB_RADEON_OLD is not set @@ -548,8 +585,10 @@ # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_SMIVGX is not set # CONFIG_FB_TRIDENT is not set # CONFIG_FB_E1356 is not set +# CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set # @@ -574,13 +613,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -606,6 +641,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -667,7 +706,6 @@ # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -696,7 +734,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="ip=any" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/ddb5477_defconfig linux-2.6.12.6/arch/mips/configs/ddb5477_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/ddb5477_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/ddb5477_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:02 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:05 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -50,41 +51,64 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set CONFIG_DDB5477=y -CONFIG_DDB5477_BUS_FREQUENCY=0 -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +CONFIG_DDB5477_BUS_FREQUENCY=0 CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_I8259=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_DDB5XXX_COMMON=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -109,6 +133,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -134,10 +169,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -242,7 +273,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -304,7 +334,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -359,6 +388,7 @@ # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -415,19 +445,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -437,6 +454,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -457,6 +485,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -483,6 +512,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -516,7 +550,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -526,13 +559,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -558,6 +587,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -650,7 +683,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="ip=any" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/decstation_defconfig linux-2.6.12.6/arch/mips/configs/decstation_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/decstation_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/decstation_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:03 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:15 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,40 +57,63 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set CONFIG_MACH_DECSTATION=y # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_EARLY_PRINTK=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=4 @@ -114,6 +138,16 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -134,10 +168,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -266,7 +296,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -328,7 +357,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) @@ -391,18 +419,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -412,12 +428,23 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_SERIAL_DEC is not set # # Serial drivers @@ -456,6 +483,10 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -489,7 +520,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -503,10 +533,6 @@ # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -534,6 +560,10 @@ # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -590,7 +620,6 @@ # # CONFIG_NFS_FS is not set # CONFIG_NFSD is not set -# CONFIG_EXPORTFS is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set @@ -630,7 +659,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/e55_defconfig linux-2.6.12.6/arch/mips/configs/e55_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/e55_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/e55_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:03 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:15 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,47 +57,71 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_VR41XX=y -# CONFIG_NEC_CMBVR4133 is not set -CONFIG_CASIO_E55=y -# CONFIG_IBM_WORKPAD is not set -# CONFIG_TANBAC_TB0226 is not set -# CONFIG_TANBAC_TB0229 is not set -# CONFIG_VICTOR_MPC30X is not set -# CONFIG_ZAO_CAPCELLA is not set -# CONFIG_VRC4171 is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +CONFIG_MACH_VR41XX=y +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_NEC_CMBVR4133 is not set +CONFIG_CASIO_E55=y +# CONFIG_IBM_WORKPAD is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +# CONFIG_GPIO_VR41XX is not set +# CONFIG_VRC4171 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -120,6 +145,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -140,11 +176,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# -CONFIG_PCMCIA_PROBE=y - -# # PCI Hotplug Support # @@ -185,7 +216,6 @@ # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set @@ -270,7 +300,6 @@ # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -330,7 +359,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -343,7 +371,6 @@ CONFIG_NET_ETHERNET=y # CONFIG_MII is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set # CONFIG_AT1700 is not set @@ -408,18 +435,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -429,6 +444,16 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -449,6 +474,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_VR41XX is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -487,6 +513,10 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -521,7 +551,6 @@ # CONFIG_VGA_CONSOLE is not set # CONFIG_MDA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -535,10 +564,6 @@ # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -562,6 +587,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -653,7 +682,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/ev64120_defconfig linux-2.6.12.6/arch/mips/configs/ev64120_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/ev64120_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/ev64120_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:03 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:16 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,40 +57,63 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set CONFIG_MIPS_EV64120=y -# CONFIG_EVB_PCI1 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_EVB_PCI1 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_MIPS_GT64120=y # CONFIG_SYSCLK_75 is not set # CONFIG_SYSCLK_83 is not set @@ -116,6 +140,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -142,10 +177,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -249,7 +280,6 @@ # Networking options # # CONFIG_PACKET is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -311,7 +341,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -346,6 +375,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -409,19 +439,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -431,6 +448,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -451,6 +479,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -477,6 +506,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -510,7 +544,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -520,13 +553,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -552,6 +581,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -613,7 +646,6 @@ # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -642,7 +674,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw nfsroot=192.168.1.1:/mnt/disk2/fs.gal ip=192.168.1.211:192.168.1.1:::gt::" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/ev96100_defconfig linux-2.6.12.6/arch/mips/configs/ev96100_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/ev96100_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/ev96100_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:03 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:16 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,39 +57,62 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set CONFIG_MIPS_EV96100=y # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_GT64120=y CONFIG_SWAP_IO_SPACE=y @@ -115,6 +139,17 @@ CONFIG_CPU_RM7000=y # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -142,10 +177,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -241,7 +272,6 @@ # Networking options # # CONFIG_PACKET is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -303,7 +333,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) @@ -366,18 +395,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -387,6 +404,16 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -432,6 +459,10 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -465,7 +496,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -479,10 +509,6 @@ # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -506,6 +532,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -567,7 +597,6 @@ # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -596,7 +625,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/ip22_defconfig linux-2.6.12.6/arch/mips/configs/ip22_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/ip22_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/ip22_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:04 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:17 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,7 +23,6 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y @@ -33,6 +30,9 @@ CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -42,6 +42,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,40 +58,63 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set CONFIG_SGI_IP22=y -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y CONFIG_DMA_NONCOHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y CONFIG_ARC32=y @@ -119,6 +143,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -135,6 +170,7 @@ # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # +CONFIG_HW_HAS_EISA=y # CONFIG_EISA is not set CONFIG_MMU=y @@ -144,10 +180,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -276,7 +308,6 @@ # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -409,7 +440,7 @@ CONFIG_IP_NF_ARP_MANGLE=m # -# IPv6: Netfilter Configuration +# IPv6: Netfilter Configuration (EXPERIMENTAL) # CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m @@ -478,6 +509,7 @@ CONFIG_NET_QOS=y CONFIG_NET_ESTIMATOR=y CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_ROUTE=y @@ -488,6 +520,7 @@ # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_CLS_POLICE=y @@ -505,7 +538,6 @@ CONFIG_BONDING=m CONFIG_EQUALIZER=m CONFIG_TUN=m -CONFIG_ETHERTAP=m # # Ethernet (10 or 100Mbit) @@ -568,18 +600,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y @@ -597,6 +617,16 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -648,6 +678,10 @@ CONFIG_MAX_RAW_DEVS=256 # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -692,7 +726,6 @@ # CONFIG_LOGO_LINUX_VGA16 is not set # CONFIG_LOGO_LINUX_CLUT224 is not set CONFIG_LOGO_SGI_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -706,10 +739,6 @@ # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -739,7 +768,12 @@ # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# CONFIG_XFS_FS=m +CONFIG_XFS_EXPORT=y # CONFIG_XFS_RT is not set CONFIG_XFS_QUOTA=y CONFIG_XFS_SECURITY=y @@ -907,7 +941,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -930,6 +966,7 @@ CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_TWOFISH=m @@ -944,7 +981,7 @@ CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_TEST=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices diff -Naur linux-2.6.12.6.orig/arch/mips/configs/ip27_defconfig linux-2.6.12.6/arch/mips/configs/ip27_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/ip27_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/ip27_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,11 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:04 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:17 2005 # CONFIG_MIPS=y -CONFIG_MIPS64=y -CONFIG_64BIT=y # # Code maturity level options @@ -13,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -24,14 +23,17 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=15 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_CPUSETS=y CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,45 +60,69 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set CONFIG_SGI_IP27=y +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_SGI_SN0_N_MODE is not set CONFIG_DISCONTIGMEM=y CONFIG_NUMA=y # CONFIG_MAPPED_KERNEL is not set # CONFIG_REPLICATE_KTEXT is not set # CONFIG_REPLICATE_EXHANDLERS is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set -# CONFIG_SNI_RM200_PCI is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y CONFIG_DMA_IP27=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_MIPS_L1_CACHE_SHIFT=7 CONFIG_ARC64=y CONFIG_BOOT_ELF64=y @@ -121,6 +148,16 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y +CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -150,10 +187,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -163,7 +196,7 @@ # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set -# CONFIG_BUILD_ELF64 is not set +CONFIG_BUILD_ELF64=y CONFIG_MIPS32_COMPAT=y CONFIG_COMPAT=y CONFIG_MIPS32_O32=y @@ -179,7 +212,7 @@ # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m # # Memory Technology Devices (MTD) @@ -256,7 +289,7 @@ # CONFIG_SCSI_SPI_ATTRS=y # CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m # # SCSI low-level drivers @@ -271,18 +304,13 @@ # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set -CONFIG_SCSI_QLOGIC_ISP=y # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set CONFIG_SCSI_QLA2XXX=y @@ -291,6 +319,7 @@ # CONFIG_SCSI_QLA2300 is not set # CONFIG_SCSI_QLA2322 is not set # CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_DEBUG is not set @@ -313,6 +342,8 @@ CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_EMC=m # # Fusion MPT device support @@ -339,7 +370,6 @@ # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -404,6 +434,7 @@ CONFIG_NET_QOS=y CONFIG_NET_ESTIMATOR=y CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_ROUTE=y @@ -413,6 +444,7 @@ # CONFIG_NET_CLS_IND is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_CLS_POLICE=y @@ -430,7 +462,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -468,6 +499,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -513,25 +545,15 @@ # CONFIG_INPUT is not set # -# Userland interfaces -# - -# -# Input I/O drivers +# Hardware I/O ports # -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y CONFIG_SERIO=y # CONFIG_SERIO_I8042 is not set CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set # CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_LIBPS2=m CONFIG_SERIO_RAW=m - -# -# Input Device Drivers -# +# CONFIG_GAMEPORT is not set # # Character devices @@ -557,6 +579,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -584,6 +607,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -611,7 +639,6 @@ # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -621,13 +648,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -642,7 +665,11 @@ # # InfiniBand support # -# CONFIG_INFINIBAND is not set +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_MTHCA=m +# CONFIG_INFINIBAND_MTHCA_DEBUG is not set +CONFIG_INFINIBAND_IPOIB=m +# CONFIG_INFINIBAND_IPOIB_DEBUG is not set # # File systems @@ -661,6 +688,10 @@ # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# CONFIG_XFS_FS=m # CONFIG_XFS_RT is not set CONFIG_XFS_QUOTA=y @@ -728,7 +759,6 @@ # CONFIG_ROOT_NFS is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_RPCSEC_GSS_KRB5=y @@ -772,7 +802,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=15 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -795,6 +827,7 @@ CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_BLOWFISH=y CONFIG_CRYPTO_TWOFISH=y @@ -809,7 +842,7 @@ CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_MICHAEL_MIC=y CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_TEST=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices diff -Naur linux-2.6.12.6.orig/arch/mips/configs/ip32_defconfig linux-2.6.12.6/arch/mips/configs/ip32_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/ip32_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/ip32_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,11 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:04 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:18 2005 # CONFIG_MIPS=y -CONFIG_MIPS64=y -CONFIG_64BIT=y # # Code maturity level options @@ -13,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +24,15 @@ # CONFIG_BSD_PROCESS_ACCT_V3 is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +42,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -50,33 +52,55 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set CONFIG_SGI_IP32=y -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y @@ -84,7 +108,9 @@ CONFIG_DMA_IP32=y CONFIG_OWN_DMA=y CONFIG_DMA_NONCOHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_ARC32=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -111,6 +137,16 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y +CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -138,10 +174,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -243,7 +275,7 @@ # # SCSI Transport Attributes # -# CONFIG_SCSI_SPI_ATTRS is not set +CONFIG_SCSI_SPI_ATTRS=y # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set @@ -265,18 +297,13 @@ # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set CONFIG_SCSI_QLA2XXX=y @@ -285,6 +312,7 @@ # CONFIG_SCSI_QLA2300 is not set # CONFIG_SCSI_QLA2322 is not set # CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_DEBUG is not set @@ -319,7 +347,6 @@ # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -381,7 +408,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -417,6 +443,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -474,27 +501,25 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports # -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y CONFIG_SERIO=y # CONFIG_SERIO_I8042 is not set CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set # CONFIG_SERIO_PCIPS2 is not set # CONFIG_SERIO_MACEPS2 is not set # CONFIG_SERIO_LIBPS2 is not set CONFIG_SERIO_RAW=y - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set +# CONFIG_GAMEPORT is not set # # Character devices @@ -517,6 +542,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -543,6 +569,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -576,7 +607,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -586,13 +616,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -618,6 +644,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -681,7 +711,6 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -720,7 +749,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/it8172_defconfig linux-2.6.12.6/arch/mips/configs/it8172_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/it8172_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/it8172_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:05 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:19 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -26,13 +24,15 @@ # CONFIG_BSD_PROCESS_ACCT_V3 is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -42,6 +42,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,40 +58,63 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set CONFIG_MIPS_ITE8172=y -# CONFIG_IT8172_REVC is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_IT8172_REVC is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_ITE_BOARD_GEN=y CONFIG_IT8172_CIR=y CONFIG_IT8712=y @@ -116,6 +140,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -139,10 +174,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -169,8 +200,8 @@ # CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_PARTITIONS is not set # CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_PARTITIONS is not set # # User Modules And Translation Layers @@ -330,7 +361,6 @@ # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -392,7 +422,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) @@ -454,18 +483,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -475,6 +492,16 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -524,6 +551,10 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -557,7 +588,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -591,10 +621,6 @@ # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -618,6 +644,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -681,7 +711,6 @@ # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -710,7 +739,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/ivr_defconfig linux-2.6.12.6/arch/mips/configs/ivr_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/ivr_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/ivr_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:05 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:19 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -26,13 +24,15 @@ # CONFIG_BSD_PROCESS_ACCT_V3 is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -42,6 +42,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,39 +58,62 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set CONFIG_MIPS_IVR=y -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_ITE_BOARD_GEN=y CONFIG_IT8172_CIR=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -114,6 +138,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -139,10 +174,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -269,7 +300,6 @@ # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -331,7 +361,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -366,6 +395,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -422,19 +452,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -444,6 +461,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -466,6 +494,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -491,6 +520,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -524,7 +558,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -534,13 +567,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -566,6 +595,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -627,7 +660,6 @@ # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -656,7 +688,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/jaguar-atx_defconfig linux-2.6.12.6/arch/mips/configs/jaguar-atx_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/jaguar-atx_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/jaguar-atx_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:05 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:20 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ # CONFIG_EXPERIMENTAL is not set CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -24,7 +22,6 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y @@ -32,6 +29,9 @@ CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -54,35 +55,64 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +CONFIG_MOMENCO_JAGUAR_ATX=y # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -CONFIG_MOMENCO_JAGUAR_ATX=y -CONFIG_JAGUAR_DMALOW=y -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +CONFIG_JAGUAR_DMALOW=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_LIMITED_DMA=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y CONFIG_IRQ_MV64340=y @@ -111,6 +141,17 @@ # CONFIG_CPU_RM7000 is not set CONFIG_CPU_RM9000=y # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -142,10 +183,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -247,7 +284,6 @@ # Networking options # # CONFIG_PACKET is not set -# CONFIG_NETLINK_DEV is not set CONFIG_UNIX=y # CONFIG_NET_KEY is not set CONFIG_INET=y @@ -265,7 +301,14 @@ # CONFIG_INET_IPCOMP is not set CONFIG_INET_TUNNEL=m CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set +CONFIG_IP_TCPDIAG_IPV6=y +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_TUNNEL=m # CONFIG_NETFILTER is not set CONFIG_XFRM=y CONFIG_XFRM_USER=m @@ -345,6 +388,7 @@ # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set CONFIG_MV643XX_ETH=y CONFIG_MV643XX_ETH_0=y CONFIG_MV643XX_ETH_1=y @@ -390,20 +434,10 @@ # CONFIG_INPUT is not set # -# Userland interfaces -# - +# Hardware I/O ports # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y # CONFIG_SERIO is not set -# CONFIG_SERIO_I8042 is not set - -# -# Input Device Drivers -# +# CONFIG_GAMEPORT is not set # # Character devices @@ -424,6 +458,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -450,6 +485,10 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -477,7 +516,6 @@ # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -487,13 +525,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -518,6 +552,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -569,7 +607,6 @@ # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set @@ -590,7 +627,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -604,7 +643,31 @@ # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_TEST=m # # Hardware crypto devices @@ -615,6 +678,8 @@ # # CONFIG_CRC_CCITT is not set # CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y diff -Naur linux-2.6.12.6.orig/arch/mips/configs/jmr3927_defconfig linux-2.6.12.6/arch/mips/configs/jmr3927_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/jmr3927_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/jmr3927_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:06 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:20 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -50,39 +51,62 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -CONFIG_TOSHIBA_JMR3927=y +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +CONFIG_TOSHIBA_JMR3927=y # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_MIPS_TX3927=y CONFIG_SWAP_IO_SPACE=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -108,6 +132,15 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -132,10 +165,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -240,7 +269,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -302,7 +330,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -337,6 +364,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -393,19 +421,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -415,6 +430,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -425,11 +451,9 @@ # CONFIG_ROCKETPORT is not set # CONFIG_CYCLADES is not set # CONFIG_DIGIEPCA is not set -# CONFIG_DIGI is not set # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set # CONFIG_ISI is not set -# CONFIG_SYNCLINK is not set # CONFIG_SYNCLINKMP is not set # CONFIG_N_HDLC is not set # CONFIG_RISCOM8 is not set @@ -437,10 +461,6 @@ # CONFIG_SX is not set # CONFIG_RIO is not set # CONFIG_STALDRV is not set -# CONFIG_SERIAL_TX3912 is not set -CONFIG_TXX927_SERIAL=y -CONFIG_TXX927_SERIAL_CONSOLE=y -# CONFIG_SERIAL_TXX9 is not set # # Serial drivers @@ -450,6 +470,13 @@ # # Non-8250 serial port support # +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_TXX9=y +CONFIG_HAS_TXX9_SERIAL=y +CONFIG_SERIAL_TXX9_CONSOLE=y +CONFIG_SERIAL_TXX9_STDSERIAL=y +# CONFIG_SERIAL_JSM is not set # CONFIG_UNIX98_PTYS is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -476,6 +503,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -503,6 +535,11 @@ # Graphics support # CONFIG_FB=y +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_SOFT_CURSOR is not set +# CONFIG_FB_MACMODES is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set # CONFIG_FB_CIRRUS is not set @@ -510,6 +547,7 @@ # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set +# CONFIG_FB_NVIDIA is not set # CONFIG_FB_RIVA is not set # CONFIG_FB_MATROX is not set # CONFIG_FB_RADEON_OLD is not set @@ -522,8 +560,10 @@ # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_SMIVGX is not set # CONFIG_FB_TRIDENT is not set # CONFIG_FB_E1356 is not set +# CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set # @@ -547,13 +587,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -578,6 +614,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -637,7 +677,6 @@ # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -666,7 +705,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/lasat200_defconfig linux-2.6.12.6/arch/mips/configs/lasat200_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/lasat200_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/lasat200_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:06 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:21 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,44 +57,67 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -CONFIG_LASAT=y -CONFIG_PICVUE=y -CONFIG_PICVUE_PROC=y -CONFIG_DS1603=y -CONFIG_LASAT_SYSCTL=y # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +CONFIG_LASAT=y # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +CONFIG_PICVUE=y +CONFIG_PICVUE_PROC=y +CONFIG_DS1603=y +CONFIG_LASAT_SYSCTL=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_MIPS_NILE4=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_MIPS_GT64120=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -117,6 +141,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -145,10 +180,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -176,8 +207,8 @@ # CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set @@ -372,7 +403,6 @@ # Networking options # # CONFIG_PACKET is not set -# CONFIG_NETLINK_DEV is not set CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -465,6 +495,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -521,19 +552,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -543,6 +561,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -563,6 +592,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -589,6 +619,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -622,7 +657,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -632,13 +666,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -669,6 +699,10 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -732,7 +766,6 @@ # CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -761,7 +794,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/malta_defconfig linux-2.6.12.6/arch/mips/configs/malta_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/malta_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/malta_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:53:14 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:22 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,33 +57,54 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set CONFIG_MIPS_MALTA=y # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y @@ -92,7 +114,10 @@ CONFIG_I8259=y CONFIG_MIPS_BONITO64=y CONFIG_MIPS_MSC=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_MIPS_BOARDS_GEN=y CONFIG_MIPS_GT64120=y CONFIG_SWAP_IO_SPACE=y @@ -120,10 +145,21 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y @@ -145,10 +181,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -323,18 +355,13 @@ # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set CONFIG_SCSI_QLA2XXX=m @@ -343,6 +370,7 @@ # CONFIG_SCSI_QLA2300 is not set # CONFIG_SCSI_QLA2322 is not set # CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set @@ -366,6 +394,8 @@ CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_EMC=m # # Fusion MPT device support @@ -392,7 +422,6 @@ # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -401,6 +430,7 @@ CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_FWMARK=y CONFIG_IP_ROUTE_MULTIPATH=y +# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y @@ -534,7 +564,7 @@ CONFIG_IP_NF_ARP_MANGLE=m # -# IPv6: Netfilter Configuration +# IPv6: Netfilter Configuration (EXPERIMENTAL) # CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m @@ -633,6 +663,7 @@ CONFIG_NET_QOS=y CONFIG_NET_ESTIMATOR=y CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_ROUTE=y @@ -643,6 +674,7 @@ # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_CLS_POLICE=y @@ -660,7 +692,6 @@ CONFIG_BONDING=m CONFIG_EQUALIZER=m CONFIG_TUN=m -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -715,6 +746,7 @@ # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -772,19 +804,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -# CONFIG_SERIO_RAW is not set - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -794,6 +813,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -814,6 +844,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -839,6 +870,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -872,7 +908,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -882,13 +917,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -929,7 +960,12 @@ # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# CONFIG_XFS_FS=m +CONFIG_XFS_EXPORT=y # CONFIG_XFS_RT is not set CONFIG_XFS_QUOTA=y CONFIG_XFS_SECURITY=y @@ -1078,7 +1114,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -1100,6 +1138,7 @@ CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_TWOFISH=m diff -Naur linux-2.6.12.6.orig/arch/mips/configs/mpc30x_defconfig linux-2.6.12.6/arch/mips/configs/mpc30x_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/mpc30x_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/mpc30x_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:07 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:22 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,48 +57,72 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_VR41XX=y -# CONFIG_NEC_CMBVR4133 is not set -# CONFIG_CASIO_E55 is not set -# CONFIG_IBM_WORKPAD is not set -# CONFIG_TANBAC_TB0226 is not set -# CONFIG_TANBAC_TB0229 is not set -CONFIG_VICTOR_MPC30X=y -# CONFIG_ZAO_CAPCELLA is not set -CONFIG_PCI_VR41XX=y -CONFIG_VRC4173=y -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +CONFIG_MACH_VR41XX=y +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_NEC_CMBVR4133 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +CONFIG_VICTOR_MPC30X=y +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_PCI_VR41XX=y +# CONFIG_GPIO_VR41XX is not set +CONFIG_VRC4173=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -121,6 +146,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -144,10 +180,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -252,7 +284,6 @@ # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -315,7 +346,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -350,6 +380,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -406,19 +437,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -428,6 +446,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -448,6 +477,8 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_VR41XX is not set +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -474,6 +505,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -507,7 +543,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -517,13 +552,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -549,6 +580,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -610,7 +645,6 @@ # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -639,7 +673,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -662,6 +698,7 @@ # CONFIG_CRYPTO_SHA256 is not set CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m # CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_BLOWFISH is not set CONFIG_CRYPTO_TWOFISH=y diff -Naur linux-2.6.12.6.orig/arch/mips/configs/ocelot_3_defconfig linux-2.6.12.6/arch/mips/configs/ocelot_3_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/ocelot_3_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/ocelot_3_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:07 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:23 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,7 +23,6 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y @@ -33,6 +30,9 @@ CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -42,6 +42,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,39 +58,62 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set CONFIG_MOMENCO_OCELOT_3=y -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y CONFIG_IRQ_MV64340=y @@ -118,6 +142,17 @@ # CONFIG_CPU_RM7000 is not set CONFIG_CPU_RM9000=y # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -149,10 +184,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -265,18 +296,13 @@ # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set CONFIG_SCSI_QLA2XXX=m @@ -285,6 +311,7 @@ # CONFIG_SCSI_QLA2300 is not set # CONFIG_SCSI_QLA2322 is not set # CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set @@ -320,7 +347,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -365,7 +391,7 @@ # CONFIG_IP_NF_ARPTABLES is not set # -# IPv6: Netfilter Configuration +# IPv6: Netfilter Configuration (EXPERIMENTAL) # # CONFIG_IP6_NF_QUEUE is not set # CONFIG_IP6_NF_IPTABLES is not set @@ -409,7 +435,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set CONFIG_TUN=m -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -439,7 +464,6 @@ # CONFIG_DGRS is not set # CONFIG_EEPRO100 is not set CONFIG_E100=y -# CONFIG_E100_NAPI is not set # CONFIG_FEALNX is not set # CONFIG_NATSEMI is not set # CONFIG_NE2K_PCI is not set @@ -465,6 +489,7 @@ # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set CONFIG_MV643XX_ETH=y CONFIG_MV643XX_ETH_0=y CONFIG_MV643XX_ETH_1=y @@ -530,19 +555,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -# CONFIG_SERIO_RAW is not set - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -552,6 +564,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -572,6 +595,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -597,6 +621,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -624,6 +653,11 @@ # Graphics support # CONFIG_FB=y +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_SOFT_CURSOR is not set +# CONFIG_FB_MACMODES is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_TILEBLITTING is not set # CONFIG_FB_CIRRUS is not set @@ -631,6 +665,7 @@ # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set +# CONFIG_FB_NVIDIA is not set # CONFIG_FB_RIVA is not set # CONFIG_FB_MATROX is not set # CONFIG_FB_RADEON_OLD is not set @@ -643,8 +678,10 @@ # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_SMIVGX is not set # CONFIG_FB_TRIDENT is not set # CONFIG_FB_E1356 is not set +# CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set # @@ -674,13 +711,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -714,7 +747,12 @@ # CONFIG_REISERFS_PROC_INFO is not set # CONFIG_REISERFS_FS_XATTR is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# CONFIG_XFS_FS=m +CONFIG_XFS_EXPORT=y # CONFIG_XFS_RT is not set # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_SECURITY is not set @@ -855,7 +893,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="ip=any root=nfs" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/ocelot_c_defconfig linux-2.6.12.6/arch/mips/configs/ocelot_c_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/ocelot_c_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/ocelot_c_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,11 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:07 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:23 2005 # CONFIG_MIPS=y -CONFIG_MIPS64=y -CONFIG_64BIT=y # # Code maturity level options @@ -13,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -24,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -40,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -49,38 +51,62 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -CONFIG_MOMENCO_OCELOT_C=y # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +CONFIG_MOMENCO_OCELOT_C=y +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_IRQ_MV64340=y CONFIG_PCI_MARVELL=y @@ -107,6 +133,17 @@ CONFIG_CPU_RM7000=y # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y +CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -134,10 +171,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -245,7 +278,6 @@ # Networking options # # CONFIG_PACKET is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -307,7 +339,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -342,6 +373,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # CONFIG_MV643XX_ETH is not set # @@ -399,19 +431,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -421,6 +440,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -441,6 +471,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -467,6 +498,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -500,7 +536,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -510,13 +545,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -542,6 +573,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -634,7 +669,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/ocelot_defconfig linux-2.6.12.6/arch/mips/configs/ocelot_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/ocelot_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/ocelot_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:08 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:24 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -50,39 +51,62 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set CONFIG_MOMENCO_OCELOT=y -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y CONFIG_MIPS_GT64120=y @@ -112,6 +136,17 @@ CONFIG_CPU_RM7000=y # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -139,10 +174,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -238,7 +269,6 @@ # Networking options # # CONFIG_PACKET is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -300,7 +330,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) @@ -362,18 +391,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -383,6 +400,16 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -428,6 +455,10 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -461,7 +492,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -475,10 +505,6 @@ # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -502,6 +528,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -594,7 +624,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/ocelot_g_defconfig linux-2.6.12.6/arch/mips/configs/ocelot_g_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/ocelot_g_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/ocelot_g_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,11 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:08 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:24 2005 # CONFIG_MIPS=y -CONFIG_MIPS64=y -CONFIG_64BIT=y # # Code maturity level options @@ -13,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -24,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -40,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -49,38 +51,62 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -CONFIG_MOMENCO_OCELOT_G=y -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +CONFIG_MOMENCO_OCELOT_G=y +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y CONFIG_PCI_MARVELL=y @@ -110,6 +136,17 @@ CONFIG_CPU_RM7000=y # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y +CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -137,10 +174,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -248,7 +281,6 @@ # Networking options # # CONFIG_PACKET is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -310,7 +342,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -346,6 +377,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -402,19 +434,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -424,6 +443,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -444,6 +474,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -470,6 +501,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -503,7 +539,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -513,13 +548,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -545,6 +576,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -637,7 +672,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/osprey_defconfig linux-2.6.12.6/arch/mips/configs/osprey_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/osprey_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/osprey_defconfig 1970-01-01 00:00:00.000000000 +0000 @@ -1,618 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:08 2005 -# -CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -CONFIG_KOBJECT_UEVENT=y -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_FUTEX=y -CONFIG_EPOLL=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -# CONFIG_TINY_SHMEM is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Machine selection -# -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_EV96100 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set -# CONFIG_DDB5477 is not set -CONFIG_NEC_OSPREY=y -# CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_VR4181=y - -# -# CPU selection -# -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -CONFIG_CPU_VR41XX=y -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -# CONFIG_CPU_ADVANCED is not set -CONFIG_CPU_HAS_SYNC=y -# CONFIG_PREEMPT is not set - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PC-card bridges -# - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_EXPORTFS=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="ip=bootp ether=46,0x03fe0300,eth0" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -CONFIG_LIBCRC32C=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y diff -Naur linux-2.6.12.6.orig/arch/mips/configs/pb1100_defconfig linux-2.6.12.6/arch/mips/configs/pb1100_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/pb1100_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/pb1100_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:08 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:25 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,55 +57,64 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +CONFIG_MIPS_PB1100=y +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -# CONFIG_SOC_AU1000 is not set -CONFIG_SOC_AU1100=y -# CONFIG_SOC_AU1500 is not set -# CONFIG_SOC_AU1550 is not set -# CONFIG_MIPS_PB1000 is not set -CONFIG_MIPS_PB1100=y -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1100=y +CONFIG_SOC_AU1X00=y CONFIG_SWAP_IO_SPACE=y # CONFIG_AU1X00_USB_DEVICE is not set CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -129,12 +139,21 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -# CONFIG_64BIT_PHYS_ADDR is not set +CONFIG_64BIT_PHYS_ADDR=y # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y @@ -170,6 +189,7 @@ CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set # # Device Drivers @@ -187,8 +207,8 @@ # CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set @@ -232,9 +252,7 @@ # # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_PB1100=y -CONFIG_MTD_PB1500_BOOT=y -CONFIG_MTD_PB1500_USER=y +CONFIG_MTD_ALCHEMY=y # # Self-contained MTD device drivers @@ -328,7 +346,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -406,7 +423,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) @@ -481,18 +497,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -502,6 +506,16 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -533,7 +547,8 @@ # Watchdog Cards # # CONFIG_WATCHDOG is not set -CONFIG_RTC=y +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set @@ -549,6 +564,10 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -582,7 +601,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -592,12 +610,9 @@ # # USB support # -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB is not set # # USB Gadget Support @@ -636,6 +651,10 @@ CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -771,7 +790,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -794,6 +815,7 @@ # CONFIG_CRYPTO_SHA256 is not set CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m # CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_BLOWFISH is not set CONFIG_CRYPTO_TWOFISH=y diff -Naur linux-2.6.12.6.orig/arch/mips/configs/pb1500_defconfig linux-2.6.12.6/arch/mips/configs/pb1500_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/pb1500_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/pb1500_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:09 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:25 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,55 +57,64 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +CONFIG_MIPS_PB1500=y +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -# CONFIG_SOC_AU1000 is not set -# CONFIG_SOC_AU1100 is not set -CONFIG_SOC_AU1500=y -# CONFIG_SOC_AU1550 is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -CONFIG_MIPS_PB1500=y -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y -CONFIG_DMA_COHERENT=y +CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1500=y +CONFIG_SOC_AU1X00=y # CONFIG_AU1X00_USB_DEVICE is not set CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -128,6 +138,15 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -177,6 +196,7 @@ CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set # # Device Drivers @@ -192,7 +212,76 @@ # # Memory Technology Devices (MTD) # -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_AMDSTD_RETRY=0 +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_ALCHEMY=y + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set # # Parallel port support @@ -323,7 +412,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -401,7 +489,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -437,6 +524,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -513,19 +601,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -535,6 +610,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # # CONFIG_VT is not set @@ -554,6 +640,7 @@ CONFIG_SERIAL_AU1X00_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -585,6 +672,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -612,7 +704,6 @@ # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -622,13 +713,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -667,6 +754,10 @@ CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -712,6 +803,8 @@ # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=m # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set @@ -800,7 +893,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -823,6 +918,7 @@ # CONFIG_CRYPTO_SHA256 is not set CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m # CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_BLOWFISH is not set CONFIG_CRYPTO_TWOFISH=y diff -Naur linux-2.6.12.6.orig/arch/mips/configs/pb1550_defconfig linux-2.6.12.6/arch/mips/configs/pb1550_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/pb1550_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/pb1550_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:09 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:26 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,56 +57,65 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +CONFIG_MIPS_PB1550=y +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -CONFIG_SOC_AU1X00=y -# CONFIG_SOC_AU1000 is not set -# CONFIG_SOC_AU1100 is not set -# CONFIG_SOC_AU1500 is not set -CONFIG_SOC_AU1550=y -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -CONFIG_MIPS_PB1550=y -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_MIPS_MTX1 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y -CONFIG_DMA_COHERENT=y +CONFIG_DMA_NONCOHERENT=y CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SOC_AU1550=y +CONFIG_SOC_AU1X00=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # @@ -128,6 +138,15 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -177,6 +196,7 @@ CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y +# CONFIG_PM is not set # # Device Drivers @@ -192,7 +212,76 @@ # # Memory Technology Devices (MTD) # -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_AMDSTD_RETRY=0 +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_ALCHEMY=y + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set # # Parallel port support @@ -323,7 +412,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -401,7 +489,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -437,6 +524,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -505,19 +593,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -527,6 +602,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # # CONFIG_VT is not set @@ -546,6 +632,7 @@ CONFIG_SERIAL_AU1X00_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -577,6 +664,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -604,7 +696,6 @@ # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -614,13 +705,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -659,6 +746,10 @@ CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -704,6 +795,8 @@ # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=m # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set @@ -792,7 +885,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -815,6 +910,7 @@ # CONFIG_CRYPTO_SHA256 is not set CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m # CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_BLOWFISH is not set CONFIG_CRYPTO_TWOFISH=y diff -Naur linux-2.6.12.6.orig/arch/mips/configs/rm200_defconfig linux-2.6.12.6/arch/mips/configs/rm200_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/rm200_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/rm200_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:09 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:26 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -26,14 +24,16 @@ # CONFIG_BSD_PROCESS_ACCT_V3 is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -43,6 +43,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -58,33 +59,54 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set CONFIG_SNI_RM200_PCI=y +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y @@ -93,7 +115,10 @@ CONFIG_DMA_NONCOHERENT=y CONFIG_GENERIC_ISA_DMA=y CONFIG_I8259=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_ARC32=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -122,6 +147,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -136,6 +172,7 @@ # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # +CONFIG_HW_HAS_EISA=y CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y @@ -150,11 +187,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# -CONFIG_PCMCIA_PROBE=y - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -175,7 +207,7 @@ # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=m # # Memory Technology Devices (MTD) @@ -187,11 +219,11 @@ # CONFIG_PARPORT=m CONFIG_PARPORT_PC=m -CONFIG_PARPORT_PC_CML1=m CONFIG_PARPORT_SERIAL=m # CONFIG_PARPORT_PC_FIFO is not set # CONFIG_PARPORT_PC_SUPERIO is not set -# CONFIG_PARPORT_OTHER is not set +CONFIG_PARPORT_NOT_PC=y +# CONFIG_PARPORT_GSC is not set CONFIG_PARPORT_1284=y # @@ -203,7 +235,6 @@ # Block devices # CONFIG_BLK_DEV_FD=m -# CONFIG_BLK_DEV_XD is not set CONFIG_PARIDE=m CONFIG_PARIDE_PARPORT=m @@ -296,17 +327,15 @@ # CONFIG_SCSI_SPI_ATTRS=y # CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m # # SCSI low-level drivers # # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_7000FASST is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set # CONFIG_SCSI_AIC7XXX_OLD is not set @@ -317,13 +346,9 @@ CONFIG_MEGARAID_MM=m CONFIG_MEGARAID_MAILBOX=m # CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_GENERIC_NCR5380 is not set # CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set # CONFIG_SCSI_IPS is not set @@ -343,7 +368,6 @@ # CONFIG_SCSI_PAS16 is not set # CONFIG_SCSI_PSI240I is not set # CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set CONFIG_SCSI_QLA2XXX=y @@ -352,11 +376,11 @@ # CONFIG_SCSI_QLA2300 is not set # CONFIG_SCSI_QLA2322 is not set # CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_SYM53C416 is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set @@ -383,6 +407,8 @@ CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_EMC=m # # Fusion MPT device support @@ -409,7 +435,6 @@ # CONFIG_PACKET=m CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=m CONFIG_UNIX=y CONFIG_NET_KEY=m CONFIG_INET=y @@ -515,7 +540,7 @@ CONFIG_IP_NF_ARP_MANGLE=m # -# IPv6: Netfilter Configuration +# IPv6: Netfilter Configuration (EXPERIMENTAL) # CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m @@ -566,7 +591,7 @@ CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m -# CONFIG_BRIDGE_EBT_ULOG is not set +CONFIG_BRIDGE_EBT_ULOG=m CONFIG_XFRM=y # CONFIG_XFRM_USER is not set @@ -610,6 +635,7 @@ CONFIG_NET_QOS=y CONFIG_NET_ESTIMATOR=y CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_ROUTE=y @@ -620,6 +646,7 @@ # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_CLS_POLICE=y @@ -645,8 +672,6 @@ CONFIG_MKISS=m CONFIG_6PACK=m CONFIG_BPQETHER=m -# CONFIG_DMASCC is not set -# CONFIG_SCC is not set # CONFIG_BAYCOM_SER_FDX is not set # CONFIG_BAYCOM_SER_HDX is not set # CONFIG_BAYCOM_PAR is not set @@ -659,7 +684,6 @@ CONFIG_BONDING=m CONFIG_EQUALIZER=m CONFIG_TUN=m -CONFIG_ETHERTAP=m # # ARCnet devices @@ -674,7 +698,6 @@ # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set @@ -695,7 +718,6 @@ # CONFIG_LP486E is not set # CONFIG_ETH16I is not set CONFIG_NE2000=m -# CONFIG_ZNET is not set # CONFIG_SEEQ8005 is not set CONFIG_NET_PCI=y CONFIG_PCNET32=y @@ -735,6 +757,7 @@ # CONFIG_SK98LIN is not set CONFIG_VIA_VELOCITY=m # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -793,20 +816,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -CONFIG_SERIO_PARKBD=m -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y @@ -827,6 +836,18 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_PARKBD=m +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -850,6 +871,7 @@ # Non-8250 serial port support # CONFIG_SERIAL_CORE=m +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -880,6 +902,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -919,7 +946,6 @@ CONFIG_VGA_CONSOLE=y # CONFIG_MDA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -929,6 +955,8 @@ # # USB support # +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB=m # CONFIG_USB_DEBUG is not set @@ -939,8 +967,6 @@ # CONFIG_USB_BANDWIDTH is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y # # USB Host Controller Drivers @@ -949,6 +975,8 @@ # CONFIG_USB_EHCI_SPLIT_ISO is not set # CONFIG_USB_EHCI_ROOT_HUB_TT is not set CONFIG_USB_OHCI_HCD=m +# CONFIG_USB_OHCI_BIG_ENDIAN is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_UHCI_HCD=m # CONFIG_USB_SL811_HCD is not set @@ -964,11 +992,10 @@ # CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_RW_DETECT is not set CONFIG_USB_STORAGE_DATAFAB=y CONFIG_USB_STORAGE_FREECOM=y CONFIG_USB_STORAGE_DPCM=y -CONFIG_USB_STORAGE_HP8200e=y +# CONFIG_USB_STORAGE_USBAT is not set CONFIG_USB_STORAGE_SDDR09=y CONFIG_USB_STORAGE_SDDR55=y CONFIG_USB_STORAGE_JUMPSHOT=y @@ -1045,6 +1072,7 @@ # USB Network Adapters # CONFIG_USB_AX8817X=y +CONFIG_USB_MON=m # # USB port drivers @@ -1056,9 +1084,11 @@ # CONFIG_USB_SERIAL=m CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRPRIME=m CONFIG_USB_SERIAL_BELKIN=m CONFIG_USB_SERIAL_WHITEHEAT=m CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +# CONFIG_USB_SERIAL_CP2101 is not set CONFIG_USB_SERIAL_CYPRESS_M8=m CONFIG_USB_SERIAL_EMPEG=m CONFIG_USB_SERIAL_FTDI_SIO=m @@ -1087,6 +1117,7 @@ CONFIG_USB_SERIAL_KOBIL_SCT=m CONFIG_USB_SERIAL_MCT_U232=m CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_HP4X=m CONFIG_USB_SERIAL_SAFE=m CONFIG_USB_SERIAL_SAFE_PADDED=y # CONFIG_USB_SERIAL_TI is not set @@ -1109,6 +1140,7 @@ CONFIG_USB_PHIDGETKIT=m CONFIG_USB_PHIDGETSERVO=m # CONFIG_USB_IDMOUSE is not set +CONFIG_USB_SISUSBVGA=m CONFIG_USB_TEST=m # @@ -1150,7 +1182,12 @@ CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# CONFIG_XFS_FS=m +CONFIG_XFS_EXPORT=y # CONFIG_XFS_RT is not set CONFIG_XFS_QUOTA=y CONFIG_XFS_SECURITY=y @@ -1328,7 +1365,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -1351,6 +1390,7 @@ CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_TWOFISH=m @@ -1365,7 +1405,7 @@ CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_MICHAEL_MIC=m # CONFIG_CRYPTO_CRC32C is not set -CONFIG_CRYPTO_TEST=m +# CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices diff -Naur linux-2.6.12.6.orig/arch/mips/configs/sb1250-swarm_defconfig linux-2.6.12.6/arch/mips/configs/sb1250-swarm_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/sb1250-swarm_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/sb1250-swarm_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:10 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:27 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,16 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=15 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_CPUSETS=y CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +42,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,32 +59,44 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -CONFIG_SIBYTE_SB1xxx_SOC=y +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set CONFIG_SIBYTE_SWARM=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set @@ -91,9 +105,11 @@ # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_UNKNOWN is not set -CONFIG_SIBYTE_BOARD=y +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_SIBYTE_SB1250=y +CONFIG_SIBYTE_SB1xxx_SOC=y CONFIG_CPU_SB1_PASS_1=y # CONFIG_CPU_SB1_PASS_2_1250 is not set # CONFIG_CPU_SB1_PASS_2_2 is not set @@ -107,13 +123,14 @@ # CONFIG_SIBYTE_BUS_WATCHER is not set # CONFIG_SIBYTE_SB1250_PROF is not set # CONFIG_SIBYTE_TBPROF is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_COHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_SWAP_IO_SPACE=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -138,6 +155,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set CONFIG_CPU_SB1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y +CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -145,12 +173,9 @@ # CONFIG_SIBYTE_DMA_PAGEOPS is not set CONFIG_CPU_HAS_PREFETCH=y CONFIG_SB1_PASS_1_WORKAROUNDS=y -# CONFIG_64BIT_PHYS_ADDR is not set -# CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y -# CONFIG_HIGHMEM is not set CONFIG_SMP=y CONFIG_NR_CPUS=2 # CONFIG_PREEMPT is not set @@ -170,10 +195,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -183,7 +204,12 @@ # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y +# CONFIG_BUILD_ELF64 is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +CONFIG_BINFMT_ELF32=y # # Device Drivers @@ -227,7 +253,6 @@ CONFIG_BLK_DEV_RAM_SIZE=9220 CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set @@ -263,7 +288,7 @@ # CONFIG_IDE_GENERIC=y # CONFIG_BLK_DEV_IDEPCI is not set -CONFIG_BLK_DEV_IDE_SWARM=y +# CONFIG_BLK_DEV_IDE_SWARM is not set # CONFIG_IDE_ARM is not set # CONFIG_BLK_DEV_IDEDMA is not set # CONFIG_IDEDMA_AUTO is not set @@ -303,7 +328,6 @@ # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -365,7 +389,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -401,6 +424,7 @@ CONFIG_NET_SB1250_MAC=y # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -445,25 +469,15 @@ # CONFIG_INPUT is not set # -# Userland interfaces -# - -# -# Input I/O drivers +# Hardware I/O ports # -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y CONFIG_SERIO=y # CONFIG_SERIO_I8042 is not set CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set # CONFIG_SERIO_PCIPS2 is not set # CONFIG_SERIO_LIBPS2 is not set CONFIG_SERIO_RAW=m - -# -# Input Device Drivers -# +# CONFIG_GAMEPORT is not set # # Character devices @@ -474,9 +488,10 @@ # CONFIG_CYCLADES is not set # CONFIG_MOXA_SMARTIO is not set # CONFIG_ISI is not set -# CONFIG_SYNCLINK is not set # CONFIG_SYNCLINKMP is not set # CONFIG_N_HDLC is not set +# CONFIG_SPECIALIX is not set +# CONFIG_SX is not set # CONFIG_STALDRV is not set CONFIG_SIBYTE_SB1250_DUART=y CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y @@ -489,6 +504,7 @@ # # Non-8250 serial port support # +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -515,6 +531,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -542,7 +563,6 @@ # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -552,13 +572,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -588,6 +604,10 @@ # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -649,7 +669,6 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -678,7 +697,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=15 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" # CONFIG_SB1XXX_CORELIS is not set @@ -702,6 +723,7 @@ CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_BLOWFISH=y CONFIG_CRYPTO_TWOFISH=y diff -Naur linux-2.6.12.6.orig/arch/mips/configs/sead_defconfig linux-2.6.12.6/arch/mips/configs/sead_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/sead_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/sead_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:10 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:27 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,22 +11,25 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" -CONFIG_SWAP=y -# CONFIG_SYSVIPC is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -39,6 +39,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -48,39 +49,63 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set CONFIG_MIPS_SEAD=y +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_BOARDS_GEN=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -105,6 +130,16 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -127,10 +162,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -179,9 +210,7 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_CDROM_PKTCDVD is not set # # IO Schedulers @@ -237,47 +266,18 @@ # # Input device support # -CONFIG_INPUT=y +# CONFIG_INPUT is not set # -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input I/O drivers +# Hardware I/O ports # +# CONFIG_SERIO is not set # CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set # # Character devices # -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y +# CONFIG_VT is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -293,7 +293,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_UNIX98_PTYS is not set +CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -318,6 +318,10 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -346,13 +350,6 @@ # CONFIG_FB is not set # -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# # Sound # # CONFIG_SOUND is not set @@ -364,10 +361,6 @@ # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -386,15 +379,15 @@ # File systems # CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set -CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -423,6 +416,7 @@ CONFIG_PROC_KCORE=y CONFIG_SYSFS=y # CONFIG_DEVFS_FS is not set +# CONFIG_DEVPTS_FS_XATTR is not set # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y @@ -447,8 +441,18 @@ # # Partition Types # -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +# CONFIG_MSDOS_PARTITION is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_EFI_PARTITION is not set # # Native Language Support @@ -463,15 +467,16 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" # # Security options # -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_KEYS is not set # CONFIG_SECURITY is not set # diff -Naur linux-2.6.12.6.orig/arch/mips/configs/tb0226_defconfig linux-2.6.12.6/arch/mips/configs/tb0226_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/tb0226_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/tb0226_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:12 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:28 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,46 +57,70 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_VR41XX=y -# CONFIG_NEC_CMBVR4133 is not set -# CONFIG_CASIO_E55 is not set -# CONFIG_IBM_WORKPAD is not set -CONFIG_TANBAC_TB0226=y -# CONFIG_TANBAC_TB0229 is not set -# CONFIG_VICTOR_MPC30X is not set -# CONFIG_ZAO_CAPCELLA is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +CONFIG_MACH_VR41XX=y +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_NEC_CMBVR4133 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_IBM_WORKPAD is not set +CONFIG_TANBAC_TB0226=y +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +# CONFIG_GPIO_VR41XX is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -119,6 +144,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -140,10 +176,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -295,7 +327,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=m CONFIG_UNIX=y # CONFIG_NET_KEY is not set CONFIG_INET=y @@ -303,6 +334,7 @@ CONFIG_IP_ADVANCED_ROUTER=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y +# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y # CONFIG_IP_PNP_DHCP is not set @@ -361,7 +393,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) @@ -430,18 +461,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -451,6 +470,16 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -471,6 +500,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_VR41XX is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -496,6 +526,10 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -523,8 +557,14 @@ # Graphics support # CONFIG_FB=y +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_SOFT_CURSOR is not set +# CONFIG_FB_MACMODES is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set +# CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set # @@ -562,10 +602,6 @@ # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -589,6 +625,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set CONFIG_ROMFS_FS=m @@ -731,7 +771,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/tb0229_defconfig linux-2.6.12.6/arch/mips/configs/tb0229_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/tb0229_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/tb0229_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:12 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:28 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,49 +57,72 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_VR41XX=y -# CONFIG_NEC_CMBVR4133 is not set -# CONFIG_CASIO_E55 is not set -# CONFIG_IBM_WORKPAD is not set -# CONFIG_TANBAC_TB0226 is not set -CONFIG_TANBAC_TB0229=y -CONFIG_TANBAC_TB0219=y -# CONFIG_VICTOR_MPC30X is not set -# CONFIG_ZAO_CAPCELLA is not set -CONFIG_PCI_VR41XX=y -# CONFIG_VRC4173 is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +CONFIG_MACH_VR41XX=y +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_NEC_CMBVR4133 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_TANBAC_TB0226 is not set +CONFIG_TANBAC_TB0229=y +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_PCI_VR41XX=y +# CONFIG_GPIO_VR41XX is not set +# CONFIG_VRC4173 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -122,6 +146,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -145,10 +180,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set @@ -256,7 +287,6 @@ # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=m CONFIG_UNIX=y # CONFIG_NET_KEY is not set CONFIG_INET=y @@ -264,6 +294,7 @@ CONFIG_IP_ADVANCED_ROUTER=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y +# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y # CONFIG_IP_PNP_DHCP is not set @@ -323,7 +354,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -378,6 +408,7 @@ # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) @@ -444,19 +475,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -466,6 +484,17 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -486,6 +515,8 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_VR41XX is not set +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -504,6 +535,7 @@ # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set +CONFIG_TANBAC_TB0219=y # # Ftape, the floppy tape device driver @@ -512,6 +544,11 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# # I2C support # # CONFIG_I2C is not set @@ -545,7 +582,6 @@ # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -555,13 +591,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -596,7 +628,12 @@ # CONFIG_JFS_SECURITY is not set # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set + +# +# XFS support +# CONFIG_XFS_FS=y +CONFIG_XFS_EXPORT=y # CONFIG_XFS_RT is not set CONFIG_XFS_QUOTA=y # CONFIG_XFS_SECURITY is not set @@ -743,7 +780,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="mem=64M console=ttyS0,38400 ip=bootp root=/dev/nfs" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/workpad_defconfig linux-2.6.12.6/arch/mips/configs/workpad_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/workpad_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/workpad_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:12 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:29 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,13 +23,15 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,47 +57,71 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_VR41XX=y -# CONFIG_NEC_CMBVR4133 is not set -# CONFIG_CASIO_E55 is not set -CONFIG_IBM_WORKPAD=y -# CONFIG_TANBAC_TB0226 is not set -# CONFIG_TANBAC_TB0229 is not set -# CONFIG_VICTOR_MPC30X is not set -# CONFIG_ZAO_CAPCELLA is not set -CONFIG_VRC4171=y -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +CONFIG_MACH_VR41XX=y +# CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_NEC_CMBVR4133 is not set +# CONFIG_CASIO_E55 is not set +CONFIG_IBM_WORKPAD=y +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +# CONFIG_GPIO_VR41XX is not set +CONFIG_VRC4171=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -120,6 +145,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -140,11 +176,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# -CONFIG_PCMCIA_PROBE=y - -# # PCI Hotplug Support # @@ -185,7 +216,6 @@ # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set @@ -270,7 +300,6 @@ # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -330,7 +359,6 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set # # ARCnet devices @@ -343,7 +371,6 @@ CONFIG_NET_ETHERNET=y # CONFIG_MII is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set # CONFIG_AT1700 is not set @@ -408,18 +435,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -429,6 +444,16 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -449,6 +474,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_VR41XX is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -487,6 +513,10 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -521,7 +551,6 @@ # CONFIG_VGA_CONSOLE is not set # CONFIG_MDA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -535,10 +564,6 @@ # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -566,6 +591,10 @@ # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -657,7 +686,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" diff -Naur linux-2.6.12.6.orig/arch/mips/configs/yosemite_defconfig linux-2.6.12.6/arch/mips/configs/yosemite_defconfig --- linux-2.6.12.6.orig/arch/mips/configs/yosemite_defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/configs/yosemite_defconfig 2005-10-02 23:47:35.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:13 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:29 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ # CONFIG_EXPERIMENTAL is not set CONFIG_CLEAN_COMPILE=y CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -24,15 +22,18 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +# CONFIG_CPUSETS is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -42,6 +43,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -56,34 +58,63 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -CONFIG_PMC_YOSEMITE=y -# CONFIG_HYPERTRANSPORT is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +CONFIG_PMC_YOSEMITE=y # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_HYPERTRANSPORT is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_COHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y CONFIG_IRQ_CPU_RM9K=y @@ -110,6 +141,17 @@ # CONFIG_CPU_RM7000 is not set CONFIG_CPU_RM9000=y # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -132,6 +174,7 @@ CONFIG_PCI=y CONFIG_PCI_LEGACY_PROC=y CONFIG_PCI_NAMES=y +# CONFIG_PCI_DEBUG is not set CONFIG_MMU=y # @@ -140,10 +183,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -247,7 +286,6 @@ # CONFIG_PACKET=m CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=m CONFIG_UNIX=y # CONFIG_NET_KEY is not set CONFIG_INET=y @@ -265,7 +303,14 @@ # CONFIG_INET_IPCOMP is not set CONFIG_INET_TUNNEL=m CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set +CONFIG_IP_TCPDIAG_IPV6=y +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_TUNNEL=m # CONFIG_NETFILTER is not set CONFIG_XFRM=y CONFIG_XFRM_USER=m @@ -329,6 +374,7 @@ # CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set CONFIG_TITAN_GE=y # @@ -371,20 +417,10 @@ # CONFIG_INPUT is not set # -# Userland interfaces -# - +# Hardware I/O ports # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y # CONFIG_SERIO is not set -# CONFIG_SERIO_I8042 is not set - -# -# Input Device Drivers -# +# CONFIG_GAMEPORT is not set # # Character devices @@ -405,6 +441,7 @@ # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -432,6 +469,10 @@ # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -459,7 +500,6 @@ # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -469,13 +509,9 @@ # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -500,6 +536,10 @@ # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -552,7 +592,6 @@ # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set @@ -573,8 +612,10 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set CONFIG_DEBUG_KERNEL=y # CONFIG_MAGIC_SYSRQ is not set +CONFIG_LOG_BUF_SHIFT=14 # CONFIG_SCHEDSTATS is not set # CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_SPINLOCK is not set @@ -599,7 +640,31 @@ # # Cryptographic options # -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_TEST=m # # Hardware crypto devices @@ -610,6 +675,8 @@ # # CONFIG_CRC_CCITT is not set # CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y diff -Naur linux-2.6.12.6.orig/arch/mips/ddb5xxx/Kconfig linux-2.6.12.6/arch/mips/ddb5xxx/Kconfig --- linux-2.6.12.6.orig/arch/mips/ddb5xxx/Kconfig 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/ddb5xxx/Kconfig 2005-10-02 23:47:35.000000000 +0000 @@ -0,0 +1,4 @@ +config DDB5477_BUS_FREQUENCY + int "bus frequency (in kHZ, 0 for auto-detect)" + depends on DDB5477 + default 0 diff -Naur linux-2.6.12.6.orig/arch/mips/ddb5xxx/ddb5074/nile4_pic.c linux-2.6.12.6/arch/mips/ddb5xxx/ddb5074/nile4_pic.c --- linux-2.6.12.6.orig/arch/mips/ddb5xxx/ddb5074/nile4_pic.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/ddb5xxx/ddb5074/nile4_pic.c 2005-10-02 23:47:35.000000000 +0000 @@ -209,14 +209,13 @@ #define nile4_irq_shutdown nile4_disable_irq static hw_irq_controller nile4_irq_controller = { - "nile4", - nile4_irq_startup, - nile4_irq_shutdown, - nile4_enable_irq, - nile4_disable_irq, - nile4_ack_irq, - nile4_irq_end, - NULL + .typename = "nile4", + .startup = nile4_irq_startup, + .shutdown = nile4_irq_shutdown, + .enable = nile4_enable_irq, + .disable = nile4_disable_irq, + .ack = nile4_ack_irq, + .end = nile4_irq_end, }; void nile4_irq_setup(u32 base) { diff -Naur linux-2.6.12.6.orig/arch/mips/ddb5xxx/ddb5074/setup.c linux-2.6.12.6/arch/mips/ddb5xxx/ddb5074/setup.c --- linux-2.6.12.6.orig/arch/mips/ddb5xxx/ddb5074/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/ddb5xxx/ddb5074/setup.c 2005-10-02 23:47:35.000000000 +0000 @@ -85,7 +85,7 @@ -static void __init ddb5074_setup(void) +void __init plat_setup(void) { set_io_port_base(NILE4_PCI_IO_BASE); isa_slot_offset = NILE4_PCI_MEM_BASE; @@ -106,8 +106,6 @@ panic_timeout = 180; } -early_initcall(ddb5074_setup); - #define USE_NILE4_SERIAL 0 #if USE_NILE4_SERIAL diff -Naur linux-2.6.12.6.orig/arch/mips/ddb5xxx/ddb5476/setup.c linux-2.6.12.6/arch/mips/ddb5xxx/ddb5476/setup.c --- linux-2.6.12.6.orig/arch/mips/ddb5xxx/ddb5476/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/ddb5xxx/ddb5476/setup.c 2005-10-02 23:47:35.000000000 +0000 @@ -124,7 +124,7 @@ static void ddb5476_board_init(void); -static void __init ddb5476_setup(void) +void __init plat_setup(void) { set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE)); @@ -158,8 +158,6 @@ ddb5476_board_init(); } -early_initcall(ddb5476_setup); - /* * We don't trust bios. We essentially does hardware re-initialization * as complete as possible, as far as we know we can safely do. diff -Naur linux-2.6.12.6.orig/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c linux-2.6.12.6/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c --- linux-2.6.12.6.orig/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c 2005-10-02 23:47:35.000000000 +0000 @@ -53,14 +53,13 @@ } static hw_irq_controller vrc5476_irq_controller = { - "vrc5476", - vrc5476_irq_startup, - vrc5476_irq_shutdown, - vrc5476_irq_enable, - vrc5476_irq_disable, - vrc5476_irq_ack, - vrc5476_irq_end, - NULL /* no affinity stuff for UP */ + .typename = "vrc5476", + .startup = vrc5476_irq_startup, + .shutdown = vrc5476_irq_shutdown, + .enable = vrc5476_irq_enable, + .disable = vrc5476_irq_disable, + .ack = vrc5476_irq_ack, + .end = vrc5476_irq_end }; void __init diff -Naur linux-2.6.12.6.orig/arch/mips/ddb5xxx/ddb5477/irq_5477.c linux-2.6.12.6/arch/mips/ddb5xxx/ddb5477/irq_5477.c --- linux-2.6.12.6.orig/arch/mips/ddb5xxx/ddb5477/irq_5477.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/ddb5xxx/ddb5477/irq_5477.c 2005-10-02 23:47:35.000000000 +0000 @@ -90,14 +90,13 @@ } hw_irq_controller vrc5477_irq_controller = { - "vrc5477_irq", - vrc5477_irq_startup, - vrc5477_irq_shutdown, - vrc5477_irq_enable, - vrc5477_irq_disable, - vrc5477_irq_ack, - vrc5477_irq_end, - NULL /* no affinity stuff for UP */ + .typename = "vrc5477_irq", + .startup = vrc5477_irq_startup, + .shutdown = vrc5477_irq_shutdown, + .enable = vrc5477_irq_enable, + .disable = vrc5477_irq_disable, + .ack = vrc5477_irq_ack, + .end = vrc5477_irq_end }; void __init vrc5477_irq_init(u32 irq_base) diff -Naur linux-2.6.12.6.orig/arch/mips/ddb5xxx/ddb5477/setup.c linux-2.6.12.6/arch/mips/ddb5xxx/ddb5477/setup.c --- linux-2.6.12.6.orig/arch/mips/ddb5xxx/ddb5477/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/ddb5xxx/ddb5477/setup.c 2005-10-02 23:47:35.000000000 +0000 @@ -170,7 +170,7 @@ extern struct pci_controller ddb5477_ext_controller; extern struct pci_controller ddb5477_io_controller; -static int ddb5477_setup(void) +static void ddb5477_setup(void) { /* initialize board - we don't trust the loader */ ddb5477_board_init(); @@ -193,12 +193,8 @@ register_pci_controller (&ddb5477_ext_controller); register_pci_controller (&ddb5477_io_controller); - - return 0; } -early_initcall(ddb5477_setup); - static void __init ddb5477_board_init(void) { /* ----------- setup PDARs ------------ */ diff -Naur linux-2.6.12.6.orig/arch/mips/dec/Makefile linux-2.6.12.6/arch/mips/dec/Makefile --- linux-2.6.12.6.orig/arch/mips/dec/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/dec/Makefile 2005-10-02 23:47:36.000000000 +0000 @@ -2,8 +2,8 @@ # Makefile for the DECstation family specific parts of the kernel # -obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn02-irq.o reset.o \ - setup.o time.o +obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \ + kn02-irq.o kn02xa-berr.o reset.o setup.o time.o obj-$(CONFIG_PROM_CONSOLE) += promcon.o obj-$(CONFIG_CPU_HAS_WB) += wbflush.o diff -Naur linux-2.6.12.6.orig/arch/mips/dec/ecc-berr.c linux-2.6.12.6/arch/mips/dec/ecc-berr.c --- linux-2.6.12.6.orig/arch/mips/dec/ecc-berr.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/dec/ecc-berr.c 2005-10-02 23:47:36.000000000 +0000 @@ -6,7 +6,7 @@ * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03), * 5900/260 (KN05) systems. * - * Copyright (c) 2003 Maciej W. Rozycki + * Copyright (c) 2003, 2005 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -15,6 +15,7 @@ */ #include +#include #include #include #include @@ -57,7 +58,7 @@ const char *kind, *agent, *cycle, *event; const char *status = "", *xbit = "", *fmt = ""; - dma_addr_t address; + unsigned long address; u16 syn = 0, sngl; int i = 0; @@ -66,7 +67,7 @@ u32 chksyn = *kn0x_chksyn; int action = MIPS_BE_FATAL; - /* For non-ECC ack ASAP, so any subsequent errors get caught. */ + /* For non-ECC ack ASAP, so that any subsequent errors get caught. */ if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID) dec_ecc_be_ack(); @@ -74,7 +75,7 @@ if (!(erraddr & KN0X_EAR_VALID)) { /* No idea what happened. */ - printk(KERN_ALERT "Unidentified bus error %s.\n", kind); + printk(KERN_ALERT "Unidentified bus error %s\n", kind); return action; } @@ -126,7 +127,7 @@ /* Ack now, no rewrite will happen. */ dec_ecc_be_ack(); - fmt = KERN_ALERT "%s" "invalid.\n"; + fmt = KERN_ALERT "%s" "invalid\n"; } else { sngl = syn & KN0X_ESR_SNGLO; syn &= KN0X_ESR_SYNLO; @@ -144,7 +145,8 @@ } else if (!sngl) { status = dbestr; } else { - volatile u32 *ptr = (void *)KSEG1ADDR(address); + volatile u32 *ptr = + (void *)CKSEG1ADDR(address); *ptr = *ptr; /* Rewrite. */ iob(); @@ -160,12 +162,12 @@ if (syn == 0x01) { fmt = KERN_ALERT "%s" "%#04x -- %s bit error " - "at check bit C%s.\n"; + "at check bit C%s\n"; xbit = "X"; } else { fmt = KERN_ALERT "%s" "%#04x -- %s bit error " - "at check bit C%s%u.\n"; + "at check bit C%s%u\n"; } i = syn >> 2; } else { @@ -175,16 +177,16 @@ if (i < 32) fmt = KERN_ALERT "%s" "%#04x -- %s bit error " - "at data bit D%s%u.\n"; + "at data bit D%s%u\n"; else fmt = KERN_ALERT "%s" - "%#04x -- %s bit error.\n"; + "%#04x -- %s bit error\n"; } } } if (action != MIPS_BE_FIXUP) - printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx.\n", + printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n", kind, agent, cycle, event, address); if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR) @@ -203,11 +205,11 @@ int action = dec_ecc_be_backend(regs, 0, 1); if (action == MIPS_BE_DISCARD) - return IRQ_NONE; + return IRQ_HANDLED; /* - * FIXME: Find affected processes and kill them, otherwise we - * must die. + * FIXME: Find the affected processes and kill them, otherwise + * we must die. * * The interrupt is asynchronously delivered thus EPC and RA * may be irrelevant, but are printed for a reference. @@ -225,16 +227,16 @@ */ static inline void dec_kn02_be_init(void) { - volatile u32 *csr = (void *)KN02_CSR_BASE; + volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); unsigned long flags; - kn0x_erraddr = (void *)(KN02_SLOT_BASE + KN02_ERRADDR); - kn0x_chksyn = (void *)(KN02_SLOT_BASE + KN02_CHKSYN); + kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); + kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); spin_lock_irqsave(&kn02_lock, flags); /* Preset write-only bits of the Control Register cache. */ - cached_kn02_csr = *csr | KN03_CSR_LEDS; + cached_kn02_csr = *csr | KN02_CSR_LEDS; /* Set normal ECC detection and generation. */ cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN); @@ -248,11 +250,11 @@ static inline void dec_kn03_be_init(void) { - volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR); - volatile u32 *mbcs = (void *)(KN03_SLOT_BASE + KN05_MB_CSR); + volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); + volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); - kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); - kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); + kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR); + kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN); /* * Set normal ECC detection and generation, enable ECC correction. @@ -264,7 +266,7 @@ *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) | KN03_MCR_CORRECT; if (current_cpu_data.cputype == CPU_R4400SC) - *mbcs |= KN05_MB_CSR_EE; + *mbcs |= KN4K_MB_CSR_EE; fast_iob(); } diff -Naur linux-2.6.12.6.orig/arch/mips/dec/int-handler.S linux-2.6.12.6/arch/mips/dec/int-handler.S --- linux-2.6.12.6.orig/arch/mips/dec/int-handler.S 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/dec/int-handler.S 2005-10-02 23:47:36.000000000 +0000 @@ -2,9 +2,9 @@ * arch/mips/dec/int-handler.S * * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen - * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki * - * Written by Ralf Baechle and Andreas Busse, modified for DECStation + * Written by Ralf Baechle and Andreas Busse, modified for DECstation * support by Paul Antoine and Harald Koerfgen. * * completly rewritten: @@ -14,11 +14,12 @@ * by Maciej W. Rozycki. */ #include + +#include #include -#include #include +#include #include -#include #include #include @@ -28,11 +29,14 @@ #include #include +#define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR) +#define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL) +#define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL) .text .set noreorder /* - * decstation_handle_int: Interrupt handler for DECStations + * decstation_handle_int: Interrupt handler for DECstations * * We follow the model in the Indy interrupt code by David Miller, where he * says: a lot of complication here is taken away because: @@ -48,7 +52,7 @@ * 3) Linux only thinks in terms of all IRQs on or all IRQs * off, nothing in between like BSD spl() brain-damage. * - * Furthermore, the IRQs on the DECStations look basically (barring + * Furthermore, the IRQs on the DECstations look basically (barring * software IRQs which we don't use at all) like... * * DS2100/3100's, aka kn01, aka Pmax: @@ -61,7 +65,7 @@ * 3 Lance Ethernet * 4 DZ11 serial * 5 RTC - * 6 Memory Controller + * 6 Memory Controller & Video * 7 FPU * * DS5000/200, aka kn02, aka 3max: diff -Naur linux-2.6.12.6.orig/arch/mips/dec/kn01-berr.c linux-2.6.12.6/arch/mips/dec/kn01-berr.c --- linux-2.6.12.6.orig/arch/mips/dec/kn01-berr.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/dec/kn01-berr.c 2005-10-02 23:47:36.000000000 +0000 @@ -0,0 +1,201 @@ +/* + * linux/arch/mips/dec/kn01-berr.c + * + * Bus error event handling code for DECstation/DECsystem 3100 + * and 2100 (KN01) systems equipped with parity error detection + * logic. + * + * Copyright (c) 2005 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + + +/* CP0 hazard avoidance. */ +#define BARRIER \ + __asm__ __volatile__( \ + ".set push\n\t" \ + ".set noreorder\n\t" \ + "nop\n\t" \ + ".set pop\n\t") + +/* + * Bits 7:0 of the Control Register are write-only -- the + * corresponding bits of the Status Register have a different + * meaning. Hence we use a cache. It speeds up things a bit + * as well. + * + * There is no default value -- it has to be initialized. + */ +u16 cached_kn01_csr; +DEFINE_SPINLOCK(kn01_lock); + + +static inline void dec_kn01_be_ack(void) +{ + volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); + unsigned long flags; + + spin_lock_irqsave(&kn01_lock, flags); + + *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */ + iob(); + + spin_unlock_irqrestore(&kn01_lock, flags); +} + +static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker) +{ + volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + + KN01_ERRADDR); + + static const char excstr[] = "exception"; + static const char intstr[] = "interrupt"; + static const char cpustr[] = "CPU"; + static const char mreadstr[] = "memory read"; + static const char readstr[] = "read"; + static const char writestr[] = "write"; + static const char timestr[] = "timeout"; + static const char paritystr[] = "parity error"; + + int data = regs->cp0_cause & 4; + unsigned int __user *pc = (unsigned int __user *)regs->cp0_epc + + ((regs->cp0_cause & CAUSEF_BD) != 0); + union mips_instruction insn; + unsigned long entrylo, offset; + long asid, entryhi, vaddr; + + const char *kind, *agent, *cycle, *event; + unsigned long address; + + u32 erraddr = *kn01_erraddr; + int action = MIPS_BE_FATAL; + + /* Ack ASAP, so that any subsequent errors get caught. */ + dec_kn01_be_ack(); + + kind = invoker ? intstr : excstr; + + agent = cpustr; + + if (invoker) + address = erraddr; + else { + /* Bloody hardware doesn't record the address for reads... */ + if (data) { + /* This never faults. */ + __get_user(insn.word, pc); + vaddr = regs->regs[insn.i_format.rs] + + insn.i_format.simmediate; + } else + vaddr = (long)pc; + if (KSEGX(vaddr) == CKSEG0 || KSEGX(vaddr) == CKSEG1) + address = CPHYSADDR(vaddr); + else { + /* Peek at what physical address the CPU used. */ + asid = read_c0_entryhi(); + entryhi = asid & (PAGE_SIZE - 1); + entryhi |= vaddr & ~(PAGE_SIZE - 1); + write_c0_entryhi(entryhi); + BARRIER; + tlb_probe(); + /* No need to check for presence. */ + tlb_read(); + entrylo = read_c0_entrylo0(); + write_c0_entryhi(asid); + offset = vaddr & (PAGE_SIZE - 1); + address = (entrylo & ~(PAGE_SIZE - 1)) | offset; + } + } + + /* Treat low 256MB as memory, high -- as I/O. */ + if (address < 0x10000000) { + cycle = mreadstr; + event = paritystr; + } else { + cycle = invoker ? writestr : readstr; + event = timestr; + } + + if (is_fixup) + action = MIPS_BE_FIXUP; + + if (action != MIPS_BE_FIXUP) + printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n", + kind, agent, cycle, event, address); + + return action; +} + +int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup) +{ + return dec_kn01_be_backend(regs, is_fixup, 0); +} + +irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id, + struct pt_regs *regs) +{ + volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); + int action; + + if (!(*csr & KN01_CSR_MEMERR)) + return IRQ_NONE; /* Must have been video. */ + + action = dec_kn01_be_backend(regs, 0, 1); + + if (action == MIPS_BE_DISCARD) + return IRQ_HANDLED; + + /* + * FIXME: Find the affected processes and kill them, otherwise + * we must die. + * + * The interrupt is asynchronously delivered thus EPC and RA + * may be irrelevant, but are printed for a reference. + */ + printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n", + regs->cp0_epc, regs->regs[31]); + die("Unrecoverable bus error", regs); +} + + +void __init dec_kn01_be_init(void) +{ + volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); + unsigned long flags; + + spin_lock_irqsave(&kn01_lock, flags); + + /* Preset write-only bits of the Control Register cache. */ + cached_kn01_csr = *csr; + cached_kn01_csr &= KN01_CSR_STATUS | KN01_CSR_PARDIS | KN01_CSR_TXDIS; + cached_kn01_csr |= KN01_CSR_LEDS; + + /* Enable parity error detection. */ + cached_kn01_csr &= ~KN01_CSR_PARDIS; + *csr = cached_kn01_csr; + iob(); + + spin_unlock_irqrestore(&kn01_lock, flags); + + /* Clear any leftover errors from the firmware. */ + dec_kn01_be_ack(); +} diff -Naur linux-2.6.12.6.orig/arch/mips/dec/kn02-irq.c linux-2.6.12.6/arch/mips/dec/kn02-irq.c --- linux-2.6.12.6.orig/arch/mips/dec/kn02-irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/dec/kn02-irq.c 2005-10-02 23:47:36.000000000 +0000 @@ -4,7 +4,7 @@ * DECstation 5000/200 (KN02) Control and Status Register * interrupts. * - * Copyright (c) 2002, 2003 Maciej W. Rozycki + * Copyright (c) 2002, 2003, 2005 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -37,7 +37,8 @@ static inline void unmask_kn02_irq(unsigned int irq) { - volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; + volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + + KN02_CSR); cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16)); *csr = cached_kn02_csr; @@ -45,7 +46,8 @@ static inline void mask_kn02_irq(unsigned int irq) { - volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; + volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + + KN02_CSR); cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16)); *csr = cached_kn02_csr; @@ -105,13 +107,14 @@ void __init init_kn02_irqs(int base) { - volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; + volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + + KN02_CSR); unsigned long flags; int i; /* Mask interrupts. */ spin_lock_irqsave(&kn02_lock, flags); - cached_kn02_csr &= ~KN03_CSR_IOINTEN; + cached_kn02_csr &= ~KN02_CSR_IOINTEN; *csr = cached_kn02_csr; iob(); spin_unlock_irqrestore(&kn02_lock, flags); diff -Naur linux-2.6.12.6.orig/arch/mips/dec/kn02xa-berr.c linux-2.6.12.6/arch/mips/dec/kn02xa-berr.c --- linux-2.6.12.6.orig/arch/mips/dec/kn02xa-berr.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/dec/kn02xa-berr.c 2005-10-02 23:47:36.000000000 +0000 @@ -0,0 +1,139 @@ +/* + * linux/arch/mips/dec/kn02xa-berr.c + * + * Bus error event handling code for 5000-series systems equipped + * with parity error detection logic, i.e. DECstation/DECsystem + * 5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal + * DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50 + * (KN04-CA) systems. + * + * Copyright (c) 2005 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +static inline void dec_kn02xa_be_ack(void) +{ + volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER); + volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR); + + *mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */ + *mem_intr = 0; /* Any write clears the bus IRQ. */ + iob(); +} + +static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup, + int invoker) +{ + volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER); + volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR); + + static const char excstr[] = "exception"; + static const char intstr[] = "interrupt"; + static const char cpustr[] = "CPU"; + static const char mreadstr[] = "memory read"; + static const char readstr[] = "read"; + static const char writestr[] = "write"; + static const char timestr[] = "timeout"; + static const char paritystr[] = "parity error"; + static const char lanestat[][4] = { " OK", "BAD" }; + + const char *kind, *agent, *cycle, *event; + unsigned long address; + + u32 mer = *kn02xa_mer; + u32 ear = *kn02xa_ear; + int action = MIPS_BE_FATAL; + + /* Ack ASAP, so that any subsequent errors get caught. */ + dec_kn02xa_be_ack(); + + kind = invoker ? intstr : excstr; + + /* No DMA errors? */ + agent = cpustr; + + address = ear & KN02XA_EAR_ADDRESS; + + /* Low 256MB is decoded as memory, high -- as TC. */ + if (address < 0x10000000) { + cycle = mreadstr; + event = paritystr; + } else { + cycle = invoker ? writestr : readstr; + event = timestr; + } + + if (is_fixup) + action = MIPS_BE_FIXUP; + + if (action != MIPS_BE_FIXUP) + printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n", + kind, agent, cycle, event, address); + + if (action != MIPS_BE_FIXUP && address < 0x10000000) + printk(KERN_ALERT " Byte lane status %#3x -- " + "#3: %s, #2: %s, #1: %s, #0: %s\n", + (mer & KN02XA_MER_BYTERR) >> 8, + lanestat[(mer & KN02XA_MER_BYTERR_3) != 0], + lanestat[(mer & KN02XA_MER_BYTERR_2) != 0], + lanestat[(mer & KN02XA_MER_BYTERR_1) != 0], + lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]); + + return action; +} + +int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup) +{ + return dec_kn02xa_be_backend(regs, is_fixup, 0); +} + +irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id, + struct pt_regs *regs) +{ + int action = dec_kn02xa_be_backend(regs, 0, 1); + + if (action == MIPS_BE_DISCARD) + return IRQ_HANDLED; + + /* + * FIXME: Find the affected processes and kill them, otherwise + * we must die. + * + * The interrupt is asynchronously delivered thus EPC and RA + * may be irrelevant, but are printed for a reference. + */ + printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n", + regs->cp0_epc, regs->regs[31]); + die("Unrecoverable bus error", regs); +} + + +void __init dec_kn02xa_be_init(void) +{ + volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); + + /* For KN04 we need to make sure EE (?) is enabled in the MB. */ + if (current_cpu_data.cputype == CPU_R4000SC) + *mbcs |= KN4K_MB_CSR_EE; + fast_iob(); + + /* Clear any leftover errors from the firmware. */ + dec_kn02xa_be_ack(); +} diff -Naur linux-2.6.12.6.orig/arch/mips/dec/prom/identify.c linux-2.6.12.6/arch/mips/dec/prom/identify.c --- linux-2.6.12.6.orig/arch/mips/dec/prom/identify.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/dec/prom/identify.c 2005-10-02 23:47:36.000000000 +0000 @@ -2,7 +2,7 @@ * identify.c: machine identification code. * * Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine - * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki */ #include #include @@ -12,6 +12,7 @@ #include #include + #include #include #include @@ -21,6 +22,7 @@ #include #include #include +#include #include "dectypes.h" @@ -68,34 +70,44 @@ static inline void prom_init_kn01(void) { - dec_rtc_base = (void *)KN01_RTC_BASE; + dec_kn_slot_base = KN01_SLOT_BASE; dec_kn_slot_size = KN01_SLOT_SIZE; + + dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); } static inline void prom_init_kn230(void) { - dec_rtc_base = (void *)KN01_RTC_BASE; + dec_kn_slot_base = KN01_SLOT_BASE; dec_kn_slot_size = KN01_SLOT_SIZE; + + dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); } static inline void prom_init_kn02(void) { - dec_rtc_base = (void *)KN02_RTC_BASE; + dec_kn_slot_base = KN02_SLOT_BASE; dec_kn_slot_size = KN02_SLOT_SIZE; + + dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC); } static inline void prom_init_kn02xa(void) { - ioasic_base = (void *)KN02XA_IOASIC_BASE; - dec_rtc_base = (void *)KN02XA_RTC_BASE; + dec_kn_slot_base = KN02XA_SLOT_BASE; dec_kn_slot_size = IOASIC_SLOT_SIZE; + + ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); + dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); } static inline void prom_init_kn03(void) { - ioasic_base = (void *)KN03_IOASIC_BASE; - dec_rtc_base = (void *)KN03_RTC_BASE; + dec_kn_slot_base = KN03_SLOT_BASE; dec_kn_slot_size = IOASIC_SLOT_SIZE; + + ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); + dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); } diff -Naur linux-2.6.12.6.orig/arch/mips/dec/prom/init.c linux-2.6.12.6/arch/mips/dec/prom/init.c --- linux-2.6.12.6.orig/arch/mips/dec/prom/init.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/dec/prom/init.c 2005-10-02 23:47:36.000000000 +0000 @@ -6,6 +6,8 @@ */ #include #include +#include +#include #include #include #include @@ -85,17 +87,13 @@ void __init prom_init(void) { - extern void dec_machine_halt(void); + extern void ATTRIB_NORET dec_machine_halt(void); static char cpu_msg[] __initdata = "Sorry, this kernel is compiled for a wrong CPU type!\n"; - static char r3k_msg[] __initdata = - "Please recompile with \"CONFIG_CPU_R3000 = y\".\n"; - static char r4k_msg[] __initdata = - "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n"; s32 argc = fw_arg0; - s32 argv = fw_arg1; + s32 *argv = (void *)fw_arg1; u32 magic = fw_arg2; - s32 prom_vec = fw_arg3; + s32 *prom_vec = (void *)fw_arg3; /* * Determine which PROM we have @@ -113,6 +111,8 @@ #if defined(CONFIG_CPU_R3000) if ((current_cpu_data.cputype == CPU_R4000SC) || (current_cpu_data.cputype == CPU_R4400SC)) { + static char r4k_msg[] __initdata = + "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n"; printk(cpu_msg); printk(r4k_msg); dec_machine_halt(); @@ -122,6 +122,8 @@ #if defined(CONFIG_CPU_R4X00) if ((current_cpu_data.cputype == CPU_R3000) || (current_cpu_data.cputype == CPU_R3000A)) { + static char r3k_msg[] __initdata = + "Please recompile with \"CONFIG_CPU_R3000 = y\".\n"; printk(cpu_msg); printk(r3k_msg); dec_machine_halt(); diff -Naur linux-2.6.12.6.orig/arch/mips/dec/prom/memory.c linux-2.6.12.6/arch/mips/dec/prom/memory.c --- linux-2.6.12.6.orig/arch/mips/dec/prom/memory.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/dec/prom/memory.c 2005-10-02 23:47:36.000000000 +0000 @@ -35,22 +35,22 @@ extern char genexcept_early; /* Install exception handler */ - memcpy(&old_handler, (void *)(KSEG0 + 0x80), 0x80); - memcpy((void *)(KSEG0 + 0x80), &genexcept_early, 0x80); + memcpy(&old_handler, (void *)(CKSEG0 + 0x80), 0x80); + memcpy((void *)(CKSEG0 + 0x80), &genexcept_early, 0x80); /* read unmapped and uncached (KSEG1) * DECstations have at least 4MB RAM * Assume less than 480MB of RAM, as this is max for 5000/2xx * FIXME this should be replaced by the first free page! */ - for (memory_page = (unsigned char *) KSEG1 + CHUNK_SIZE; - (mem_err== 0) && (memory_page < ((unsigned char *) KSEG1+0x1E000000)); + for (memory_page = (unsigned char *)CKSEG1 + CHUNK_SIZE; + mem_err == 0 && memory_page < (unsigned char *)CKSEG1 + 0x1e00000; memory_page += CHUNK_SIZE) { dummy = *memory_page; } - memcpy((void *)(KSEG0 + 0x80), &old_handler, 0x80); + memcpy((void *)(CKSEG0 + 0x80), &old_handler, 0x80); - add_memory_region(0, (unsigned long)memory_page - KSEG1 - CHUNK_SIZE, + add_memory_region(0, (unsigned long)memory_page - CKSEG1 - CHUNK_SIZE, BOOT_MEM_RAM); } @@ -65,7 +65,7 @@ memmap *bm; /* some free 64k */ - bm = (memmap *)KSEG0ADDR(0x28000); + bm = (memmap *)CKSEG0ADDR(0x28000); bitmap_size = rex_getbitmap(bm); diff -Naur linux-2.6.12.6.orig/arch/mips/dec/reset.c linux-2.6.12.6/arch/mips/dec/reset.c --- linux-2.6.12.6.orig/arch/mips/dec/reset.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/dec/reset.c 2005-10-02 23:47:36.000000000 +0000 @@ -14,7 +14,7 @@ static inline void ATTRIB_NORET back_to_prom(void) { - noret_func_t func = (void *) KSEG1ADDR(0x1fc00000); + noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000); func(); } diff -Naur linux-2.6.12.6.orig/arch/mips/dec/setup.c linux-2.6.12.6/arch/mips/dec/setup.c --- linux-2.6.12.6.orig/arch/mips/dec/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/dec/setup.c 2005-10-02 23:47:36.000000000 +0000 @@ -1,19 +1,20 @@ /* - * Setup the interrupt stuff. + * System-specific setup, especially interrupts. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1998 Harald Koerfgen - * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki */ -#include -#include -#include #include #include +#include +#include #include +#include +#include #include #include @@ -38,6 +39,7 @@ #include #include #include +#include extern void dec_machine_restart(char *command); @@ -47,10 +49,16 @@ extern asmlinkage void decstation_handle_int(void); +unsigned long dec_kn_slot_base, dec_kn_slot_size; + +EXPORT_SYMBOL(dec_kn_slot_base); +EXPORT_SYMBOL(dec_kn_slot_size); + spinlock_t ioasic_ssr_lock; volatile u32 *ioasic_base; -unsigned long dec_kn_slot_size; + +EXPORT_SYMBOL(ioasic_base); /* * IRQ routing and priority tables. Priorites are set as follows: @@ -77,6 +85,9 @@ int dec_interrupt[DEC_NR_INTS] = { [0 ... DEC_NR_INTS - 1] = -1 }; + +EXPORT_SYMBOL(dec_interrupt); + int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = { { { .i = ~0 }, { .p = dec_intr_unimplemented } }, }; @@ -112,7 +123,16 @@ { switch (mips_machtype) { case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ + board_be_handler = dec_kn01_be_handler; + busirq.handler = dec_kn01_be_interrupt; busirq.flags |= SA_SHIRQ; + dec_kn01_be_init(); + break; + case MACH_DS5000_1XX: /* DS5000/1xx 3min */ + case MACH_DS5000_XX: /* DS5000/xx Maxine */ + board_be_handler = dec_kn02xa_be_handler; + busirq.handler = dec_kn02xa_be_interrupt; + dec_kn02xa_be_init(); break; case MACH_DS5000_200: /* DS5000/200 3max */ case MACH_DS5000_2X0: /* DS5000/240 3max+ */ @@ -128,7 +148,7 @@ extern void dec_time_init(void); extern void dec_timer_setup(struct irqaction *); -static void __init decstation_setup(void) +void __init decstation_setup(void) { board_be_init = dec_be_init; board_time_init = dec_time_init; @@ -139,9 +159,10 @@ _machine_restart = dec_machine_restart; _machine_halt = dec_machine_halt; _machine_power_off = dec_machine_power_off; -} -early_initcall(decstation_setup); + ioport_resource.start = ~0UL; + ioport_resource.end = 0UL; +} /* * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin) @@ -744,7 +765,3 @@ if (dec_interrupt[DEC_IRQ_HALT] >= 0) setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); } - -EXPORT_SYMBOL(ioasic_base); -EXPORT_SYMBOL(dec_kn_slot_size); -EXPORT_SYMBOL(dec_interrupt); diff -Naur linux-2.6.12.6.orig/arch/mips/defconfig linux-2.6.12.6/arch/mips/defconfig --- linux-2.6.12.6.orig/arch/mips/defconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/defconfig 2005-10-02 23:47:36.000000000 +0000 @@ -1,12 +1,9 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:48:59 2005 +# Linux kernel version: 2.6.12 +# Sat Jun 18 14:53:00 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options @@ -14,6 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -25,7 +23,6 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y CONFIG_IKCONFIG=y @@ -33,6 +30,9 @@ CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -42,6 +42,7 @@ CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -57,40 +58,63 @@ # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set CONFIG_SGI_IP22=y -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y CONFIG_DMA_NONCOHERENT=y +CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y CONFIG_ARC32=y @@ -119,6 +143,17 @@ # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set @@ -135,6 +170,7 @@ # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # +CONFIG_HW_HAS_EISA=y # CONFIG_EISA is not set CONFIG_MMU=y @@ -144,10 +180,6 @@ # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -276,7 +308,6 @@ # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y CONFIG_UNIX=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -409,7 +440,7 @@ CONFIG_IP_NF_ARP_MANGLE=m # -# IPv6: Netfilter Configuration +# IPv6: Netfilter Configuration (EXPERIMENTAL) # CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m @@ -478,6 +509,7 @@ CONFIG_NET_QOS=y CONFIG_NET_ESTIMATOR=y CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_ROUTE=y @@ -488,6 +520,7 @@ # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_CLS_POLICE=y @@ -505,7 +538,6 @@ CONFIG_BONDING=m CONFIG_EQUALIZER=m CONFIG_TUN=m -CONFIG_ETHERTAP=m # # Ethernet (10 or 100Mbit) @@ -568,18 +600,6 @@ # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y @@ -597,6 +617,16 @@ # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -648,6 +678,10 @@ CONFIG_MAX_RAW_DEVS=256 # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set @@ -692,7 +726,6 @@ # CONFIG_LOGO_LINUX_VGA16 is not set # CONFIG_LOGO_LINUX_CLUT224 is not set CONFIG_LOGO_SGI_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -706,10 +739,6 @@ # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -739,7 +768,12 @@ # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y + +# +# XFS support +# CONFIG_XFS_FS=m +CONFIG_XFS_EXPORT=y # CONFIG_XFS_RT is not set CONFIG_XFS_QUOTA=y CONFIG_XFS_SECURITY=y @@ -907,7 +941,9 @@ # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" @@ -930,6 +966,7 @@ CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_TWOFISH=m diff -Naur linux-2.6.12.6.orig/arch/mips/galileo-boards/ev96100/setup.c linux-2.6.12.6/arch/mips/galileo-boards/ev96100/setup.c --- linux-2.6.12.6.orig/arch/mips/galileo-boards/ev96100/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/galileo-boards/ev96100/setup.c 2005-10-02 23:47:36.000000000 +0000 @@ -55,7 +55,7 @@ unsigned char mac_0_1[12]; -static void __init ev96100_setup(void) +void __init plat_setup(void) { unsigned int config = read_c0_config(); unsigned int status = read_c0_status(); @@ -142,8 +142,6 @@ tmp = GT_READ(GT_PCI0_CFGDATA_OFS); } -early_initcall(ev96100_setup); - unsigned short get_gt_devid(void) { u32 gt_devid; diff -Naur linux-2.6.12.6.orig/arch/mips/gt64120/ev64120/Kconfig linux-2.6.12.6/arch/mips/gt64120/ev64120/Kconfig --- linux-2.6.12.6.orig/arch/mips/gt64120/ev64120/Kconfig 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/gt64120/ev64120/Kconfig 2005-10-02 23:47:36.000000000 +0000 @@ -0,0 +1,3 @@ +config EVB_PCI1 + bool "Enable Second PCI (PCI1)" + depends on MIPS_EV64120 diff -Naur linux-2.6.12.6.orig/arch/mips/gt64120/ev64120/setup.c linux-2.6.12.6/arch/mips/gt64120/ev64120/setup.c --- linux-2.6.12.6.orig/arch/mips/gt64120/ev64120/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/gt64120/ev64120/setup.c 2005-10-02 23:47:36.000000000 +0000 @@ -69,7 +69,7 @@ */ extern void gt64120_time_init(void); -static void __init ev64120_setup(void) +void __init plat_setup(void) { _machine_restart = galileo_machine_restart; _machine_halt = galileo_machine_halt; @@ -79,8 +79,6 @@ set_io_port_base(KSEG1); } -early_initcall(ev64120_setup); - const char *get_system_type(void) { return "Galileo EV64120A"; diff -Naur linux-2.6.12.6.orig/arch/mips/gt64120/momenco_ocelot/setup.c linux-2.6.12.6/arch/mips/gt64120/momenco_ocelot/setup.c --- linux-2.6.12.6.orig/arch/mips/gt64120/momenco_ocelot/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/gt64120/momenco_ocelot/setup.c 2005-10-02 23:47:36.000000000 +0000 @@ -150,7 +150,7 @@ gt64120_base = 0xe0000000; } -static void __init momenco_ocelot_setup(void) +void __init plat_setup(void) { void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache); unsigned int tmpword; @@ -307,8 +307,6 @@ GT_WRITE(GT_DEV_B3_OFS, 0xfef73); } -early_initcall(momenco_ocelot_setup); - extern int rm7k_tcache_enabled; /* * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache() diff -Naur linux-2.6.12.6.orig/arch/mips/ite-boards/Kconfig linux-2.6.12.6/arch/mips/ite-boards/Kconfig --- linux-2.6.12.6.orig/arch/mips/ite-boards/Kconfig 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/ite-boards/Kconfig 2005-10-02 23:47:36.000000000 +0000 @@ -0,0 +1,8 @@ +config IT8172_REVC + bool "Support for older IT8172 (Rev C)" + depends on MIPS_ITE8172 + help + Say Y here to support the older, Revision C version of the Integrated + Technology Express, Inc. ITE8172 SBC. Vendor page at + ; picture of the + board at . diff -Naur linux-2.6.12.6.orig/arch/mips/ite-boards/generic/irq.c linux-2.6.12.6/arch/mips/ite-boards/generic/irq.c --- linux-2.6.12.6.orig/arch/mips/ite-boards/generic/irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/ite-boards/generic/irq.c 2005-10-02 23:47:36.000000000 +0000 @@ -138,14 +138,13 @@ } static struct hw_interrupt_type it8172_irq_type = { - "ITE8172", - startup_ite_irq, - shutdown_ite_irq, - enable_it8172_irq, - disable_it8172_irq, - mask_and_ack_ite_irq, - end_ite_irq, - NULL + .typename = "ITE8172", + .startup = startup_ite_irq, + .shutdown = shutdown_ite_irq, + .enable = enable_it8172_irq, + .disable = disable_it8172_irq, + .ack = mask_and_ack_ite_irq, + .end = end_ite_irq, }; @@ -159,13 +158,13 @@ #define end_none enable_none static struct hw_interrupt_type cp0_irq_type = { - "CP0 Count", - startup_none, - shutdown_none, - enable_none, - disable_none, - ack_none, - end_none + .typename = "CP0 Count", + .startup = startup_none, + .shutdown = shutdown_none, + .enable = enable_none, + .disable = disable_none, + .ack = ack_none, + .end = end_none }; void enable_cpu_timer(void) diff -Naur linux-2.6.12.6.orig/arch/mips/ite-boards/generic/it8172_setup.c linux-2.6.12.6/arch/mips/ite-boards/generic/it8172_setup.c --- linux-2.6.12.6.orig/arch/mips/ite-boards/generic/it8172_setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/ite-boards/generic/it8172_setup.c 2005-10-02 23:47:36.000000000 +0000 @@ -105,7 +105,7 @@ it8172_resources.ram.end = memsize; } -static void __init it8172_setup(void) +void __init plat_setup(void) { unsigned short dsr; char *argptr; @@ -251,8 +251,6 @@ #endif /* CONFIG_IT8172_SCR1 */ } -early_initcall(it8172_setup); - #ifdef CONFIG_SERIO_I8042 /* * According to the ITE Special BIOS Note for waking up the diff -Naur linux-2.6.12.6.orig/arch/mips/jazz/Kconfig linux-2.6.12.6/arch/mips/jazz/Kconfig --- linux-2.6.12.6.orig/arch/mips/jazz/Kconfig 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/jazz/Kconfig 2005-10-02 23:47:36.000000000 +0000 @@ -0,0 +1,33 @@ +config ACER_PICA_61 + bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)" + depends on MACH_JAZZ && EXPERIMENTAL + select DMA_NONCOHERENT + select SYS_SUPPORTS_LITTLE_ENDIAN + help + This is a machine with a R4400 133/150 MHz CPU. To compile a Linux + kernel that runs on these, say Y here. For details about Linux on + the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at + . + +config MIPS_MAGNUM_4000 + bool "Support for MIPS Magnum 4000" + depends on MACH_JAZZ + select DMA_NONCOHERENT + select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN + help + This is a machine with a R4000 100 MHz CPU. To compile a Linux + kernel that runs on these, say Y here. For details about Linux on + the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at + . + +config OLIVETTI_M700 + bool "Support for Olivetti M700-10" + depends on MACH_JAZZ + select DMA_NONCOHERENT + select SYS_SUPPORTS_LITTLE_ENDIAN + help + This is a machine with a R4000 100 MHz CPU. To compile a Linux + kernel that runs on these, say Y here. For details about Linux on + the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at + . diff -Naur linux-2.6.12.6.orig/arch/mips/jazz/irq.c linux-2.6.12.6/arch/mips/jazz/irq.c --- linux-2.6.12.6.orig/arch/mips/jazz/irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/jazz/irq.c 2005-10-02 23:47:36.000000000 +0000 @@ -58,14 +58,13 @@ } static struct hw_interrupt_type r4030_irq_type = { - "R4030", - startup_r4030_irq, - shutdown_r4030_irq, - enable_r4030_irq, - disable_r4030_irq, - mask_and_ack_r4030_irq, - end_r4030_irq, - NULL + .typename = "R4030", + .startup = startup_r4030_irq, + .shutdown = shutdown_r4030_irq, + .enable = enable_r4030_irq, + .disable = disable_r4030_irq, + .ack = mask_and_ack_r4030_irq, + .end = end_r4030_irq, }; void __init init_r4030_ints(void) diff -Naur linux-2.6.12.6.orig/arch/mips/jazz/setup.c linux-2.6.12.6/arch/mips/jazz/setup.c --- linux-2.6.12.6.orig/arch/mips/jazz/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/jazz/setup.c 2005-10-02 23:47:36.000000000 +0000 @@ -50,7 +50,7 @@ { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, }; -static void __init jazz_setup(void) +void __init plat_setup(void) { int i; @@ -97,5 +97,3 @@ vdma_init(); } - -early_initcall(jazz_setup); diff -Naur linux-2.6.12.6.orig/arch/mips/jmr3927/rbhma3100/irq.c linux-2.6.12.6/arch/mips/jmr3927/rbhma3100/irq.c --- linux-2.6.12.6.orig/arch/mips/jmr3927/rbhma3100/irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/jmr3927/rbhma3100/irq.c 2005-10-02 23:47:36.000000000 +0000 @@ -412,13 +412,13 @@ } static hw_irq_controller jmr3927_irq_controller = { - "jmr3927_irq", - jmr3927_irq_startup, - jmr3927_irq_shutdown, - jmr3927_irq_enable, - jmr3927_irq_disable, - jmr3927_irq_ack, - jmr3927_irq_end, + .typename = "jmr3927_irq", + .startup = jmr3927_irq_startup, + .shutdown = jmr3927_irq_shutdown, + .enable = jmr3927_irq_enable, + .disable = jmr3927_irq_disable, + .ack = jmr3927_irq_ack, + .end = jmr3927_irq_end, }; void jmr3927_irq_init(u32 irq_base) diff -Naur linux-2.6.12.6.orig/arch/mips/jmr3927/rbhma3100/setup.c linux-2.6.12.6/arch/mips/jmr3927/rbhma3100/setup.c --- linux-2.6.12.6.orig/arch/mips/jmr3927/rbhma3100/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/jmr3927/rbhma3100/setup.c 2005-10-02 23:47:36.000000000 +0000 @@ -44,6 +44,11 @@ #include #include /* for HZ */ #include +#ifdef CONFIG_SERIAL_TXX9 +#include +#include +#include +#endif #include #include @@ -193,7 +198,7 @@ extern struct resource pci_io_resource; extern struct resource pci_mem_resource; -static void __init jmr3927_setup(void) +void __init plat_setup(void) { char *argptr; @@ -211,8 +216,8 @@ */ ioport_resource.start = pci_io_resource.start; ioport_resource.end = pci_io_resource.end; - iomem_resource.start = pci_mem_resource.start; - iomem_resource.end = pci_mem_resource.end; + iomem_resource.start = 0; + iomem_resource.end = 0xffffffff; /* Reboot on panic */ panic_timeout = 180; @@ -265,18 +270,35 @@ strcat(argptr, " ip=bootp"); } -#ifdef CONFIG_TXX927_SERIAL_CONSOLE +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + int i; + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (char *)TX3927_SIO_REG(i); + req.mapbase = TX3927_SIO_REG(i); + req.irq = i == 0 ? + JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; + if (i == 0) + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = JMR3927_IMCLK; + early_serial_txx9_setup(&req); + } + } +#ifdef CONFIG_SERIAL_TXX9_CONSOLE argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "console=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " console=ttyS1,115200"); } #endif +#endif } -early_initcall(jmr3927_setup); - - static void tx3927_setup(void); #ifdef CONFIG_PCI @@ -335,7 +357,7 @@ jmr3927_io_dipsw()); } -static void __init tx3927_setup(void) +void __init plat_setup(void) { int i; diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/Makefile linux-2.6.12.6/arch/mips/kernel/Makefile --- linux-2.6.12.6.orig/arch/mips/kernel/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/Makefile 2005-10-02 23:47:36.000000000 +0000 @@ -11,11 +11,7 @@ binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ irix5sys.o sysirix.o -ifdef CONFIG_MODULES -obj-y += mips_ksyms.o module.o -obj-$(CONFIG_MIPS32) += module-elf32.o -obj-$(CONFIG_MIPS64) += module-elf64.o -endif +obj-$(CONFIG_MODULES) += mips_ksyms.o module.o obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/binfmt_elfn32.c linux-2.6.12.6/arch/mips/kernel/binfmt_elfn32.c --- linux-2.6.12.6.orig/arch/mips/kernel/binfmt_elfn32.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/binfmt_elfn32.c 2005-10-02 23:47:36.000000000 +0000 @@ -52,7 +52,6 @@ #include #include -#include #include #include @@ -116,4 +115,7 @@ #undef MODULE_DESCRIPTION #undef MODULE_AUTHOR +#undef TASK_SIZE +#define TASK_SIZE TASK_SIZE32 + #include "../../../fs/binfmt_elf.c" diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/binfmt_elfo32.c linux-2.6.12.6/arch/mips/kernel/binfmt_elfo32.c --- linux-2.6.12.6.orig/arch/mips/kernel/binfmt_elfo32.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/binfmt_elfo32.c 2005-10-02 23:47:36.000000000 +0000 @@ -54,7 +54,6 @@ #include #include -#include #include #include @@ -98,7 +97,7 @@ #define init_elf_binfmt init_elf32_binfmt #define jiffies_to_timeval jiffies_to_compat_timeval -static __inline__ void +static inline void jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) { /* @@ -113,21 +112,26 @@ #undef ELF_CORE_COPY_REGS #define ELF_CORE_COPY_REGS(_dest,_regs) elf32_core_copy_regs(_dest,_regs); -void elf32_core_copy_regs(elf_gregset_t _dest, struct pt_regs *_regs) +void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs) { int i; - memset(_dest, 0, sizeof(elf_gregset_t)); - - /* XXXKW the 6 is from EF_REG0 in gdb/gdb/mips-linux-tdep.c, include/asm-mips/reg.h */ - for (i=6; i<38; i++) - _dest[i] = (elf_greg_t) _regs->regs[i-6]; - _dest[i++] = (elf_greg_t) _regs->lo; - _dest[i++] = (elf_greg_t) _regs->hi; - _dest[i++] = (elf_greg_t) _regs->cp0_epc; - _dest[i++] = (elf_greg_t) _regs->cp0_badvaddr; - _dest[i++] = (elf_greg_t) _regs->cp0_status; - _dest[i++] = (elf_greg_t) _regs->cp0_cause; + for (i = 0; i < EF_R0; i++) + grp[i] = 0; + grp[EF_R0] = 0; + for (i = 1; i <= 31; i++) + grp[EF_R0 + i] = (elf_greg_t) regs->regs[i]; + grp[EF_R26] = 0; + grp[EF_R27] = 0; + grp[EF_LO] = (elf_greg_t) regs->lo; + grp[EF_HI] = (elf_greg_t) regs->hi; + grp[EF_CP0_EPC] = (elf_greg_t) regs->cp0_epc; + grp[EF_CP0_BADVADDR] = (elf_greg_t) regs->cp0_badvaddr; + grp[EF_CP0_STATUS] = (elf_greg_t) regs->cp0_status; + grp[EF_CP0_CAUSE] = (elf_greg_t) regs->cp0_cause; +#ifdef EF_UNUSED0 + grp[EF_UNUSED0] = 0; +#endif } MODULE_DESCRIPTION("Binary format loader for compatibility with o32 Linux/MIPS binaries"); @@ -136,4 +140,7 @@ #undef MODULE_DESCRIPTION #undef MODULE_AUTHOR +#undef TASK_SIZE +#define TASK_SIZE TASK_SIZE32 + #include "../../../fs/binfmt_elf.c" diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/branch.c linux-2.6.12.6/arch/mips/kernel/branch.c --- linux-2.6.12.6.orig/arch/mips/kernel/branch.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/branch.c 2005-10-02 23:47:36.000000000 +0000 @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -21,7 +22,7 @@ */ int __compute_return_epc(struct pt_regs *regs) { - unsigned int *addr, bit, fcr31; + unsigned int *addr, bit, fcr31, dspcontrol; long epc; union mips_instruction insn; @@ -98,6 +99,18 @@ epc += 8; regs->cp0_epc = epc; break; + case bposge32_op: + if (!cpu_has_dsp) + goto sigill; + + dspcontrol = rddsp(0x01); + + if (dspcontrol >= 32) { + epc = epc + 4 + (insn.i_format.simmediate << 2); + } else + epc += 8; + regs->cp0_epc = epc; + break; } break; @@ -161,10 +174,13 @@ * And now the FPA/cp1 branch instructions. */ case cop1_op: - if (!cpu_has_fpu) - fcr31 = current->thread.fpu.soft.fcr31; - else + preempt_disable(); + if (is_fpu_owner()) asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); + else + fcr31 = current->thread.fpu.hard.fcr31; + preempt_enable(); + bit = (insn.i_format.rt >> 2); bit += (bit != 0); bit += 23; @@ -196,4 +212,9 @@ printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); force_sig(SIGBUS, current); return -EFAULT; + +sigill: + printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm); + force_sig(SIGBUS, current); + return -EFAULT; } diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/cpu-probe.c linux-2.6.12.6/arch/mips/kernel/cpu-probe.c --- linux-2.6.12.6.orig/arch/mips/kernel/cpu-probe.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/cpu-probe.c 2005-10-02 23:47:36.000000000 +0000 @@ -2,9 +2,9 @@ * Processor capabilities determination functions. * * Copyright (C) xxxx the Anonymous - * Copyright (C) 2003 Maciej W. Rozycki + * Copyright (C) 2003, 2004 Maciej W. Rozycki * Copyright (C) 1994 - 2003 Ralf Baechle - * Copyright (C) 2001 MIPS Inc. + * Copyright (C) 2001, 2004 MIPS Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -17,7 +17,6 @@ #include #include -#include #include #include #include @@ -51,29 +50,25 @@ ".set\tmips0"); } -/* - * The Au1xxx wait is available only if we run CONFIG_PM and - * the timer setup found we had a 32KHz counter available. - * There are still problems with functions that may call au1k_wait - * directly, but that will be discovered pretty quickly. - */ -extern void (*au1k_wait_ptr)(void); +/* The Au1xxx wait is available only if using 32khz counter or + * external timer source, but specifically not CP0 Counter. */ +int allow_au1k_wait; -void au1k_wait(void) +static void au1k_wait(void) { -#ifdef CONFIG_PM /* using the wait instruction makes CP0 counter unusable */ - __asm__(".set\tmips3\n\t" + __asm__(".set mips3\n\t" + "cache 0x14, 0(%0)\n\t" + "cache 0x14, 32(%0)\n\t" + "sync\n\t" + "nop\n\t" "wait\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" - ".set\tmips0"); -#else - __asm__("nop\n\t" - "nop"); -#endif + ".set mips0\n\t" + : : "r" (au1k_wait)); } static inline void check_wait(void) @@ -112,19 +107,17 @@ cpu_wait = r4k_wait; printk(" available.\n"); break; -#ifdef CONFIG_PM case CPU_AU1000: case CPU_AU1100: case CPU_AU1500: - if (au1k_wait_ptr != NULL) { - cpu_wait = au1k_wait_ptr; + case CPU_AU1550: + case CPU_AU1200: + if (allow_au1k_wait) { + cpu_wait = au1k_wait; printk(" available.\n"); - } - else { + } else printk(" unavailable.\n"); - } break; -#endif default: printk(" unavailable.\n"); break; @@ -136,6 +129,58 @@ check_wait(); } +#ifdef CONFIG_MIPS64 + +/* + * On RM5230/5231 all accesses to XKPHYS by LL(D) are forced + * to be uncached, bits 61-59 of the address are ignored. + * + * Apparently fixed on RM5230A/5231A. + */ +static inline int check_lld(void) +{ + unsigned long flags, value, match, phys, *addr; + + printk("Checking for lld bug... "); + + /* hope the stack is in the low 512MB */ + phys = CPHYSADDR((unsigned long) &value); + + /* write value to memory */ + value = 0xfedcba9876543210; + addr = (unsigned long *) PHYS_TO_XKPHYS(K_CALG_UNCACHED, phys); + *addr = value; + + /* stop spurious flushes */ + local_irq_save(flags); + + /* flip cached value */ + value = ~value; + + /* read value, supposedly from cache */ + addr = (unsigned long *) PHYS_TO_XKPHYS(K_CALG_NONCOHERENT, phys); + asm volatile("lld %0, %1" : "=r" (match) : "m" (*addr)); + + local_irq_restore(flags); + + match ^= value; + + switch ((long) match) { + case 0: + printk("no.\n"); + break; + case -1: + printk("yes.\n"); + break; + default: + printk("yikes yes! (%lx/%lx@%p)\nPlease report to .", value, match, &value); + } + + return !match; +} + +#endif + /* * Probe whether cpu has config register by trying to play with * alternate cache bit and see whether it matters. @@ -352,7 +397,11 @@ c->cputype = CPU_NEVADA; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_DIVEC | MIPS_CPU_LLSC; + MIPS_CPU_DIVEC; +#ifdef CONFIG_MIPS64 + if (check_lld()) +#endif + c->options |= MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_R6000: @@ -427,65 +476,127 @@ } } -static inline void decode_config1(struct cpuinfo_mips *c) +static inline unsigned int decode_config0(struct cpuinfo_mips *c) { - unsigned long config0 = read_c0_config(); - unsigned long config1; + unsigned int config0; + int isa; + + config0 = read_c0_config(); - if ((config0 & (1 << 31)) == 0) - return; /* actually wort a panic() */ + if (((config0 & MIPS_CONF_MT) >> 7) == 1) + c->options |= MIPS_CPU_TLB | MIPS_CPU_4KTLB; + isa = (config0 & MIPS_CONF_AT) >> 13; + switch (isa) { + case 0: + c->isa_level = MIPS_CPU_ISA_M32; + break; + case 2: + c->isa_level = MIPS_CPU_ISA_M64; + break; + default: + panic("Unsupported ISA type, cp0.config0.at: %d.", isa); + } + + return config0 & MIPS_CONF_M; +} + +static inline unsigned int decode_config1(struct cpuinfo_mips *c) +{ + unsigned int config1; - /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */ - c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | - MIPS_CPU_LLSC | MIPS_CPU_MCHECK; config1 = read_c0_config1(); - if (config1 & (1 << 3)) + + if (config1 & MIPS_CONF1_MD) + c->ases |= MIPS_ASE_MDMX; + if (config1 & MIPS_CONF1_WR) c->options |= MIPS_CPU_WATCH; - if (config1 & (1 << 2)) - c->options |= MIPS_CPU_MIPS16; - if (config1 & (1 << 1)) + if (config1 & MIPS_CONF1_CA) + c->ases |= MIPS_ASE_MIPS16; + if (config1 & MIPS_CONF1_EP) c->options |= MIPS_CPU_EJTAG; - if (config1 & 1) { + if (config1 & MIPS_CONF1_FP) { c->options |= MIPS_CPU_FPU; c->options |= MIPS_CPU_32FPR; } + if (cpu_has_tlb) + c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; + + return config1 & MIPS_CONF_M; +} + +static inline unsigned int decode_config2(struct cpuinfo_mips *c) +{ + unsigned int config2; + + config2 = read_c0_config2(); + + if (config2 & MIPS_CONF2_SL) + c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; + + return config2 & MIPS_CONF_M; +} + +static inline unsigned int decode_config3(struct cpuinfo_mips *c) +{ + unsigned int config3; + + config3 = read_c0_config3(); + + if (config3 & MIPS_CONF3_SM) + c->ases |= MIPS_ASE_SMARTMIPS; + if (config3 & MIPS_CONF3_DSP) + c->ases |= MIPS_ASE_DSP; + + return config3 & MIPS_CONF_M; +} + +static inline void decode_configs(struct cpuinfo_mips *c) +{ + /* MIPS32 or MIPS64 compliant CPU. */ + c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | + MIPS_CPU_LLSC | MIPS_CPU_MCHECK; + c->scache.flags = MIPS_CACHE_NOT_PRESENT; - c->tlbsize = ((config1 >> 25) & 0x3f) + 1; + /* Read Config registers. */ + if (!decode_config0(c)) + return; /* actually worth a panic() */ + if (!decode_config1(c)) + return; + if (!decode_config2(c)) + return; + if (!decode_config3(c)) + return; } static inline void cpu_probe_mips(struct cpuinfo_mips *c) { - decode_config1(c); + decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_4KC: c->cputype = CPU_4KC; - c->isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_4KEC: c->cputype = CPU_4KEC; - c->isa_level = MIPS_CPU_ISA_M32; + break; + case PRID_IMP_4KECR2: + c->cputype = CPU_4KEC; break; case PRID_IMP_4KSC: c->cputype = CPU_4KSC; - c->isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_5KC: c->cputype = CPU_5KC; - c->isa_level = MIPS_CPU_ISA_M64; break; case PRID_IMP_20KC: c->cputype = CPU_20KC; - c->isa_level = MIPS_CPU_ISA_M64; break; case PRID_IMP_24K: + case PRID_IMP_24KE: c->cputype = CPU_24K; - c->isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_25KF: c->cputype = CPU_25KF; - c->isa_level = MIPS_CPU_ISA_M64; /* Probe for L2 cache */ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; break; @@ -494,7 +605,7 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) { - decode_config1(c); + decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_AU1_REV1: case PRID_IMP_AU1_REV2: @@ -511,29 +622,26 @@ case 3: c->cputype = CPU_AU1550; break; + case 4: + c->cputype = CPU_AU1200; + break; default: panic("Unknown Au Core!"); break; } - c->isa_level = MIPS_CPU_ISA_M32; break; } } static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) { - decode_config1(c); + decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_SB1: c->cputype = CPU_SB1; - c->isa_level = MIPS_CPU_ISA_M64; - c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | - MIPS_CPU_MCHECK | MIPS_CPU_EJTAG | - MIPS_CPU_WATCH | MIPS_CPU_LLSC; -#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS +#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS /* FPU in pass1 is known to have issues. */ - c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; + c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); #endif break; } @@ -541,14 +649,10 @@ static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) { - decode_config1(c); + decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_SR71000: c->cputype = CPU_SR71000; - c->isa_level = MIPS_CPU_ISA_M64; - c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_4KTLB | MIPS_CPU_FPU | - MIPS_CPU_COUNTER | MIPS_CPU_MCHECK; c->scache.ways = 8; c->tlbsize = 64; break; @@ -577,15 +681,21 @@ case PRID_COMP_SIBYTE: cpu_probe_sibyte(c); break; - case PRID_COMP_SANDCRAFT: cpu_probe_sandcraft(c); break; default: c->cputype = CPU_UNKNOWN; } - if (c->options & MIPS_CPU_FPU) + if (c->options & MIPS_CPU_FPU) { c->fpu_id = cpu_get_fpu_id(); + + if (c->isa_level == MIPS_CPU_ISA_M32 || + c->isa_level == MIPS_CPU_ISA_M64) { + if (c->fpu_id & MIPS_FPIR_3D) + c->ases |= MIPS_ASE_MIPS3D; + } + } } __init void cpu_report(void) diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/dma-no-isa.c linux-2.6.12.6/arch/mips/kernel/dma-no-isa.c --- linux-2.6.12.6.orig/arch/mips/kernel/dma-no-isa.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/dma-no-isa.c 2005-10-02 23:47:36.000000000 +0000 @@ -0,0 +1,28 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004 by Ralf Baechle + * + * Dummy ISA DMA functions for systems that don't have ISA but share drivers + * with ISA such as legacy free PCI. + */ +#include +#include +#include + +DEFINE_SPINLOCK(dma_spin_lock); + +int request_dma(unsigned int dmanr, const char * device_id) +{ + return -EINVAL; +} + +void free_dma(unsigned int dmanr) +{ +} + +EXPORT_SYMBOL(dma_spin_lock); +EXPORT_SYMBOL(request_dma); +EXPORT_SYMBOL(free_dma); diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/entry.S linux-2.6.12.6/arch/mips/kernel/entry.S --- linux-2.6.12.6.orig/arch/mips/kernel/entry.S 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/entry.S 2005-10-02 23:47:36.000000000 +0000 @@ -19,11 +19,11 @@ #include #ifdef CONFIG_PREEMPT - .macro preempt_stop reg=t0 + .macro preempt_stop .endm #else - .macro preempt_stop reg=t0 - local_irq_disable \reg + .macro preempt_stop + local_irq_disable .endm #define resume_kernel restore_all #endif @@ -37,17 +37,18 @@ andi t0, t0, KU_USER beqz t0, resume_kernel -FEXPORT(resume_userspace) - local_irq_disable t0 # make sure we dont miss an +resume_userspace: + local_irq_disable # make sure we dont miss an # interrupt setting need_resched # between sampling and return LONG_L a2, TI_FLAGS($28) # current->work - andi a2, _TIF_WORK_MASK # (ignoring syscall_trace) - bnez a2, work_pending + andi t0, a2, _TIF_WORK_MASK # (ignoring syscall_trace) + bnez t0, work_pending j restore_all #ifdef CONFIG_PREEMPT -ENTRY(resume_kernel) +resume_kernel: + local_irq_disable lw t0, TI_PRE_COUNT($28) bnez t0, restore_all need_resched: @@ -57,12 +58,7 @@ LONG_L t0, PT_STATUS(sp) # Interrupts off? andi t0, 1 beqz t0, restore_all - li t0, PREEMPT_ACTIVE - sw t0, TI_PRE_COUNT($28) - local_irq_enable t0 - jal schedule - sw zero, TI_PRE_COUNT($28) - local_irq_disable t0 + jal preempt_schedule_irq b need_resched #endif @@ -88,13 +84,13 @@ RESTORE_SP_AND_RET .set at -FEXPORT(work_pending) - andi t0, a2, _TIF_NEED_RESCHED +work_pending: + andi t0, a2, _TIF_NEED_RESCHED # a2 is preloaded with TI_FLAGS beqz t0, work_notifysig work_resched: jal schedule - local_irq_disable t0 # make sure need_resched and + local_irq_disable # make sure need_resched and # signals dont change between # sampling and return LONG_L a2, TI_FLAGS($28) @@ -113,11 +109,10 @@ FEXPORT(syscall_exit_work_partial) SAVE_STATIC -FEXPORT(syscall_exit_work) - LONG_L t0, TI_FLAGS($28) - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT - and t0, t1 - beqz t0, work_pending # trace bit is set +syscall_exit_work: + li t0, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT + and t0, a2 # a2 is preloaded with TI_FLAGS + beqz t0, work_pending # trace bit set? local_irq_enable # could let do_syscall_trace() # call schedule() instead move a0, sp @@ -128,28 +123,25 @@ /* * Common spurious interrupt handler. */ - .text - .align 5 LEAF(spurious_interrupt) /* * Someone tried to fool us by sending an interrupt but we * couldn't find a cause for it. */ + PTR_LA t1, irq_err_count #ifdef CONFIG_SMP - lui t1, %hi(irq_err_count) -1: ll t0, %lo(irq_err_count)(t1) +1: ll t0, (t1) addiu t0, 1 - sc t0, %lo(irq_err_count)(t1) + sc t0, (t1) #if R10000_LLSC_WAR beqzl t0, 1b #else beqz t0, 1b #endif #else - lui t1, %hi(irq_err_count) - lw t0, %lo(irq_err_count)(t1) + lw t0, (t1) addiu t0, 1 - sw t0, %lo(irq_err_count)(t1) + sw t0, (t1) #endif j ret_from_irq END(spurious_interrupt) diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/gdb-stub.c linux-2.6.12.6/arch/mips/kernel/gdb-stub.c --- linux-2.6.12.6.orig/arch/mips/kernel/gdb-stub.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/gdb-stub.c 2005-10-02 23:47:36.000000000 +0000 @@ -176,7 +176,7 @@ /* * spin locks for smp case */ -static spinlock_t kgdb_lock = SPIN_LOCK_UNLOCKED; +static DEFINE_SPINLOCK(kgdb_lock); static spinlock_t kgdb_cpulock[NR_CPUS] = { [0 ... NR_CPUS-1] = SPIN_LOCK_UNLOCKED}; /* @@ -637,15 +637,18 @@ * and only one can be active at a time. */ extern spinlock_t smp_call_lock; + void set_async_breakpoint(unsigned long *epc) { /* skip breaking into userland */ if ((*epc & 0x80000000) == 0) return; +#ifdef CONFIG_SMP /* avoid deadlock if someone is make IPC */ if (spin_is_locked(&smp_call_lock)) return; +#endif async_bp.addr = *epc; *epc = (unsigned long)async_breakpoint; diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/genex.S linux-2.6.12.6/arch/mips/kernel/genex.S --- linux-2.6.12.6.orig/arch/mips/kernel/genex.S 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/genex.S 2005-10-02 23:47:36.000000000 +0000 @@ -82,7 +82,7 @@ li k0, 14<<2 beq k1, k0, handle_vcei #ifdef CONFIG_MIPS64 - dsll k1, k1, 1 + dsll k1, k1, 1 #endif .set pop PTR_L k0, exception_handlers(k1) @@ -90,17 +90,17 @@ /* * Big shit, we now may have two dirty primary cache lines for the same - * physical address. We can savely invalidate the line pointed to by + * physical address. We can safely invalidate the line pointed to by * c0_badvaddr because after return from this exception handler the * load / store will be re-executed. */ handle_vced: - DMFC0 k0, CP0_BADVADDR + MFC0 k0, CP0_BADVADDR li k1, -4 # Is this ... and k0, k1 # ... really needed? mtc0 zero, CP0_TAGLO - cache Index_Store_Tag_D,(k0) - cache Hit_Writeback_Inv_SD,(k0) + cache Index_Store_Tag_D, (k0) + cache Hit_Writeback_Inv_SD, (k0) #ifdef CONFIG_PROC_FS PTR_LA k0, vced_count lw k1, (k0) @@ -291,6 +291,7 @@ BUILD_HANDLER mdmx mdmx sti silent /* #22 */ BUILD_HANDLER watch watch sti verbose /* #23 */ BUILD_HANDLER mcheck mcheck cli verbose /* #24 */ + BUILD_HANDLER dsp dsp sti silent /* #26 */ BUILD_HANDLER reserved reserved sti verbose /* others */ #ifdef CONFIG_MIPS64 diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/genrtc.c linux-2.6.12.6/arch/mips/kernel/genrtc.c --- linux-2.6.12.6.orig/arch/mips/kernel/genrtc.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/genrtc.c 2005-10-02 23:47:36.000000000 +0000 @@ -14,7 +14,7 @@ #include #include -static spinlock_t mips_rtc_lock = SPIN_LOCK_UNLOCKED; +static DEFINE_SPINLOCK(mips_rtc_lock); unsigned int get_rtc_time(struct rtc_time *time) { diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/head.S linux-2.6.12.6/arch/mips/kernel/head.S --- linux-2.6.12.6.orig/arch/mips/kernel/head.S 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/head.S 2005-10-02 23:47:36.000000000 +0000 @@ -157,6 +157,7 @@ LONG_S a2, fw_arg2 LONG_S a3, fw_arg3 + MTC0 zero, CP0_CONTEXT # clear context register PTR_LA $28, init_thread_union PTR_ADDIU sp, $28, _THREAD_SIZE - 32 set_saved_sp sp, t0, t1 @@ -200,19 +201,13 @@ .comm fw_arg2, SZREG, SZREG .comm fw_arg3, SZREG, SZREG - .macro page name, order=0 - .globl \name -\name: .size \name, (_PAGE_SIZE << \order) - .org . + (_PAGE_SIZE << \order) - .type \name, @object + .macro page name, order + .comm \name, (_PAGE_SIZE << \order), (_PAGE_SIZE << \order) .endm - .data - .align PAGE_SHIFT - /* - * ... but on 64-bit we've got three-level pagetables with a - * slightly different layout ... + * On 64-bit we've got three-level pagetables with a slightly + * different layout ... */ page swapper_pg_dir, _PGD_ORDER #ifdef CONFIG_MIPS64 diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/i8259.c linux-2.6.12.6/arch/mips/kernel/i8259.c --- linux-2.6.12.6.orig/arch/mips/kernel/i8259.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/i8259.c 2005-10-02 23:47:36.000000000 +0000 @@ -31,7 +31,7 @@ * moves to arch independent land */ -spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED; +DEFINE_SPINLOCK(i8259A_lock); static void end_8259A_irq (unsigned int irq) { @@ -52,14 +52,13 @@ } static struct hw_interrupt_type i8259A_irq_type = { - "XT-PIC", - startup_8259A_irq, - shutdown_8259A_irq, - enable_8259A_irq, - disable_8259A_irq, - mask_and_ack_8259A, - end_8259A_irq, - NULL + .typename = "XT-PIC", + .startup = startup_8259A_irq, + .shutdown = shutdown_8259A_irq, + .enable = enable_8259A_irq, + .disable = disable_8259A_irq, + .ack = mask_and_ack_8259A, + .end = end_8259A_irq, }; /* @@ -322,7 +321,7 @@ for (i = 0; i < 16; i++) { irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; + irq_desc[i].action = NULL; irq_desc[i].depth = 1; irq_desc[i].handler = &i8259A_irq_type; } diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/irixelf.c linux-2.6.12.6/arch/mips/kernel/irixelf.c --- linux-2.6.12.6.orig/arch/mips/kernel/irixelf.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/irixelf.c 2005-10-02 23:47:36.000000000 +0000 @@ -8,7 +8,7 @@ * * Copyright (C) 1993 - 1994 Eric Youngdale * Copyright (C) 1996 - 2004 David S. Miller - * Copyright (C) 2004 Steven J. Hill + * Copyright (C) 2004 - 2005 Steven J. Hill */ #include #include @@ -31,15 +31,16 @@ #include #include -#include #include +#include #include +#include #define DLINFO_ITEMS 12 #include -#undef DEBUG_ELF +#undef DEBUG static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs); static int load_irix_library(struct file *); @@ -55,7 +56,7 @@ #define elf_addr_t unsigned long #endif -#ifdef DEBUG_ELF +#ifdef DEBUG /* Debugging routines. */ static char *get_elf_p_type(Elf32_Word p_type) { @@ -120,7 +121,7 @@ print_phdr(i, ep); } } -#endif /* (DEBUG_ELF) */ +#endif /* DEBUG */ static void set_brk(unsigned long start, unsigned long end) { @@ -146,20 +147,20 @@ nbyte = elf_bss & (PAGE_SIZE-1); if (nbyte) { nbyte = PAGE_SIZE - nbyte; - clear_user((void *) elf_bss, nbyte); + clear_user((void __user *) elf_bss, nbyte); } } -unsigned long * create_irix_tables(char * p, int argc, int envc, - struct elfhdr * exec, unsigned int load_addr, - unsigned int interp_load_addr, - struct pt_regs *regs, struct elf_phdr *ephdr) +static unsigned long * create_irix_tables(char * p, int argc, int envc, + struct elfhdr * exec, unsigned int load_addr, + unsigned int interp_load_addr, struct pt_regs *regs, + struct elf_phdr *ephdr) { elf_addr_t *argv; elf_addr_t *envp; elf_addr_t *sp, *csp; -#ifdef DEBUG_ELF +#ifdef DEBUG printk("create_irix_tables: p[%p] argc[%d] envc[%d] " "load_addr[%08x] interp_load_addr[%08x]\n", p, argc, envc, load_addr, interp_load_addr); @@ -248,14 +249,13 @@ last_bss = 0; error = load_addr = 0; -#ifdef DEBUG_ELF +#ifdef DEBUG print_elfhdr(interp_elf_ex); #endif /* First of all, some simple consistency checks */ if ((interp_elf_ex->e_type != ET_EXEC && interp_elf_ex->e_type != ET_DYN) || - !irix_elf_check_arch(interp_elf_ex) || !interpreter->f_op->mmap) { printk("IRIX interp has bad e_type %d\n", interp_elf_ex->e_type); return 0xffffffff; @@ -290,7 +290,7 @@ (char *) elf_phdata, sizeof(struct elf_phdr) * interp_elf_ex->e_phnum); -#ifdef DEBUG_ELF +#ifdef DEBUG dump_phdrs(elf_phdata, interp_elf_ex->e_phnum); #endif @@ -306,13 +306,11 @@ elf_type |= MAP_FIXED; vaddr = eppnt->p_vaddr; -#ifdef DEBUG_ELF - printk("INTERP do_mmap(%p, %08lx, %08lx, %08lx, %08lx, %08lx) ", + pr_debug("INTERP do_mmap(%p, %08lx, %08lx, %08lx, %08lx, %08lx) ", interpreter, vaddr, (unsigned long) (eppnt->p_filesz + (eppnt->p_vaddr & 0xfff)), (unsigned long) elf_prot, (unsigned long) elf_type, (unsigned long) (eppnt->p_offset & 0xfffff000)); -#endif down_write(¤t->mm->mmap_sem); error = do_mmap(interpreter, vaddr, eppnt->p_filesz + (eppnt->p_vaddr & 0xfff), @@ -324,14 +322,10 @@ printk("Aieee IRIX interp mmap error=%d\n", error); break; /* Real error */ } -#ifdef DEBUG_ELF - printk("error=%08lx ", (unsigned long) error); -#endif + pr_debug("error=%08lx ", (unsigned long) error); if(!load_addr && interp_elf_ex->e_type == ET_DYN) { load_addr = error; -#ifdef DEBUG_ELF - printk("load_addr = error "); -#endif + pr_debug("load_addr = error "); } /* Find the end of the file mapping for this phdr, and keep @@ -345,17 +339,13 @@ */ k = eppnt->p_memsz + eppnt->p_vaddr; if(k > last_bss) last_bss = k; -#ifdef DEBUG_ELF - printk("\n"); -#endif + pr_debug("\n"); } } /* Now use mmap to map the library into memory. */ if(error < 0 && error > -1024) { -#ifdef DEBUG_ELF - printk("got error %d\n", error); -#endif + pr_debug("got error %d\n", error); kfree(elf_phdata); return 0xffffffff; } @@ -365,16 +355,12 @@ * that there are zero-mapped pages up to and including the * last bss page. */ -#ifdef DEBUG_ELF - printk("padzero(%08lx) ", (unsigned long) (elf_bss)); -#endif + pr_debug("padzero(%08lx) ", (unsigned long) (elf_bss)); padzero(elf_bss); len = (elf_bss + 0xfff) & 0xfffff000; /* What we have mapped so far */ -#ifdef DEBUG_ELF - printk("last_bss[%08lx] len[%08lx]\n", (unsigned long) last_bss, - (unsigned long) len); -#endif + pr_debug("last_bss[%08lx] len[%08lx]\n", (unsigned long) last_bss, + (unsigned long) len); /* Map the last of the bss segment */ if (last_bss > len) { @@ -396,12 +382,7 @@ /* First of all, some simple consistency checks */ if((ehp->e_type != ET_EXEC && ehp->e_type != ET_DYN) || - !irix_elf_check_arch(ehp) || !bprm->file->f_op->mmap) { - return -ENOEXEC; - } - - /* Only support MIPS ARCH2 or greater IRIX binaries for now. */ - if(!(ehp->e_flags & EF_MIPS_ARCH) && !(ehp->e_flags & 0x04)) { + !bprm->file->f_op->mmap) { return -ENOEXEC; } @@ -411,16 +392,17 @@ * XXX all registers as 64bits on cpu's capable of this at * XXX exception time plus frob the XTLB exception vector. */ - if((ehp->e_flags & 0x20)) { + if((ehp->e_flags & EF_MIPS_ABI2)) return -ENOEXEC; - } - return 0; /* It's ok. */ + return 0; } -#define IRIX_INTERP_PREFIX "/usr/gnemul/irix" - -/* Look for an IRIX ELF interpreter. */ +/* + * This is where the detailed check is performed. Irix binaries + * use interpreters with 'libc.so' in the name, so this function + * can differentiate between Linux and Irix binaries. + */ static inline int look_for_irix_interpreter(char **name, struct file **interpreter, struct elfhdr *interp_elf_ex, @@ -440,12 +422,13 @@ if (*name != NULL) goto out; - *name = kmalloc((epp->p_filesz + strlen(IRIX_INTERP_PREFIX)), - GFP_KERNEL); + *name = (char *) kmalloc((epp->p_filesz + + strlen(IRIX_EMUL)), + GFP_KERNEL); if (!*name) return -ENOMEM; - strcpy(*name, IRIX_INTERP_PREFIX); + strcpy(*name, IRIX_EMUL); retval = kernel_read(bprm->file, epp->p_offset, (*name + 16), epp->p_filesz); if (retval < 0) @@ -562,7 +545,7 @@ * process and the system, here we map the page and fill the * structure */ -void irix_map_prda_page (void) +static void irix_map_prda_page(void) { unsigned long v; struct prda *pp; @@ -601,14 +584,33 @@ load_addr = 0; has_interp = has_ephdr = 0; - elf_ihdr = elf_ephdr = 0; + elf_ihdr = elf_ephdr = NULL; elf_ex = *((struct elfhdr *) bprm->buf); retval = -ENOEXEC; if (verify_binary(&elf_ex, bprm)) goto out; -#ifdef DEBUG_ELF + /* + * Telling -o32 static binaries from Linux and Irix apart from each + * other is difficult. There are 2 differences to be noted for static + * binaries from the 2 operating systems: + * + * 1) Irix binaries have their .text section before their .init + * section. Linux binaries are just the opposite. + * + * 2) Irix binaries usually have <= 12 sections and Linux + * binaries have > 20. + * + * We will use Method #2 since Method #1 would require us to read in + * the section headers which is way too much overhead. This appears + * to work for everything we have ran into so far. If anyone has a + * better method to tell the binaries apart, I'm listening. + */ + if (elf_ex.e_shnum > 20) + goto out; + +#ifdef DEBUG print_elfhdr(&elf_ex); #endif @@ -623,11 +625,10 @@ } retval = kernel_read(bprm->file, elf_ex.e_phoff, (char *)elf_phdata, size); - if (retval < 0) goto out_free_ph; -#ifdef DEBUG_ELF +#ifdef DEBUG dump_phdrs(elf_phdata, elf_ex.e_phnum); #endif @@ -644,9 +645,8 @@ break; }; } -#ifdef DEBUG_ELF - printk("\n"); -#endif + + pr_debug("\n"); elf_bss = 0; elf_brk = 0; @@ -657,12 +657,19 @@ end_code = 0; end_data = 0; - retval = look_for_irix_interpreter(&elf_interpreter, - &interpreter, + /* + * If we get a return value, we change the value to be ENOEXEC + * so that we can exit gracefully and the main binary format + * search loop in 'fs/exec.c' will move onto the next handler + * which should be the normal ELF binary handler. + */ + retval = look_for_irix_interpreter(&elf_interpreter, &interpreter, &interp_elf_ex, elf_phdata, bprm, elf_ex.e_phnum); - if (retval) + if (retval) { + retval = -ENOEXEC; goto out_free_file; + } if (elf_interpreter) { retval = verify_irix_interpreter(&interp_elf_ex); @@ -746,18 +753,16 @@ * IRIX maps a page at 0x200000 which holds some system * information. Programs depend on this. */ - irix_map_prda_page (); + irix_map_prda_page(); padzero(elf_bss); -#ifdef DEBUG_ELF - printk("(start_brk) %lx\n" , (long) current->mm->start_brk); - printk("(end_code) %lx\n" , (long) current->mm->end_code); - printk("(start_code) %lx\n" , (long) current->mm->start_code); - printk("(end_data) %lx\n" , (long) current->mm->end_data); - printk("(start_stack) %lx\n" , (long) current->mm->start_stack); - printk("(brk) %lx\n" , (long) current->mm->brk); -#endif + pr_debug("(start_brk) %lx\n" , (long) current->mm->start_brk); + pr_debug("(end_code) %lx\n" , (long) current->mm->end_code); + pr_debug("(start_code) %lx\n" , (long) current->mm->start_code); + pr_debug("(end_data) %lx\n" , (long) current->mm->end_data); + pr_debug("(start_stack) %lx\n" , (long) current->mm->start_stack); + pr_debug("(brk) %lx\n" , (long) current->mm->brk); #if 0 /* XXX No fucking way dude... */ /* Why this, you ask??? Well SVr4 maps page 0 as read-only, @@ -813,7 +818,7 @@ /* First of all, some simple consistency checks. */ if(elf_ex.e_type != ET_EXEC || elf_ex.e_phnum > 2 || - !irix_elf_check_arch(&elf_ex) || !file->f_op->mmap) + !file->f_op->mmap) return -ENOEXEC; /* Now read in all of the header information. */ @@ -874,35 +879,36 @@ * phdrs there are in the USER_PHDRP array. We return the vaddr the * first phdr was successfully mapped to. */ -unsigned long irix_mapelf(int fd, struct elf_phdr *user_phdrp, int cnt) +unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt) { - struct elf_phdr *hp; + unsigned long type, vaddr, filesz, offset, flags; + struct elf_phdr __user *hp; struct file *filp; int i, retval; -#ifdef DEBUG_ELF - printk("irix_mapelf: fd[%d] user_phdrp[%p] cnt[%d]\n", - fd, user_phdrp, cnt); -#endif + pr_debug("irix_mapelf: fd[%d] user_phdrp[%p] cnt[%d]\n", + fd, user_phdrp, cnt); /* First get the verification out of the way. */ hp = user_phdrp; if (!access_ok(VERIFY_READ, hp, (sizeof(struct elf_phdr) * cnt))) { -#ifdef DEBUG_ELF - printk("irix_mapelf: access_ok fails!\n"); -#endif + pr_debug("irix_mapelf: bad pointer to ELF PHDR!\n"); + return -EFAULT; } -#ifdef DEBUG_ELF +#ifdef DEBUG dump_phdrs(user_phdrp, cnt); #endif - for(i = 0; i < cnt; i++, hp++) - if(hp->p_type != PT_LOAD) { + for (i = 0; i < cnt; i++, hp++) { + if (__get_user(type, &hp->p_type)) + return -EFAULT; + if (type != PT_LOAD) { printk("irix_mapelf: One section is not PT_LOAD!\n"); return -ENOEXEC; } + } filp = fget(fd); if (!filp) @@ -917,29 +923,40 @@ for(i = 0; i < cnt; i++, hp++) { int prot; - prot = (hp->p_flags & PF_R) ? PROT_READ : 0; - prot |= (hp->p_flags & PF_W) ? PROT_WRITE : 0; - prot |= (hp->p_flags & PF_X) ? PROT_EXEC : 0; + retval = __get_user(vaddr, &hp->p_vaddr); + retval |= __get_user(filesz, &hp->p_filesz); + retval |= __get_user(offset, &hp->p_offset); + retval |= __get_user(flags, &hp->p_flags); + if (retval) + return retval; + + prot = (flags & PF_R) ? PROT_READ : 0; + prot |= (flags & PF_W) ? PROT_WRITE : 0; + prot |= (flags & PF_X) ? PROT_EXEC : 0; + down_write(¤t->mm->mmap_sem); - retval = do_mmap(filp, (hp->p_vaddr & 0xfffff000), - (hp->p_filesz + (hp->p_vaddr & 0xfff)), + retval = do_mmap(filp, (vaddr & 0xfffff000), + (filesz + (vaddr & 0xfff)), prot, (MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE), - (hp->p_offset & 0xfffff000)); + (offset & 0xfffff000)); up_write(¤t->mm->mmap_sem); - if(retval != (hp->p_vaddr & 0xfffff000)) { + if (retval != (vaddr & 0xfffff000)) { printk("irix_mapelf: do_mmap fails with %d!\n", retval); fput(filp); return retval; } } -#ifdef DEBUG_ELF - printk("irix_mapelf: Success, returning %08lx\n", - (unsigned long) user_phdrp->p_vaddr); -#endif + pr_debug("irix_mapelf: Success, returning %08lx\n", + (unsigned long) user_phdrp->p_vaddr); + fput(filp); - return user_phdrp->p_vaddr; + + if (__get_user(vaddr, &user_phdrp->p_vaddr)) + return -EFAULT; + + return vaddr; } /* @@ -952,9 +969,9 @@ /* These are the only things you should do on a core-file: use only these * functions to write out all the necessary info. */ -static int dump_write(struct file *file, const void *addr, int nr) +static int dump_write(struct file *file, const void __user *addr, int nr) { - return file->f_op->write(file, addr, nr, &file->f_pos) == nr; + return file->f_op->write(file, (const char __user *) addr, nr, &file->f_pos) == nr; } static int dump_seek(struct file *file, off_t off) @@ -1073,7 +1090,7 @@ /* Count what's needed to dump, up to the limit of coredump size. */ segs = 0; size = 0; - for(vma = current->mm->mmap; vma != NULL; vma = vma->vm_next) { + for (vma = current->mm->mmap; vma != NULL; vma = vma->vm_next) { if (maydump(vma)) { int sz = vma->vm_end-vma->vm_start; @@ -1187,9 +1204,9 @@ len = current->mm->arg_end - current->mm->arg_start; len = len >= ELF_PRARGSZ ? ELF_PRARGSZ : len; - copy_from_user(&psinfo.pr_psargs, - (const char *)current->mm->arg_start, len); - for(i = 0; i < len; i++) + (void *) copy_from_user(&psinfo.pr_psargs, + (const char __user *)current->mm->arg_start, len); + for (i = 0; i < len; i++) if (psinfo.pr_psargs[i] == 0) psinfo.pr_psargs[i] = ' '; psinfo.pr_psargs[len] = 0; @@ -1256,8 +1273,10 @@ phdr.p_memsz = sz; offset += phdr.p_filesz; phdr.p_flags = vma->vm_flags & VM_READ ? PF_R : 0; - if (vma->vm_flags & VM_WRITE) phdr.p_flags |= PF_W; - if (vma->vm_flags & VM_EXEC) phdr.p_flags |= PF_X; + if (vma->vm_flags & VM_WRITE) + phdr.p_flags |= PF_W; + if (vma->vm_flags & VM_EXEC) + phdr.p_flags |= PF_X; phdr.p_align = PAGE_SIZE; DUMP_WRITE(&phdr, sizeof(phdr)); @@ -1283,7 +1302,7 @@ #ifdef DEBUG printk("elf_core_dump: writing %08lx %lx\n", addr, len); #endif - DUMP_WRITE((void *)addr, len); + DUMP_WRITE((void __user *)addr, len); } if ((off_t) file->f_pos != offset) { @@ -1299,7 +1318,7 @@ static int __init init_irix_binfmt(void) { - int init_inventory(void); + extern int init_inventory(void); extern asmlinkage unsigned long sys_call_table; extern asmlinkage unsigned long sys_call_table_irix5; @@ -1318,7 +1337,9 @@ static void __exit exit_irix_binfmt(void) { - /* Remove the IRIX ELF loaders. */ + /* + * Remove the Irix ELF loader. + */ unregister_binfmt(&irix_format); } diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/irixinv.c linux-2.6.12.6/arch/mips/kernel/irixinv.c --- linux-2.6.12.6.orig/arch/mips/kernel/irixinv.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/irixinv.c 2005-10-02 23:47:36.000000000 +0000 @@ -30,10 +30,10 @@ inventory_items++; } -int dump_inventory_to_user (void *userbuf, int size) +int dump_inventory_to_user (void __user *userbuf, int size) { inventory_t *inv = &inventory [0]; - inventory_t *user = userbuf; + inventory_t __user *user = userbuf; int v; if (!access_ok(VERIFY_WRITE, userbuf, size)) @@ -41,7 +41,8 @@ for (v = 0; v < inventory_items; v++){ inv = &inventory [v]; - copy_to_user (user, inv, sizeof (inventory_t)); + if (copy_to_user (user, inv, sizeof (inventory_t))) + return -EFAULT; user++; } return inventory_items * sizeof (inventory_t); diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/irixioctl.c linux-2.6.12.6/arch/mips/kernel/irixioctl.c --- linux-2.6.12.6.orig/arch/mips/kernel/irixioctl.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/irixioctl.c 2005-10-02 23:47:36.000000000 +0000 @@ -58,7 +58,7 @@ { struct tty_struct *tp, *rtp; mm_segment_t old_fs; - int error = 0; + int i, error = 0; #ifdef DEBUG_IOCTLS printk("[%s:%d] irix_ioctl(%d, ", current->comm, current->pid, fd); @@ -73,12 +73,13 @@ case 0x0000540d: { struct termios kt; - struct irix_termios *it = (struct irix_termios *) arg; + struct irix_termios __user *it = + (struct irix_termios __user *) arg; #ifdef DEBUG_IOCTLS printk("TCGETS, %08lx) ", arg); #endif - if(!access_ok(VERIFY_WRITE, it, sizeof(*it))) { + if (!access_ok(VERIFY_WRITE, it, sizeof(*it))) { error = -EFAULT; break; } @@ -87,13 +88,14 @@ set_fs(old_fs); if (error) break; - __put_user(kt.c_iflag, &it->c_iflag); - __put_user(kt.c_oflag, &it->c_oflag); - __put_user(kt.c_cflag, &it->c_cflag); - __put_user(kt.c_lflag, &it->c_lflag); - for(error = 0; error < NCCS; error++) - __put_user(kt.c_cc[error], &it->c_cc[error]); - error = 0; + + error = __put_user(kt.c_iflag, &it->c_iflag); + error |= __put_user(kt.c_oflag, &it->c_oflag); + error |= __put_user(kt.c_cflag, &it->c_cflag); + error |= __put_user(kt.c_lflag, &it->c_lflag); + + for (i = 0; i < NCCS; i++) + error |= __put_user(kt.c_cc[i], &it->c_cc[i]); break; } @@ -111,14 +113,19 @@ old_fs = get_fs(); set_fs(get_ds()); error = sys_ioctl(fd, TCGETS, (unsigned long) &kt); set_fs(old_fs); - if(error) + if (error) + break; + + error = __get_user(kt.c_iflag, &it->c_iflag); + error |= __get_user(kt.c_oflag, &it->c_oflag); + error |= __get_user(kt.c_cflag, &it->c_cflag); + error |= __get_user(kt.c_lflag, &it->c_lflag); + + for (i = 0; i < NCCS; i++) + error |= __get_user(kt.c_cc[i], &it->c_cc[i]); + + if (error) break; - __get_user(kt.c_iflag, &it->c_iflag); - __get_user(kt.c_oflag, &it->c_oflag); - __get_user(kt.c_cflag, &it->c_cflag); - __get_user(kt.c_lflag, &it->c_lflag); - for(error = 0; error < NCCS; error++) - __get_user(kt.c_cc[error], &it->c_cc[error]); old_fs = get_fs(); set_fs(get_ds()); error = sys_ioctl(fd, TCSETS, (unsigned long) &kt); set_fs(old_fs); @@ -152,7 +159,7 @@ #ifdef DEBUG_IOCTLS printk("rtp->session=%d ", rtp->session); #endif - error = put_user(rtp->session, (unsigned long *) arg); + error = put_user(rtp->session, (unsigned long __user *) arg); break; case 0x746e: @@ -194,50 +201,32 @@ break; case 0x8004667e: -#ifdef DEBUG_IOCTLS - printk("FIONBIO, %08lx) arg=%d ", arg, *(int *)arg); -#endif error = sys_ioctl(fd, FIONBIO, arg); break; case 0x80047476: -#ifdef DEBUG_IOCTLS - printk("TIOCSPGRP, %08lx) arg=%d ", arg, *(int *)arg); -#endif error = sys_ioctl(fd, TIOCSPGRP, arg); break; case 0x8020690c: -#ifdef DEBUG_IOCTLS - printk("SIOCSIFADDR, %08lx) arg=%d ", arg, *(int *)arg); -#endif error = sys_ioctl(fd, SIOCSIFADDR, arg); break; case 0x80206910: -#ifdef DEBUG_IOCTLS - printk("SIOCSIFFLAGS, %08lx) arg=%d ", arg, *(int *)arg); -#endif error = sys_ioctl(fd, SIOCSIFFLAGS, arg); break; case 0xc0206911: -#ifdef DEBUG_IOCTLS - printk("SIOCGIFFLAGS, %08lx) arg=%d ", arg, *(int *)arg); -#endif error = sys_ioctl(fd, SIOCGIFFLAGS, arg); break; case 0xc020691b: -#ifdef DEBUG_IOCTLS - printk("SIOCGIFMETRIC, %08lx) arg=%d ", arg, *(int *)arg); -#endif error = sys_ioctl(fd, SIOCGIFMETRIC, arg); break; default: { #ifdef DEBUG_MISSING_IOCTL - char *msg = "Unimplemented IOCTL cmd tell linux@engr.sgi.com\n"; + char *msg = "Unimplemented IOCTL cmd tell linux-mips@linux-mips.org\n"; #ifdef DEBUG_IOCTLS printk("UNIMP_IOCTL, %08lx)\n", arg); diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/irixsig.c linux-2.6.12.6/arch/mips/kernel/irixsig.c --- linux-2.6.12.6.orig/arch/mips/kernel/irixsig.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/irixsig.c 2005-10-02 23:47:36.000000000 +0000 @@ -79,33 +79,36 @@ static void setup_irix_frame(struct k_sigaction *ka, struct pt_regs *regs, int signr, sigset_t *oldmask) { + struct sigctx_irix5 __user *ctx; unsigned long sp; - struct sigctx_irix5 *ctx; - int i; + int error, i; sp = regs->regs[29]; sp -= sizeof(struct sigctx_irix5); sp &= ~(0xf); - ctx = (struct sigctx_irix5 *) sp; + ctx = (struct sigctx_irix5 __user *) sp; if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx))) goto segv_and_exit; - __put_user(0, &ctx->weird_fpu_thing); - __put_user(~(0x00000001), &ctx->rmask); - __put_user(0, &ctx->regs[0]); + error = __put_user(0, &ctx->weird_fpu_thing); + error |= __put_user(~(0x00000001), &ctx->rmask); + error |= __put_user(0, &ctx->regs[0]); for(i = 1; i < 32; i++) - __put_user((u64) regs->regs[i], &ctx->regs[i]); + error |= __put_user((u64) regs->regs[i], &ctx->regs[i]); - __put_user((u64) regs->hi, &ctx->hi); - __put_user((u64) regs->lo, &ctx->lo); - __put_user((u64) regs->cp0_epc, &ctx->pc); - __put_user(!!used_math(), &ctx->usedfp); - __put_user((u64) regs->cp0_cause, &ctx->cp0_cause); - __put_user((u64) regs->cp0_badvaddr, &ctx->cp0_badvaddr); + error |= __put_user((u64) regs->hi, &ctx->hi); + error |= __put_user((u64) regs->lo, &ctx->lo); + error |= __put_user((u64) regs->cp0_epc, &ctx->pc); + error |= __put_user(!!used_math(), &ctx->usedfp); + error |= __put_user((u64) regs->cp0_cause, &ctx->cp0_cause); + error |= __put_user((u64) regs->cp0_badvaddr, &ctx->cp0_badvaddr); - __put_user(0, &ctx->sstk_flags); /* XXX sigstack unimp... todo... */ + error |= __put_user(0, &ctx->sstk_flags); /* XXX sigstack unimp... todo... */ - __copy_to_user(&ctx->sigset, oldmask, sizeof(irix_sigset_t)); + error |= __copy_to_user(&ctx->sigset, oldmask, sizeof(irix_sigset_t)) ? -EFAULT : 0; + + if (error) + goto segv_and_exit; #ifdef DEBUG_SIG dump_irix5_sigctx(ctx); @@ -209,10 +212,11 @@ asmlinkage void irix_sigreturn(struct pt_regs *regs) { - struct sigctx_irix5 *context, *magic; + struct sigctx_irix5 __user *context, *magic; unsigned long umask, mask; u64 *fregs; - int sig, i, base = 0; + u32 usedfp; + int error, sig, i, base = 0; sigset_t blocked; /* Always make any pending restarted system calls return -EINTR */ @@ -221,8 +225,8 @@ if (regs->regs[2] == 1000) base = 1; - context = (struct sigctx_irix5 *) regs->regs[base + 4]; - magic = (struct sigctx_irix5 *) regs->regs[base + 5]; + context = (struct sigctx_irix5 __user *) regs->regs[base + 4]; + magic = (struct sigctx_irix5 __user *) regs->regs[base + 5]; sig = (int) regs->regs[base + 6]; #ifdef DEBUG_SIG printk("[%s:%d] IRIX sigreturn(scp[%p],ucp[%p],sig[%d])\n", @@ -237,25 +241,31 @@ dump_irix5_sigctx(context); #endif - __get_user(regs->cp0_epc, &context->pc); - umask = context->rmask; mask = 2; + error = __get_user(regs->cp0_epc, &context->pc); + error |= __get_user(umask, &context->rmask); + + mask = 2; for (i = 1; i < 32; i++, mask <<= 1) { - if(umask & mask) - __get_user(regs->regs[i], &context->regs[i]); + if (umask & mask) + error |= __get_user(regs->regs[i], &context->regs[i]); } - __get_user(regs->hi, &context->hi); - __get_user(regs->lo, &context->lo); + error |= __get_user(regs->hi, &context->hi); + error |= __get_user(regs->lo, &context->lo); - if ((umask & 1) && context->usedfp) { + error |= __get_user(usedfp, &context->usedfp); + if ((umask & 1) && usedfp) { fregs = (u64 *) ¤t->thread.fpu; + for(i = 0; i < 32; i++) - fregs[i] = (u64) context->fpregs[i]; - __get_user(current->thread.fpu.hard.fcr31, &context->fpcsr); + error |= __get_user(fregs[i], &context->fpregs[i]); + error |= __get_user(current->thread.fpu.hard.fcr31, &context->fpcsr); } /* XXX do sigstack crapola here... XXX */ - if (__copy_from_user(&blocked, &context->sigset, sizeof(blocked))) + error |= __copy_from_user(&blocked, &context->sigset, sizeof(blocked)) ? -EFAULT : 0; + + if (error) goto badframe; sigdelsetmask(&blocked, ~_BLOCKABLE); @@ -297,8 +307,8 @@ #endif asmlinkage int -irix_sigaction(int sig, const struct sigaction *act, - struct sigaction *oact, void *trampoline) +irix_sigaction(int sig, const struct sigaction __user *act, + struct sigaction __user *oact, void __user *trampoline) { struct k_sigaction new_ka, old_ka; int ret; @@ -312,12 +322,16 @@ #endif if (act) { sigset_t mask; - if (!access_ok(VERIFY_READ, act, sizeof(*act)) || - __get_user(new_ka.sa.sa_handler, &act->sa_handler) || - __get_user(new_ka.sa.sa_flags, &act->sa_flags)) + int err; + + if (!access_ok(VERIFY_READ, act, sizeof(*act))) return -EFAULT; + err = __get_user(new_ka.sa.sa_handler, &act->sa_handler); + err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags); - __copy_from_user(&mask, &act->sa_mask, sizeof(sigset_t)); + err |= __copy_from_user(&mask, &act->sa_mask, sizeof(sigset_t)) ? -EFAULT : 0; + if (err) + return err; /* * Hmmm... methinks IRIX libc always passes a valid trampoline @@ -331,30 +345,37 @@ ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); if (!ret && oact) { - if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || - __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || - __put_user(old_ka.sa.sa_flags, &oact->sa_flags)) + int err; + + if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact))) + return -EFAULT; + + err = __put_user(old_ka.sa.sa_handler, &oact->sa_handler); + err |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags); + err |= __copy_to_user(&oact->sa_mask, &old_ka.sa.sa_mask, + sizeof(sigset_t)) ? -EFAULT : 0; + if (err) return -EFAULT; - __copy_to_user(&old_ka.sa.sa_mask, &oact->sa_mask, - sizeof(sigset_t)); } return ret; } -asmlinkage int irix_sigpending(irix_sigset_t *set) +asmlinkage int irix_sigpending(irix_sigset_t __user *set) { return do_sigpending(set, sizeof(*set)); } -asmlinkage int irix_sigprocmask(int how, irix_sigset_t *new, irix_sigset_t *old) +asmlinkage int irix_sigprocmask(int how, irix_sigset_t __user *new, + irix_sigset_t __user *old) { sigset_t oldbits, newbits; if (new) { if (!access_ok(VERIFY_READ, new, sizeof(*new))) return -EFAULT; - __copy_from_user(&newbits, new, sizeof(unsigned long)*4); + if (__copy_from_user(&newbits, new, sizeof(unsigned long)*4)) + return -EFAULT; sigdelsetmask(&newbits, ~_BLOCKABLE); spin_lock_irq(¤t->sighand->siglock); @@ -382,20 +403,19 @@ recalc_sigpending(); spin_unlock_irq(¤t->sighand->siglock); } - if(old) { - if (!access_ok(VERIFY_WRITE, old, sizeof(*old))) - return -EFAULT; - __copy_to_user(old, ¤t->blocked, sizeof(unsigned long)*4); - } + if (old) + return copy_to_user(old, ¤t->blocked, + sizeof(unsigned long)*4) ? -EFAULT : 0; return 0; } asmlinkage int irix_sigsuspend(struct pt_regs *regs) { - sigset_t *uset, saveset, newset; + sigset_t saveset, newset; + sigset_t __user *uset; - uset = (sigset_t *) regs->regs[4]; + uset = (sigset_t __user *) regs->regs[4]; if (copy_from_user(&newset, uset, sizeof(sigset_t))) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); @@ -453,12 +473,13 @@ return HZ * sec + nsec; } -asmlinkage int irix_sigpoll_sys(unsigned long *set, struct irix5_siginfo *info, - struct timespec *tp) +asmlinkage int irix_sigpoll_sys(unsigned long __user *set, + struct irix5_siginfo __user *info, struct timespec __user *tp) { long expire = MAX_SCHEDULE_TIMEOUT; sigset_t kset; int i, sig, error, timeo = 0; + struct timespec ktp; #ifdef DEBUG_SIG printk("[%s:%d] irix_sigpoll_sys(%p,%p,%p)\n", @@ -469,14 +490,8 @@ if (!set) return -EINVAL; - if (!access_ok(VERIFY_READ, set, sizeof(kset))) { - error = -EFAULT; - goto out; - } - - __copy_from_user(&kset, set, sizeof(set)); - if (error) - goto out; + if (copy_from_user(&kset, set, sizeof(set))) + return -EFAULT; if (info && clear_user(info, sizeof(*info))) { error = -EFAULT; @@ -484,13 +499,13 @@ } if (tp) { - if (!access_ok(VERIFY_READ, tp, sizeof(*tp))) + if (copy_from_user(&ktp, tp, sizeof(*tp))) return -EFAULT; - if (!tp->tv_sec && !tp->tv_nsec) { - error = -EINVAL; - goto out; - } - expire = timespectojiffies(tp)+(tp->tv_sec||tp->tv_nsec); + + if (!ktp.tv_sec && !ktp.tv_nsec) + return -EINVAL; + + expire = timespectojiffies(&ktp) + (ktp.tv_sec || ktp.tv_nsec); } while(1) { @@ -514,15 +529,14 @@ if (timeo) return -EAGAIN; - for(sig = 1; i <= 65 /* IRIX_NSIG */; sig++) { + for (sig = 1; i <= 65 /* IRIX_NSIG */; sig++) { if (sigismember (&kset, sig)) continue; if (sigismember (¤t->pending.signal, sig)) { /* XXX need more than this... */ if (info) - info->sig = sig; - error = 0; - goto out; + return copy_to_user(&info->sig, &sig, sizeof(sig)); + return 0; } } @@ -548,8 +562,9 @@ #define W_MASK (W_EXITED | W_TRAPPED | W_STOPPED | W_CONT | W_NOHANG) -asmlinkage int irix_waitsys(int type, int pid, struct irix5_siginfo *info, - int options, struct rusage *ru) +asmlinkage int irix_waitsys(int type, int pid, + struct irix5_siginfo __user *info, int options, + struct rusage __user *ru) { int flag, retval; DECLARE_WAITQUEUE(wait, current); @@ -557,28 +572,22 @@ struct task_struct *p; struct list_head *_p; - if (!info) { - retval = -EINVAL; - goto out; - } - if (!access_ok(VERIFY_WRITE, info, sizeof(*info))) { - retval = -EFAULT; - goto out; - } - if (ru) { - if (!access_ok(VERIFY_WRITE, ru, sizeof(*ru))) { - retval = -EFAULT; - goto out; - } - } - if (options & ~(W_MASK)) { - retval = -EINVAL; - goto out; - } - if (type != IRIX_P_PID && type != IRIX_P_PGID && type != IRIX_P_ALL) { - retval = -EINVAL; - goto out; - } + if (!info) + return -EINVAL; + + if (!access_ok(VERIFY_WRITE, info, sizeof(*info))) + return -EFAULT; + + if (ru) + if (!access_ok(VERIFY_WRITE, ru, sizeof(*ru))) + return -EFAULT; + + if (options & ~W_MASK) + return -EINVAL; + + if (type != IRIX_P_PID && type != IRIX_P_PGID && type != IRIX_P_ALL) + return -EINVAL; + add_wait_queue(¤t->signal->wait_chldexit, &wait); repeat: flag = 0; @@ -609,18 +618,20 @@ add_parent(p, p->parent); write_unlock_irq(&tasklist_lock); retval = ru ? getrusage(p, RUSAGE_BOTH, ru) : 0; - if (!retval && ru) { - retval |= __put_user(SIGCHLD, &info->sig); - retval |= __put_user(0, &info->code); - retval |= __put_user(p->pid, &info->stuff.procinfo.pid); - retval |= __put_user((p->exit_code >> 8) & 0xff, - &info->stuff.procinfo.procdata.child.status); - retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime); - retval |= __put_user(p->stime, &info->stuff.procinfo.procdata.child.stime); - } - if (!retval) { - p->exit_code = 0; - } + if (retval) + goto end_waitsys; + + retval = __put_user(SIGCHLD, &info->sig); + retval |= __put_user(0, &info->code); + retval |= __put_user(p->pid, &info->stuff.procinfo.pid); + retval |= __put_user((p->exit_code >> 8) & 0xff, + &info->stuff.procinfo.procdata.child.status); + retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime); + retval |= __put_user(p->stime, &info->stuff.procinfo.procdata.child.stime); + if (retval) + goto end_waitsys; + + p->exit_code = 0; goto end_waitsys; case EXIT_ZOMBIE: @@ -628,16 +639,18 @@ current->signal->cstime += p->stime + p->signal->cstime; if (ru != NULL) getrusage(p, RUSAGE_BOTH, ru); - __put_user(SIGCHLD, &info->sig); - __put_user(1, &info->code); /* CLD_EXITED */ - __put_user(p->pid, &info->stuff.procinfo.pid); - __put_user((p->exit_code >> 8) & 0xff, + retval = __put_user(SIGCHLD, &info->sig); + retval |= __put_user(1, &info->code); /* CLD_EXITED */ + retval |= __put_user(p->pid, &info->stuff.procinfo.pid); + retval |= __put_user((p->exit_code >> 8) & 0xff, &info->stuff.procinfo.procdata.child.status); - __put_user(p->utime, + retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime); - __put_user(p->stime, + retval |= __put_user(p->stime, &info->stuff.procinfo.procdata.child.stime); - retval = 0; + if (retval) + return retval; + if (p->real_parent != p->parent) { write_lock_irq(&tasklist_lock); remove_parent(p); @@ -670,7 +683,6 @@ current->state = TASK_RUNNING; remove_wait_queue(¤t->signal->wait_chldexit, &wait); -out: return retval; } @@ -689,39 +701,39 @@ asmlinkage int irix_getcontext(struct pt_regs *regs) { - int i, base = 0; - struct irix5_context *ctx; + int error, i, base = 0; + struct irix5_context __user *ctx; unsigned long flags; if (regs->regs[2] == 1000) base = 1; - ctx = (struct irix5_context *) regs->regs[base + 4]; + ctx = (struct irix5_context __user *) regs->regs[base + 4]; #ifdef DEBUG_SIG printk("[%s:%d] irix_getcontext(%p)\n", current->comm, current->pid, ctx); #endif - if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx))) + if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx))); return -EFAULT; - __put_user(current->thread.irix_oldctx, &ctx->link); + error = __put_user(current->thread.irix_oldctx, &ctx->link); - __copy_to_user(&ctx->sigmask, ¤t->blocked, sizeof(irix_sigset_t)); + error |= __copy_to_user(&ctx->sigmask, ¤t->blocked, sizeof(irix_sigset_t)) ? -EFAULT : 0; /* XXX Do sigstack stuff someday... */ - __put_user(0, &ctx->stack.sp); - __put_user(0, &ctx->stack.size); - __put_user(0, &ctx->stack.flags); + error |= __put_user(0, &ctx->stack.sp); + error |= __put_user(0, &ctx->stack.size); + error |= __put_user(0, &ctx->stack.flags); - __put_user(0, &ctx->weird_graphics_thing); - __put_user(0, &ctx->regs[0]); + error |= __put_user(0, &ctx->weird_graphics_thing); + error |= __put_user(0, &ctx->regs[0]); for (i = 1; i < 32; i++) - __put_user(regs->regs[i], &ctx->regs[i]); - __put_user(regs->lo, &ctx->regs[32]); - __put_user(regs->hi, &ctx->regs[33]); - __put_user(regs->cp0_cause, &ctx->regs[34]); - __put_user(regs->cp0_epc, &ctx->regs[35]); + error |= __put_user(regs->regs[i], &ctx->regs[i]); + error |= __put_user(regs->lo, &ctx->regs[32]); + error |= __put_user(regs->hi, &ctx->regs[33]); + error |= __put_user(regs->cp0_cause, &ctx->regs[34]); + error |= __put_user(regs->cp0_epc, &ctx->regs[35]); flags = 0x0f; if (!used_math()) { @@ -730,119 +742,124 @@ /* XXX wheee... */ printk("Wheee, no code for saving IRIX FPU context yet.\n"); } - __put_user(flags, &ctx->flags); + error |= __put_user(flags, &ctx->flags); - return 0; + return error; } -asmlinkage unsigned long irix_setcontext(struct pt_regs *regs) +asmlinkage void irix_setcontext(struct pt_regs *regs) { - int error, base = 0; - struct irix5_context *ctx; + struct irix5_context __user *ctx; + int err, base = 0; + u32 flags; - if(regs->regs[2] == 1000) + if (regs->regs[2] == 1000) base = 1; - ctx = (struct irix5_context *) regs->regs[base + 4]; + ctx = (struct irix5_context __user *) regs->regs[base + 4]; #ifdef DEBUG_SIG printk("[%s:%d] irix_setcontext(%p)\n", current->comm, current->pid, ctx); #endif - if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx))) { - error = -EFAULT; - goto out; - } + if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx))) + goto segv_and_exit; - if (ctx->flags & 0x02) { + err = __get_user(flags, &ctx->flags); + if (flags & 0x02) { /* XXX sigstack garbage, todo... */ printk("Wheee, cannot do sigstack stuff in setcontext\n"); } - if (ctx->flags & 0x04) { + if (flags & 0x04) { int i; /* XXX extra control block stuff... todo... */ - for(i = 1; i < 32; i++) - regs->regs[i] = ctx->regs[i]; - regs->lo = ctx->regs[32]; - regs->hi = ctx->regs[33]; - regs->cp0_epc = ctx->regs[35]; + for (i = 1; i < 32; i++) + err |= __get_user(regs->regs[i], &ctx->regs[i]); + err |= __get_user(regs->lo, &ctx->regs[32]); + err |= __get_user(regs->hi, &ctx->regs[33]); + err |= __get_user(regs->cp0_epc, &ctx->regs[35]); } - if (ctx->flags & 0x08) { + if (flags & 0x08) /* XXX fpu context, blah... */ - printk("Wheee, cannot restore FPU context yet...\n"); - } - current->thread.irix_oldctx = ctx->link; - error = regs->regs[2]; + printk(KERN_ERR "Wheee, cannot restore FPU context yet...\n"); -out: - return error; + err |= __get_user(current->thread.irix_oldctx, &ctx->link); + if (err) + goto segv_and_exit; + + /* + * Don't let your children do this ... + */ + if (current_thread_info()->flags & TIF_SYSCALL_TRACE) + do_syscall_trace(regs, 1); + __asm__ __volatile__( + "move\t$29,%0\n\t" + "j\tsyscall_exit" + :/* no outputs */ + :"r" (®s)); + /* Unreached */ + +segv_and_exit: + force_sigsegv(SIGSEGV, current); } -struct irix_sigstack { unsigned long sp; int status; }; +struct irix_sigstack { + unsigned long sp; + int status; +}; -asmlinkage int irix_sigstack(struct irix_sigstack *new, struct irix_sigstack *old) +asmlinkage int irix_sigstack(struct irix_sigstack __user *new, + struct irix_sigstack __user *old) { - int error = -EFAULT; - #ifdef DEBUG_SIG printk("[%s:%d] irix_sigstack(%p,%p)\n", current->comm, current->pid, new, old); #endif - if(new) { + if (new) { if (!access_ok(VERIFY_READ, new, sizeof(*new))) - goto out; + return -EFAULT; } - if(old) { + if (old) { if (!access_ok(VERIFY_WRITE, old, sizeof(*old))) - goto out; + return -EFAULT; } - error = 0; -out: - return error; + return 0; } struct irix_sigaltstack { unsigned long sp; int size; int status; }; -asmlinkage int irix_sigaltstack(struct irix_sigaltstack *new, - struct irix_sigaltstack *old) +asmlinkage int irix_sigaltstack(struct irix_sigaltstack __user *new, + struct irix_sigaltstack __user *old) { - int error = -EFAULT; - #ifdef DEBUG_SIG printk("[%s:%d] irix_sigaltstack(%p,%p)\n", current->comm, current->pid, new, old); #endif - if (new) { + if (new) if (!access_ok(VERIFY_READ, new, sizeof(*new))) - goto out; - } + return -EFAULT; if (old) { if (!access_ok(VERIFY_WRITE, old, sizeof(*old))) - goto out; + return -EFAULT; } - error = 0; - -out: - error = 0; - return error; + return 0; } struct irix_procset { int cmd, ltype, lid, rtype, rid; }; -asmlinkage int irix_sigsendset(struct irix_procset *pset, int sig) +asmlinkage int irix_sigsendset(struct irix_procset __user *pset, int sig) { if (!access_ok(VERIFY_READ, pset, sizeof(*pset))) return -EFAULT; - #ifdef DEBUG_SIG printk("[%s:%d] irix_sigsendset([%d,%d,%d,%d,%d],%d)\n", current->comm, current->pid, diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/irq-msc01.c linux-2.6.12.6/arch/mips/kernel/irq-msc01.c --- linux-2.6.12.6.orig/arch/mips/kernel/irq-msc01.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/irq-msc01.c 2005-10-02 23:47:36.000000000 +0000 @@ -129,25 +129,23 @@ #define shutdown_msc_irq disable_msc_irq struct hw_interrupt_type msc_levelirq_type = { - "SOC-it-Level", - startup_msc_irq, - shutdown_msc_irq, - enable_msc_irq, - disable_msc_irq, - level_mask_and_ack_msc_irq, - end_msc_irq, - NULL + .typename = "SOC-it-Level", + .startup = startup_msc_irq, + .shutdown = shutdown_msc_irq, + .enable = enable_msc_irq, + .disable = disable_msc_irq, + .ack = level_mask_and_ack_msc_irq, + .end = end_msc_irq, }; struct hw_interrupt_type msc_edgeirq_type = { - "SOC-it-Edge", - startup_msc_irq, - shutdown_msc_irq, - enable_msc_irq, - disable_msc_irq, - edge_mask_and_ack_msc_irq, - end_msc_irq, - NULL + .typename = "SOC-it-Edge", + .startup =startup_msc_irq, + .shutdown = shutdown_msc_irq, + .enable = enable_msc_irq, + .disable = disable_msc_irq, + .ack = edge_mask_and_ack_msc_irq, + .end = end_msc_irq, }; diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/irq-mv6434x.c linux-2.6.12.6/arch/mips/kernel/irq-mv6434x.c --- linux-2.6.12.6.orig/arch/mips/kernel/irq-mv6434x.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/irq-mv6434x.c 2005-10-02 23:47:36.000000000 +0000 @@ -135,14 +135,13 @@ #define shutdown_mv64340_irq disable_mv64340_irq struct hw_interrupt_type mv64340_irq_type = { - "MV-64340", - startup_mv64340_irq, - shutdown_mv64340_irq, - enable_mv64340_irq, - disable_mv64340_irq, - mask_and_ack_mv64340_irq, - end_mv64340_irq, - NULL + .typename = "MV-64340", + .startup = startup_mv64340_irq, + .shutdown = shutdown_mv64340_irq, + .enable = enable_mv64340_irq, + .disable = disable_mv64340_irq, + .ack = mask_and_ack_mv64340_irq, + .end = end_mv64340_irq, }; void __init mv64340_irq_init(unsigned int base) diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/irq-rm7000.c linux-2.6.12.6/arch/mips/kernel/irq-rm7000.c --- linux-2.6.12.6.orig/arch/mips/kernel/irq-rm7000.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/irq-rm7000.c 2005-10-02 23:47:36.000000000 +0000 @@ -72,13 +72,13 @@ } static hw_irq_controller rm7k_irq_controller = { - "RM7000", - rm7k_cpu_irq_startup, - rm7k_cpu_irq_shutdown, - rm7k_cpu_irq_enable, - rm7k_cpu_irq_disable, - rm7k_cpu_irq_ack, - rm7k_cpu_irq_end, + .typename = "RM7000", + .startup = rm7k_cpu_irq_startup, + .shutdown = rm7k_cpu_irq_shutdown, + .enable = rm7k_cpu_irq_enable, + .disable = rm7k_cpu_irq_disable, + .ack = rm7k_cpu_irq_ack, + .end = rm7k_cpu_irq_end, }; void __init rm7k_cpu_irq_init(int base) diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/irq-rm9000.c linux-2.6.12.6/arch/mips/kernel/irq-rm9000.c --- linux-2.6.12.6.orig/arch/mips/kernel/irq-rm9000.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/irq-rm9000.c 2005-10-02 23:47:36.000000000 +0000 @@ -106,23 +106,23 @@ } static hw_irq_controller rm9k_irq_controller = { - "RM9000", - rm9k_cpu_irq_startup, - rm9k_cpu_irq_shutdown, - rm9k_cpu_irq_enable, - rm9k_cpu_irq_disable, - rm9k_cpu_irq_ack, - rm9k_cpu_irq_end, + .typename = "RM9000", + .startup = rm9k_cpu_irq_startup, + .shutdown = rm9k_cpu_irq_shutdown, + .enable = rm9k_cpu_irq_enable, + .disable = rm9k_cpu_irq_disable, + .ack = rm9k_cpu_irq_ack, + .end = rm9k_cpu_irq_end, }; static hw_irq_controller rm9k_perfcounter_irq = { - "RM9000", - rm9k_perfcounter_irq_startup, - rm9k_perfcounter_irq_shutdown, - rm9k_cpu_irq_enable, - rm9k_cpu_irq_disable, - rm9k_cpu_irq_ack, - rm9k_cpu_irq_end, + .typename = "RM9000", + .startup = rm9k_perfcounter_irq_startup, + .shutdown = rm9k_perfcounter_irq_shutdown, + .enable = rm9k_cpu_irq_enable, + .disable = rm9k_cpu_irq_disable, + .ack = rm9k_cpu_irq_ack, + .end = rm9k_cpu_irq_end, }; unsigned int rm9000_perfcount_irq; diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/irq_cpu.c linux-2.6.12.6/arch/mips/kernel/irq_cpu.c --- linux-2.6.12.6.orig/arch/mips/kernel/irq_cpu.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/irq_cpu.c 2005-10-02 23:47:36.000000000 +0000 @@ -3,6 +3,8 @@ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net * * Copyright (C) 2001 Ralf Baechle + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * Author: Maciej W. Rozycki * * This file define the irq handler for MIPS CPU interrupts. * @@ -37,7 +39,6 @@ static inline void unmask_mips_irq(unsigned int irq) { - clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); set_c0_status(0x100 << (irq - mips_cpu_irq_base)); } @@ -92,14 +93,13 @@ } static hw_irq_controller mips_cpu_irq_controller = { - "MIPS", - mips_cpu_irq_startup, - mips_cpu_irq_shutdown, - mips_cpu_irq_enable, - mips_cpu_irq_disable, - mips_cpu_irq_ack, - mips_cpu_irq_end, - NULL /* no affinity stuff for UP */ + .typename = "MIPS", + .startup = mips_cpu_irq_startup, + .shutdown = mips_cpu_irq_shutdown, + .enable = mips_cpu_irq_enable, + .disable = mips_cpu_irq_disable, + .ack = mips_cpu_irq_ack, + .end = mips_cpu_irq_end, }; @@ -107,6 +107,10 @@ { int i; + /* Mask interrupts. */ + clear_c0_status(ST0_IM); + clear_c0_cause(CAUSEF_IP); + for (i = irq_base; i < irq_base + 8; i++) { irq_desc[i].status = IRQ_DISABLED; irq_desc[i].action = NULL; diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/linux32.c linux-2.6.12.6/arch/mips/kernel/linux32.c --- linux-2.6.12.6.orig/arch/mips/kernel/linux32.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/linux32.c 2005-10-02 23:47:36.000000000 +0000 @@ -215,81 +215,35 @@ return(n); } -struct rusage32 { - struct compat_timeval ru_utime; - struct compat_timeval ru_stime; - int ru_maxrss; - int ru_ixrss; - int ru_idrss; - int ru_isrss; - int ru_minflt; - int ru_majflt; - int ru_nswap; - int ru_inblock; - int ru_oublock; - int ru_msgsnd; - int ru_msgrcv; - int ru_nsignals; - int ru_nvcsw; - int ru_nivcsw; -}; +asmlinkage int compat_sys_wait4(compat_pid_t pid, unsigned int * stat_addr, + int options, struct compat_rusage * ru); -static int -put_rusage (struct rusage32 *ru, struct rusage *r) +asmlinkage int +sys32_waitpid(compat_pid_t pid, unsigned int *stat_addr, int options) { - int err; - - if (!access_ok(VERIFY_WRITE, ru, sizeof *ru)) - return -EFAULT; - - err = __put_user (r->ru_utime.tv_sec, &ru->ru_utime.tv_sec); - err |= __put_user (r->ru_utime.tv_usec, &ru->ru_utime.tv_usec); - err |= __put_user (r->ru_stime.tv_sec, &ru->ru_stime.tv_sec); - err |= __put_user (r->ru_stime.tv_usec, &ru->ru_stime.tv_usec); - err |= __put_user (r->ru_maxrss, &ru->ru_maxrss); - err |= __put_user (r->ru_ixrss, &ru->ru_ixrss); - err |= __put_user (r->ru_idrss, &ru->ru_idrss); - err |= __put_user (r->ru_isrss, &ru->ru_isrss); - err |= __put_user (r->ru_minflt, &ru->ru_minflt); - err |= __put_user (r->ru_majflt, &ru->ru_majflt); - err |= __put_user (r->ru_nswap, &ru->ru_nswap); - err |= __put_user (r->ru_inblock, &ru->ru_inblock); - err |= __put_user (r->ru_oublock, &ru->ru_oublock); - err |= __put_user (r->ru_msgsnd, &ru->ru_msgsnd); - err |= __put_user (r->ru_msgrcv, &ru->ru_msgrcv); - err |= __put_user (r->ru_nsignals, &ru->ru_nsignals); - err |= __put_user (r->ru_nvcsw, &ru->ru_nvcsw); - err |= __put_user (r->ru_nivcsw, &ru->ru_nivcsw); - - return err; + return compat_sys_wait4(pid, stat_addr, options, NULL); } -asmlinkage int -sys32_wait4(compat_pid_t pid, unsigned int * stat_addr, int options, - struct rusage32 * ru) +asmlinkage long +sysn32_waitid(int which, compat_pid_t pid, + siginfo_t __user *uinfo, int options, + struct compat_rusage __user *uru) { - if (!ru) - return sys_wait4(pid, stat_addr, options, NULL); - else { - struct rusage r; - int ret; - unsigned int status; - mm_segment_t old_fs = get_fs(); + struct rusage ru; + long ret; + mm_segment_t old_fs = get_fs(); - set_fs(KERNEL_DS); - ret = sys_wait4(pid, stat_addr ? &status : NULL, options, &r); - set_fs(old_fs); - if (put_rusage (ru, &r)) return -EFAULT; - if (stat_addr && put_user (status, stat_addr)) - return -EFAULT; + set_fs (KERNEL_DS); + ret = sys_waitid(which, pid, uinfo, options, + uru ? (struct rusage __user *) &ru : NULL); + set_fs (old_fs); + + if (ret < 0 || uinfo->si_signo == 0) return ret; - } -} -asmlinkage int -sys32_waitpid(compat_pid_t pid, unsigned int *stat_addr, int options) -{ - return sys32_wait4(pid, stat_addr, options, NULL); + if (uru) + ret = put_compat_rusage(&ru, uru); + return ret; } struct sysinfo32 { @@ -1467,3 +1421,80 @@ } return err; } + +struct sigevent32 { + u32 sigev_value; + u32 sigev_signo; + u32 sigev_notify; + u32 payload[(64 / 4) - 3]; +}; + +extern asmlinkage long +sys_timer_create(clockid_t which_clock, + struct sigevent __user *timer_event_spec, + timer_t __user * created_timer_id); + +long +sys32_timer_create(u32 clock, struct sigevent32 __user *se32, timer_t __user *timer_id) +{ + struct sigevent __user *p = NULL; + if (se32) { + struct sigevent se; + p = compat_alloc_user_space(sizeof(struct sigevent)); + memset(&se, 0, sizeof(struct sigevent)); + if (get_user(se.sigev_value.sival_int, &se32->sigev_value) || + __get_user(se.sigev_signo, &se32->sigev_signo) || + __get_user(se.sigev_notify, &se32->sigev_notify) || + __copy_from_user(&se._sigev_un._pad, &se32->payload, + sizeof(se32->payload)) || + copy_to_user(p, &se, sizeof(se))) + return -EFAULT; + } + return sys_timer_create(clock, p, timer_id); +} + +asmlinkage long +sysn32_rt_sigtimedwait(const sigset_t __user *uthese, + siginfo_t __user *uinfo, + const struct compat_timespec __user *uts32, + size_t sigsetsize) +{ + struct timespec __user *uts = NULL; + + if (uts32) { + struct timespec ts; + uts = compat_alloc_user_space(sizeof(struct timespec)); + if (get_user(ts.tv_sec, &uts32->tv_sec) || + get_user(ts.tv_nsec, &uts32->tv_nsec) || + copy_to_user (uts, &ts, sizeof (ts))) + return -EFAULT; + } + return sys_rt_sigtimedwait(uthese, uinfo, uts, sigsetsize); +} + +save_static_function(sys32_clone); +__attribute_used__ noinline static int +_sys32_clone(nabi_no_regargs struct pt_regs regs) +{ + unsigned long clone_flags; + unsigned long newsp; + int __user *parent_tidptr, *child_tidptr; + + clone_flags = regs.regs[4]; + newsp = regs.regs[5]; + if (!newsp) + newsp = regs.regs[29]; + parent_tidptr = (int *) regs.regs[6]; + + /* Use __dummy4 instead of getting it off the stack, so that + syscall() works. */ + child_tidptr = (int __user *) __dummy4; + return do_fork(clone_flags, newsp, ®s, 0, + parent_tidptr, child_tidptr); +} + +extern asmlinkage void sys_set_thread_area(u32 addr); +asmlinkage void sys32_set_thread_area(u32 addr) +{ + sys_set_thread_area(AA(addr)); +} diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/module-elf32.c linux-2.6.12.6/arch/mips/kernel/module-elf32.c --- linux-2.6.12.6.orig/arch/mips/kernel/module-elf32.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/module-elf32.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,250 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Copyright (C) 2001 Rusty Russell. - * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org) - */ - -#undef DEBUG - -#include -#include -#include -#include -#include -#include -#include - -struct mips_hi16 { - struct mips_hi16 *next; - Elf32_Addr *addr; - Elf32_Addr value; -}; - -static struct mips_hi16 *mips_hi16_list; - -void *module_alloc(unsigned long size) -{ - if (size == 0) - return NULL; - return vmalloc(size); -} - - -/* Free memory returned from module_alloc */ -void module_free(struct module *mod, void *module_region) -{ - vfree(module_region); - /* FIXME: If module_region == mod->init_region, trim exception - table entries. */ -} - -int module_frob_arch_sections(Elf_Ehdr *hdr, - Elf_Shdr *sechdrs, - char *secstrings, - struct module *mod) -{ - return 0; -} - -static int apply_r_mips_none(struct module *me, uint32_t *location, - Elf32_Addr v) -{ - return 0; -} - -static int apply_r_mips_32(struct module *me, uint32_t *location, - Elf32_Addr v) -{ - *location += v; - - return 0; -} - -static int apply_r_mips_26(struct module *me, uint32_t *location, - Elf32_Addr v) -{ - if (v % 4) { - printk(KERN_ERR "module %s: dangerous relocation\n", me->name); - return -ENOEXEC; - } - - if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { - printk(KERN_ERR - "module %s: relocation overflow\n", - me->name); - return -ENOEXEC; - } - - *location = (*location & ~0x03ffffff) | - ((*location + (v >> 2)) & 0x03ffffff); - - return 0; -} - -static int apply_r_mips_hi16(struct module *me, uint32_t *location, - Elf32_Addr v) -{ - struct mips_hi16 *n; - - /* - * We cannot relocate this one now because we don't know the value of - * the carry we need to add. Save the information, and let LO16 do the - * actual relocation. - */ - n = kmalloc(sizeof *n, GFP_KERNEL); - if (!n) - return -ENOMEM; - - n->addr = location; - n->value = v; - n->next = mips_hi16_list; - mips_hi16_list = n; - - return 0; -} - -static int apply_r_mips_lo16(struct module *me, uint32_t *location, - Elf32_Addr v) -{ - unsigned long insnlo = *location; - Elf32_Addr val, vallo; - - /* Sign extend the addend we extract from the lo insn. */ - vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; - - if (mips_hi16_list != NULL) { - struct mips_hi16 *l; - - l = mips_hi16_list; - while (l != NULL) { - struct mips_hi16 *next; - unsigned long insn; - - /* - * The value for the HI16 had best be the same. - */ - if (v != l->value) - goto out_danger; - - /* - * Do the HI16 relocation. Note that we actually don't - * need to know anything about the LO16 itself, except - * where to find the low 16 bits of the addend needed - * by the LO16. - */ - insn = *l->addr; - val = ((insn & 0xffff) << 16) + vallo; - val += v; - - /* - * Account for the sign extension that will happen in - * the low bits. - */ - val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff; - - insn = (insn & ~0xffff) | val; - *l->addr = insn; - - next = l->next; - kfree(l); - l = next; - } - - mips_hi16_list = NULL; - } - - /* - * Ok, we're done with the HI16 relocs. Now deal with the LO16. - */ - val = v + vallo; - insnlo = (insnlo & ~0xffff) | (val & 0xffff); - *location = insnlo; - - return 0; - -out_danger: - printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name); - - return -ENOEXEC; -} - -static int (*reloc_handlers[]) (struct module *me, uint32_t *location, - Elf32_Addr v) = { - [R_MIPS_NONE] = apply_r_mips_none, - [R_MIPS_32] = apply_r_mips_32, - [R_MIPS_26] = apply_r_mips_26, - [R_MIPS_HI16] = apply_r_mips_hi16, - [R_MIPS_LO16] = apply_r_mips_lo16 -}; - -int apply_relocate(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - Elf32_Rel *rel = (void *) sechdrs[relsec].sh_addr; - Elf32_Sym *sym; - uint32_t *location; - unsigned int i; - Elf32_Addr v; - int res; - - pr_debug("Applying relocate section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - Elf32_Word r_info = rel[i].r_info; - - /* This is where to make the change */ - location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - /* This is the symbol it is referring to */ - sym = (Elf32_Sym *)sechdrs[symindex].sh_addr - + ELF32_R_SYM(r_info); - if (!sym->st_value) { - printk(KERN_WARNING "%s: Unknown symbol %s\n", - me->name, strtab + sym->st_name); - return -ENOENT; - } - - v = sym->st_value; - - res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v); - if (res) - return res; - } - - return 0; -} - -int apply_relocate_add(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - /* - * Current binutils always generate .rela relocations. Keep smiling - * if it's empty, abort otherwise. - */ - if (!sechdrs[relsec].sh_size) - return 0; - - printk(KERN_ERR "module %s: ADD RELOCATION unsupported\n", - me->name); - return -ENOEXEC; -} diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/module-elf64.c linux-2.6.12.6/arch/mips/kernel/module-elf64.c --- linux-2.6.12.6.orig/arch/mips/kernel/module-elf64.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/module-elf64.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,274 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Copyright (C) 2001 Rusty Russell. - * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org) - */ - -#undef DEBUG - -#include -#include -#include -#include -#include -#include -#include - -struct mips_hi16 { - struct mips_hi16 *next; - Elf32_Addr *addr; - Elf64_Addr value; -}; - -static struct mips_hi16 *mips_hi16_list; - -void *module_alloc(unsigned long size) -{ - if (size == 0) - return NULL; - return vmalloc(size); -} - - -/* Free memory returned from module_alloc */ -void module_free(struct module *mod, void *module_region) -{ - vfree(module_region); - /* FIXME: If module_region == mod->init_region, trim exception - table entries. */ -} - -int module_frob_arch_sections(Elf_Ehdr *hdr, - Elf_Shdr *sechdrs, - char *secstrings, - struct module *mod) -{ - return 0; -} - -int apply_relocate(Elf64_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - /* - * We don't want to deal with REL relocations - RELA is so much saner. - */ - if (!sechdrs[relsec].sh_size) - return 0; - - printk(KERN_ERR "module %s: REL relocation unsupported\n", - me->name); - return -ENOEXEC; -} - -static int apply_r_mips_none(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - return 0; -} - -static int apply_r_mips_32(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - *location = v; - - return 0; -} - -static int apply_r_mips_26(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - if (v % 4) { - printk(KERN_ERR "module %s: dangerous relocation\n", me->name); - return -ENOEXEC; - } - - if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { - printk(KERN_ERR - "module %s: relocation overflow\n", - me->name); - return -ENOEXEC; - } - - *location = (*location & ~0x03ffffff) | ((v >> 2) & 0x03ffffff); - - return 0; -} - -static int apply_r_mips_hi16(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - struct mips_hi16 *n; - - /* - * We cannot relocate this one now because we don't know the value of - * the carry we need to add. Save the information, and let LO16 do the - * actual relocation. - */ - n = kmalloc(sizeof *n, GFP_KERNEL); - if (!n) - return -ENOMEM; - - n->addr = location; - n->value = v; - n->next = mips_hi16_list; - mips_hi16_list = n; - - return 0; -} - -static int apply_r_mips_lo16(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - unsigned long insnlo = *location; - Elf32_Addr val, vallo; - - /* Sign extend the addend we extract from the lo insn. */ - vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; - - if (mips_hi16_list != NULL) { - struct mips_hi16 *l; - - l = mips_hi16_list; - while (l != NULL) { - struct mips_hi16 *next; - unsigned long insn; - - /* - * The value for the HI16 had best be the same. - */ - if (v != l->value) - goto out_danger; - - /* - * Do the HI16 relocation. Note that we actually don't - * need to know anything about the LO16 itself, except - * where to find the low 16 bits of the addend needed - * by the LO16. - */ - insn = *l->addr; - val = ((insn & 0xffff) << 16) + vallo; - val += v; - - /* - * Account for the sign extension that will happen in - * the low bits. - */ - val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff; - - insn = (insn & ~0xffff) | val; - *l->addr = insn; - - next = l->next; - kfree(l); - l = next; - } - - mips_hi16_list = NULL; - } - - /* - * Ok, we're done with the HI16 relocs. Now deal with the LO16. - */ - insnlo = (insnlo & ~0xffff) | (v & 0xffff); - *location = insnlo; - - return 0; - -out_danger: - printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name); - - return -ENOEXEC; -} - -static int apply_r_mips_64(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - *(uint64_t *) location = v; - - return 0; -} - - -static int apply_r_mips_higher(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - *location = (*location & 0xffff0000) | - ((((long long) v + 0x80008000LL) >> 32) & 0xffff); - - return 0; -} - -static int apply_r_mips_highest(struct module *me, uint32_t *location, - Elf64_Addr v) -{ - *location = (*location & 0xffff0000) | - ((((long long) v + 0x800080008000LL) >> 48) & 0xffff); - - return 0; -} - -static int (*reloc_handlers[]) (struct module *me, uint32_t *location, - Elf64_Addr v) = { - [R_MIPS_NONE] = apply_r_mips_none, - [R_MIPS_32] = apply_r_mips_32, - [R_MIPS_26] = apply_r_mips_26, - [R_MIPS_HI16] = apply_r_mips_hi16, - [R_MIPS_LO16] = apply_r_mips_lo16, - [R_MIPS_64] = apply_r_mips_64, - [R_MIPS_HIGHER] = apply_r_mips_higher, - [R_MIPS_HIGHEST] = apply_r_mips_highest -}; - -int apply_relocate_add(Elf64_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - Elf64_Mips_Rela *rel = (void *) sechdrs[relsec].sh_addr; - Elf64_Sym *sym; - uint32_t *location; - unsigned int i; - Elf64_Addr v; - int res; - - pr_debug("Applying relocate section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - /* This is where to make the change */ - location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - /* This is the symbol it is referring to */ - sym = (Elf64_Sym *)sechdrs[symindex].sh_addr + rel[i].r_sym; - if (!sym->st_value) { - printk(KERN_WARNING "%s: Unknown symbol %s\n", - me->name, strtab + sym->st_name); - return -ENOENT; - } - - v = sym->st_value; - - res = reloc_handlers[rel[i].r_type](me, location, v); - if (res) - return res; - } - - return 0; -} diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/module.c linux-2.6.12.6/arch/mips/kernel/module.c --- linux-2.6.12.6.orig/arch/mips/kernel/module.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/module.c 2005-10-02 23:47:36.000000000 +0000 @@ -1,9 +1,345 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2001 Rusty Russell. + * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2005 Thiemo Seufer + */ + +#undef DEBUG + +#include +#include +#include +#include +#include +#include +#include #include #include +struct mips_hi16 { + struct mips_hi16 *next; + Elf_Addr *addr; + Elf_Addr value; +}; + +static struct mips_hi16 *mips_hi16_list; + static LIST_HEAD(dbe_list); static DEFINE_SPINLOCK(dbe_lock); +void *module_alloc(unsigned long size) +{ + if (size == 0) + return NULL; + return vmalloc(size); +} + +/* Free memory returned from module_alloc */ +void module_free(struct module *mod, void *module_region) +{ + vfree(module_region); + /* FIXME: If module_region == mod->init_region, trim exception + table entries. */ +} + +int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, + char *secstrings, struct module *mod) +{ + return 0; +} + +static int apply_r_mips_none(struct module *me, u32 *location, Elf_Addr v) +{ + return 0; +} + +static int apply_r_mips_32_rel(struct module *me, u32 *location, Elf_Addr v) +{ + *location += v; + + return 0; +} + +static int apply_r_mips_32_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *location = v; + + return 0; +} + +static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v) +{ + if (v % 4) { + printk(KERN_ERR "module %s: dangerous relocation\n", me->name); + return -ENOEXEC; + } + + if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { + printk(KERN_ERR + "module %s: relocation overflow\n", + me->name); + return -ENOEXEC; + } + + *location = (*location & ~0x03ffffff) | + ((*location + (v >> 2)) & 0x03ffffff); + + return 0; +} + +static int apply_r_mips_26_rela(struct module *me, u32 *location, Elf_Addr v) +{ + if (v % 4) { + printk(KERN_ERR "module %s: dangerous relocation\n", me->name); + return -ENOEXEC; + } + + if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { + printk(KERN_ERR + "module %s: relocation overflow\n", + me->name); + return -ENOEXEC; + } + + *location = (*location & ~0x03ffffff) | ((v >> 2) & 0x03ffffff); + + return 0; +} + +static int apply_r_mips_hi16_rel(struct module *me, u32 *location, Elf_Addr v) +{ + struct mips_hi16 *n; + + /* + * We cannot relocate this one now because we don't know the value of + * the carry we need to add. Save the information, and let LO16 do the + * actual relocation. + */ + n = kmalloc(sizeof *n, GFP_KERNEL); + if (!n) + return -ENOMEM; + + n->addr = (Elf_Addr *)location; + n->value = v; + n->next = mips_hi16_list; + mips_hi16_list = n; + + return 0; +} + +static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *location = (*location & 0xffff0000) | + ((((long long) v + 0x8000LL) >> 16) & 0xffff); + + return 0; +} + +static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v) +{ + unsigned long insnlo = *location; + Elf_Addr val, vallo; + + /* Sign extend the addend we extract from the lo insn. */ + vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; + + if (mips_hi16_list != NULL) { + struct mips_hi16 *l; + + l = mips_hi16_list; + while (l != NULL) { + struct mips_hi16 *next; + unsigned long insn; + + /* + * The value for the HI16 had best be the same. + */ + if (v != l->value) + goto out_danger; + + /* + * Do the HI16 relocation. Note that we actually don't + * need to know anything about the LO16 itself, except + * where to find the low 16 bits of the addend needed + * by the LO16. + */ + insn = *l->addr; + val = ((insn & 0xffff) << 16) + vallo; + val += v; + + /* + * Account for the sign extension that will happen in + * the low bits. + */ + val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff; + + insn = (insn & ~0xffff) | val; + *l->addr = insn; + + next = l->next; + kfree(l); + l = next; + } + + mips_hi16_list = NULL; + } + + /* + * Ok, we're done with the HI16 relocs. Now deal with the LO16. + */ + val = v + vallo; + insnlo = (insnlo & ~0xffff) | (val & 0xffff); + *location = insnlo; + + return 0; + +out_danger: + printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name); + + return -ENOEXEC; +} + +static int apply_r_mips_lo16_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *location = (*location & 0xffff0000) | (v & 0xffff); + + return 0; +} + +static int apply_r_mips_64_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(Elf_Addr *)location = v; + + return 0; +} + +static int apply_r_mips_higher_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *location = (*location & 0xffff0000) | + ((((long long) v + 0x80008000LL) >> 32) & 0xffff); + + return 0; +} + +static int apply_r_mips_highest_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *location = (*location & 0xffff0000) | + ((((long long) v + 0x800080008000LL) >> 48) & 0xffff); + + return 0; +} + +static int (*reloc_handlers_rel[]) (struct module *me, u32 *location, + Elf_Addr v) = { + [R_MIPS_NONE] = apply_r_mips_none, + [R_MIPS_32] = apply_r_mips_32_rel, + [R_MIPS_26] = apply_r_mips_26_rel, + [R_MIPS_HI16] = apply_r_mips_hi16_rel, + [R_MIPS_LO16] = apply_r_mips_lo16_rel +}; + +static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, + Elf_Addr v) = { + [R_MIPS_NONE] = apply_r_mips_none, + [R_MIPS_32] = apply_r_mips_32_rela, + [R_MIPS_26] = apply_r_mips_26_rela, + [R_MIPS_HI16] = apply_r_mips_hi16_rela, + [R_MIPS_LO16] = apply_r_mips_lo16_rela, + [R_MIPS_64] = apply_r_mips_64_rela, + [R_MIPS_HIGHER] = apply_r_mips_higher_rela, + [R_MIPS_HIGHEST] = apply_r_mips_highest_rela +}; + +int apply_relocate(Elf_Shdr *sechdrs, const char *strtab, + unsigned int symindex, unsigned int relsec, + struct module *me) +{ + Elf_Mips_Rel *rel = (void *) sechdrs[relsec].sh_addr; + Elf_Sym *sym; + u32 *location; + unsigned int i; + Elf_Addr v; + int res; + + pr_debug("Applying relocate section %u to %u\n", relsec, + sechdrs[relsec].sh_info); + + for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + /* This is where to make the change */ + location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr + + rel[i].r_offset; + /* This is the symbol it is referring to */ + sym = (Elf_Sym *)sechdrs[symindex].sh_addr + + ELF_MIPS_R_SYM(rel[i]); + if (!sym->st_value) { + printk(KERN_WARNING "%s: Unknown symbol %s\n", + me->name, strtab + sym->st_name); + return -ENOENT; + } + + v = sym->st_value; + + res = reloc_handlers_rel[ELF_MIPS_R_TYPE(rel[i])](me, location, v); + if (res) + return res; + } + + return 0; +} + +int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, + unsigned int symindex, unsigned int relsec, + struct module *me) +{ + Elf_Mips_Rela *rel = (void *) sechdrs[relsec].sh_addr; + Elf_Sym *sym; + u32 *location; + unsigned int i; + Elf_Addr v; + int res; + + pr_debug("Applying relocate section %u to %u\n", relsec, + sechdrs[relsec].sh_info); + + for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + /* This is where to make the change */ + location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr + + rel[i].r_offset; + /* This is the symbol it is referring to */ + sym = (Elf_Sym *)sechdrs[symindex].sh_addr + + ELF_MIPS_R_SYM(rel[i]); + if (!sym->st_value) { + printk(KERN_WARNING "%s: Unknown symbol %s\n", + me->name, strtab + sym->st_name); + return -ENOENT; + } + + v = sym->st_value + rel[i].r_addend; + + res = reloc_handlers_rela[ELF_MIPS_R_TYPE(rel[i])](me, location, v); + if (res) + return res; + } + + return 0; +} + /* Given an address, look for it in the module exception tables. */ const struct exception_table_entry *search_module_dbetables(unsigned long addr) { diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/offset.c linux-2.6.12.6/arch/mips/kernel/offset.c --- linux-2.6.12.6.orig/arch/mips/kernel/offset.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/offset.c 2005-10-02 23:47:36.000000000 +0000 @@ -95,6 +95,7 @@ offset("#define TI_PRE_COUNT ", struct thread_info, preempt_count); offset("#define TI_ADDR_LIMIT ", struct thread_info, addr_limit); offset("#define TI_RESTART_BLOCK ", struct thread_info, restart_block); + offset("#define TI_TP_VALUE ", struct thread_info, tp_value); constant("#define _THREAD_SIZE_ORDER ", THREAD_SIZE_ORDER); constant("#define _THREAD_SIZE ", THREAD_SIZE); constant("#define _THREAD_MASK ", THREAD_MASK); @@ -240,6 +241,7 @@ linefeed; } +#ifdef CONFIG_MIPS32 void output_sc_defines(void) { text("/* Linux sigcontext offsets. */"); @@ -251,10 +253,29 @@ offset("#define SC_STATUS ", struct sigcontext, sc_status); offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr); offset("#define SC_FPC_EIR ", struct sigcontext, sc_fpc_eir); - offset("#define SC_CAUSE ", struct sigcontext, sc_cause); - offset("#define SC_BADVADDR ", struct sigcontext, sc_badvaddr); + offset("#define SC_HI1 ", struct sigcontext, sc_hi1); + offset("#define SC_LO1 ", struct sigcontext, sc_lo1); + offset("#define SC_HI2 ", struct sigcontext, sc_hi2); + offset("#define SC_LO2 ", struct sigcontext, sc_lo2); + offset("#define SC_HI3 ", struct sigcontext, sc_hi3); + offset("#define SC_LO3 ", struct sigcontext, sc_lo3); linefeed; } +#endif + +#ifdef CONFIG_MIPS64 +void output_sc_defines(void) +{ + text("/* Linux sigcontext offsets. */"); + offset("#define SC_REGS ", struct sigcontext, sc_regs); + offset("#define SC_FPREGS ", struct sigcontext, sc_fpregs); + offset("#define SC_MDHI ", struct sigcontext, sc_hi); + offset("#define SC_MDLO ", struct sigcontext, sc_lo); + offset("#define SC_PC ", struct sigcontext, sc_pc); + offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr); + linefeed; +} +#endif #ifdef CONFIG_MIPS32_COMPAT void output_sc32_defines(void) diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/proc.c linux-2.6.12.6/arch/mips/kernel/proc.c --- linux-2.6.12.6.orig/arch/mips/kernel/proc.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/proc.c 2005-10-02 23:47:36.000000000 +0000 @@ -2,7 +2,8 @@ * linux/arch/mips/kernel/proc.c * * Copyright (C) 1995, 1996, 2001 Ralf Baechle - * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 2001, 2004 MIPS Technologies, Inc. + * Copyright (C) 2004 Maciej W. Rozycki */ #include #include @@ -19,63 +20,66 @@ unsigned int vced_count, vcei_count; static const char *cpu_name[] = { - [CPU_UNKNOWN] "unknown", - [CPU_R2000] "R2000", - [CPU_R3000] "R3000", - [CPU_R3000A] "R3000A", - [CPU_R3041] "R3041", - [CPU_R3051] "R3051", - [CPU_R3052] "R3052", - [CPU_R3081] "R3081", - [CPU_R3081E] "R3081E", - [CPU_R4000PC] "R4000PC", - [CPU_R4000SC] "R4000SC", - [CPU_R4000MC] "R4000MC", - [CPU_R4200] "R4200", - [CPU_R4400PC] "R4400PC", - [CPU_R4400SC] "R4400SC", - [CPU_R4400MC] "R4400MC", - [CPU_R4600] "R4600", - [CPU_R6000] "R6000", - [CPU_R6000A] "R6000A", - [CPU_R8000] "R8000", - [CPU_R10000] "R10000", - [CPU_R12000] "R12000", - [CPU_R4300] "R4300", - [CPU_R4650] "R4650", - [CPU_R4700] "R4700", - [CPU_R5000] "R5000", - [CPU_R5000A] "R5000A", - [CPU_R4640] "R4640", - [CPU_NEVADA] "Nevada", - [CPU_RM7000] "RM7000", - [CPU_RM9000] "RM9000", - [CPU_R5432] "R5432", - [CPU_4KC] "MIPS 4Kc", - [CPU_5KC] "MIPS 5Kc", - [CPU_R4310] "R4310", - [CPU_SB1] "SiByte SB1", - [CPU_TX3912] "TX3912", - [CPU_TX3922] "TX3922", - [CPU_TX3927] "TX3927", - [CPU_AU1000] "Au1000", - [CPU_AU1500] "Au1500", - [CPU_4KEC] "MIPS 4KEc", - [CPU_4KSC] "MIPS 4KSc", - [CPU_VR41XX] "NEC Vr41xx", - [CPU_R5500] "R5500", - [CPU_TX49XX] "TX49xx", - [CPU_20KC] "MIPS 20Kc", - [CPU_24K] "MIPS 24K", - [CPU_25KF] "MIPS 25Kf", - [CPU_VR4111] "NEC VR4111", - [CPU_VR4121] "NEC VR4121", - [CPU_VR4122] "NEC VR4122", - [CPU_VR4131] "NEC VR4131", - [CPU_VR4133] "NEC VR4133", - [CPU_VR4181] "NEC VR4181", - [CPU_VR4181A] "NEC VR4181A", - [CPU_SR71000] "Sandcraft SR71000" + [CPU_UNKNOWN] = "unknown", + [CPU_R2000] = "R2000", + [CPU_R3000] = "R3000", + [CPU_R3000A] = "R3000A", + [CPU_R3041] = "R3041", + [CPU_R3051] = "R3051", + [CPU_R3052] = "R3052", + [CPU_R3081] = "R3081", + [CPU_R3081E] = "R3081E", + [CPU_R4000PC] = "R4000PC", + [CPU_R4000SC] = "R4000SC", + [CPU_R4000MC] = "R4000MC", + [CPU_R4200] = "R4200", + [CPU_R4400PC] = "R4400PC", + [CPU_R4400SC] = "R4400SC", + [CPU_R4400MC] = "R4400MC", + [CPU_R4600] = "R4600", + [CPU_R6000] = "R6000", + [CPU_R6000A] = "R6000A", + [CPU_R8000] = "R8000", + [CPU_R10000] = "R10000", + [CPU_R12000] = "R12000", + [CPU_R4300] = "R4300", + [CPU_R4650] = "R4650", + [CPU_R4700] = "R4700", + [CPU_R5000] = "R5000", + [CPU_R5000A] = "R5000A", + [CPU_R4640] = "R4640", + [CPU_NEVADA] = "Nevada", + [CPU_RM7000] = "RM7000", + [CPU_RM9000] = "RM9000", + [CPU_R5432] = "R5432", + [CPU_4KC] = "MIPS 4Kc", + [CPU_5KC] = "MIPS 5Kc", + [CPU_R4310] = "R4310", + [CPU_SB1] = "SiByte SB1", + [CPU_TX3912] = "TX3912", + [CPU_TX3922] = "TX3922", + [CPU_TX3927] = "TX3927", + [CPU_AU1000] = "Au1000", + [CPU_AU1500] = "Au1500", + [CPU_AU1100] = "Au1100", + [CPU_AU1550] = "Au1550", + [CPU_AU1200] = "Au1200", + [CPU_4KEC] = "MIPS 4KEc", + [CPU_4KSC] = "MIPS 4KSc", + [CPU_VR41XX] = "NEC Vr41xx", + [CPU_R5500] = "R5500", + [CPU_TX49XX] = "TX49xx", + [CPU_20KC] = "MIPS 20Kc", + [CPU_24K] = "MIPS 24K", + [CPU_25KF] = "MIPS 25Kf", + [CPU_VR4111] = "NEC VR4111", + [CPU_VR4121] = "NEC VR4121", + [CPU_VR4122] = "NEC VR4122", + [CPU_VR4131] = "NEC VR4131", + [CPU_VR4133] = "NEC VR4133", + [CPU_VR4181] = "NEC VR4181", + [CPU_VR4181A] = "NEC VR4181A", + [CPU_SR71000] = "Sandcraft SR71000" }; @@ -105,8 +109,13 @@ (version >> 4) & 0x0f, version & 0x0f, (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", - loops_per_jiffy / (500000/HZ), - (loops_per_jiffy / (5000/HZ)) % 100); + cpu_data[n].udelay_val / (500000/HZ), + (cpu_data[n].udelay_val / (5000/HZ)) % 100); +#ifdef __MIPSEB__ + seq_printf(m, "byteorder\t\t: big endian\n"); +#else + seq_printf(m, "byteorder\t\t: little endian\n"); +#endif seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); seq_printf(m, "microsecond timers\t: %s\n", cpu_has_counter ? "yes" : "no"); @@ -115,6 +124,11 @@ cpu_has_divec ? "yes" : "no"); seq_printf(m, "hardware watchpoint\t: %s\n", cpu_has_watch ? "yes" : "no"); + seq_printf(m, "ASEs implemented\t:%s%s%s%s\n", + cpu_has_mips16 ? " mips16" : "", + cpu_has_mdmx ? " mdmx" : "", + cpu_has_mips3d ? " mips3d" : "", + cpu_has_smartmips ? " smartmips" : ""); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", cpu_has_vce ? "%u" : "not available"); diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/process.c linux-2.6.12.6/arch/mips/kernel/process.c --- linux-2.6.12.6.orig/arch/mips/kernel/process.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/process.c 2005-10-02 23:47:36.000000000 +0000 @@ -25,8 +25,10 @@ #include #include +#include #include #include +#include #include #include #include @@ -39,14 +41,6 @@ #include /* - * We use this if we don't have any better idle routine.. - * (This to kill: kernel/platform.c. - */ -void default_idle (void) -{ -} - -/* * The idle thread. There's no useful work to be done, so just try to conserve * power and have a low exit latency (ie sit in a loop waiting for somebody to * say that they'd like to reschedule) @@ -62,6 +56,54 @@ } } +extern int do_signal(sigset_t *oldset, struct pt_regs *regs); +extern int do_signal32(sigset_t *oldset, struct pt_regs *regs); + +/* + * Native o32 and N64 ABI without DSP ASE + */ +extern void setup_frame(struct k_sigaction * ka, struct pt_regs *regs, + int signr, sigset_t *set); +extern void setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, + int signr, sigset_t *set, siginfo_t *info); + +struct mips_abi mips_abi = { + .do_signal = do_signal, +#ifdef CONFIG_TRAD_SIGNALS + .setup_frame = setup_frame, +#endif + .setup_rt_frame = setup_rt_frame +}; + +#ifdef CONFIG_MIPS32_O32 +/* + * o32 compatibility on 64-bit kernels, without DSP ASE + */ +extern void setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs, + int signr, sigset_t *set); +extern void setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs, + int signr, sigset_t *set, siginfo_t *info); + +struct mips_abi mips_abi_32 = { + .do_signal = do_signal32, + .setup_frame = setup_frame_32, + .setup_rt_frame = setup_rt_frame_32 +}; +#endif /* CONFIG_MIPS32_O32 */ + +#ifdef CONFIG_MIPS32_N32 +/* + * N32 on 64-bit kernels, without DSP ASE + */ +extern void setup_rt_frame_n32(struct k_sigaction * ka, struct pt_regs *regs, + int signr, sigset_t *set, siginfo_t *info); + +struct mips_abi mips_abi_n32 = { + .do_signal = do_signal, + .setup_rt_frame = setup_rt_frame_n32 +}; +#endif /* CONFIG_MIPS32_N32 */ + asmlinkage void ret_from_fork(void); void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) @@ -78,6 +120,8 @@ regs->cp0_status = status; clear_used_math(); lose_fpu(); + if (cpu_has_dsp) + __init_dsp(); regs->cp0_epc = pc; regs->regs[29] = sp; current_thread_info()->addr_limit = USER_DS; @@ -97,14 +141,17 @@ struct thread_info *ti = p->thread_info; struct pt_regs *childregs; long childksp; + p->set_child_tid = p->clear_child_tid = NULL; childksp = (unsigned long)ti + THREAD_SIZE - 32; preempt_disable(); - if (is_fpu_owner()) { + if (is_fpu_owner()) save_fp(p); - } + + if (cpu_has_dsp) + save_dsp(p); preempt_enable(); @@ -142,6 +189,9 @@ childregs->cp0_status &= ~(ST0_CU2|ST0_CU1); clear_tsk_thread_flag(p, TIF_USEDFPU); + if (clone_flags & CLONE_SETTLS) + ti->tp_value = regs->regs[7]; + return 0; } @@ -175,6 +225,14 @@ #endif } +int dump_task_regs (struct task_struct *tsk, elf_gregset_t *regs) +{ + struct thread_info *ti = tsk->thread_info; + long ksp = (unsigned long)ti + THREAD_SIZE - 32; + dump_regs(&(*regs)[0], (struct pt_regs *) ksp - 1); + return 1; +} + int dump_task_fpu (struct task_struct *t, elf_fpregset_t *fpr) { memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu)); @@ -211,22 +269,48 @@ return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); } -struct mips_frame_info { +static struct mips_frame_info { + void *func; + int omit_fp; /* compiled without fno-omit-frame-pointer */ int frame_offset; int pc_offset; +} schedule_frame, mfinfo[] = { + { schedule, 0 }, /* must be first */ + /* arch/mips/kernel/semaphore.c */ + { __down, 1 }, + { __down_interruptible, 1 }, + /* kernel/sched.c */ +#ifdef CONFIG_PREEMPT + { preempt_schedule, 0 }, +#endif + { wait_for_completion, 0 }, + { interruptible_sleep_on, 0 }, + { interruptible_sleep_on_timeout, 0 }, + { sleep_on, 0 }, + { sleep_on_timeout, 0 }, + { yield, 0 }, + { io_schedule, 0 }, + { io_schedule_timeout, 0 }, +#if defined(CONFIG_SMP) && defined(CONFIG_PREEMPT) + { __preempt_spin_lock, 0 }, + { __preempt_write_lock, 0 }, +#endif + /* kernel/timer.c */ + { schedule_timeout, 1 }, +/* { nanosleep_restart, 1 }, */ + /* lib/rwsem-spinlock.c */ + { __down_read, 1 }, + { __down_write, 1 }, }; -static struct mips_frame_info schedule_frame; -static struct mips_frame_info schedule_timeout_frame; -static struct mips_frame_info sleep_on_frame; -static struct mips_frame_info sleep_on_timeout_frame; -static struct mips_frame_info wait_for_completion_frame; + static int mips_frame_info_initialized; -static int __init get_frame_info(struct mips_frame_info *info, void *func) +static int __init get_frame_info(struct mips_frame_info *info) { int i; + void *func = info->func; union mips_instruction *ip = (union mips_instruction *)func; info->pc_offset = -1; - info->frame_offset = -1; + info->frame_offset = info->omit_fp ? 0 : -1; for (i = 0; i < 128; i++, ip++) { /* if jal, jalr, jr, stop. */ if (ip->j_format.opcode == jal_op || @@ -247,14 +331,16 @@ /* sw / sd $ra, offset($sp) */ if (ip->i_format.rt == 31) { if (info->pc_offset != -1) - break; + continue; info->pc_offset = ip->i_format.simmediate / sizeof(long); } /* sw / sd $s8, offset($sp) */ if (ip->i_format.rt == 30) { +//#if 0 /* gcc 3.4 does aggressive optimization... */ if (info->frame_offset != -1) - break; + continue; +//#endif info->frame_offset = ip->i_format.simmediate / sizeof(long); } @@ -272,13 +358,25 @@ static int __init frame_info_init(void) { - mips_frame_info_initialized = - !get_frame_info(&schedule_frame, schedule) && - !get_frame_info(&schedule_timeout_frame, schedule_timeout) && - !get_frame_info(&sleep_on_frame, sleep_on) && - !get_frame_info(&sleep_on_timeout_frame, sleep_on_timeout) && - !get_frame_info(&wait_for_completion_frame, wait_for_completion); - + int i, found; + for (i = 0; i < ARRAY_SIZE(mfinfo); i++) + if (get_frame_info(&mfinfo[i])) + return -1; + schedule_frame = mfinfo[0]; + /* bubble sort */ + do { + struct mips_frame_info tmp; + found = 0; + for (i = 1; i < ARRAY_SIZE(mfinfo); i++) { + if (mfinfo[i-1].func > mfinfo[i].func) { + tmp = mfinfo[i]; + mfinfo[i] = mfinfo[i-1]; + mfinfo[i-1] = tmp; + found = 1; + } + } + } while (found); + mips_frame_info_initialized = 1; return 0; } @@ -311,53 +409,27 @@ if (!mips_frame_info_initialized) return 0; pc = thread_saved_pc(p); + if (!in_sched_functions(pc)) goto out; - if (pc >= (unsigned long) sleep_on_timeout) - goto schedule_timeout_caller; - if (pc >= (unsigned long) sleep_on) - goto schedule_caller; - if (pc >= (unsigned long) interruptible_sleep_on_timeout) - goto schedule_timeout_caller; - if (pc >= (unsigned long)interruptible_sleep_on) - goto schedule_caller; - if (pc >= (unsigned long)wait_for_completion) - goto schedule_caller; - goto schedule_timeout_caller; - -schedule_caller: - frame = ((unsigned long *)p->thread.reg30)[schedule_frame.frame_offset]; - if (pc >= (unsigned long) sleep_on) - pc = ((unsigned long *)frame)[sleep_on_frame.pc_offset]; - else - pc = ((unsigned long *)frame)[wait_for_completion_frame.pc_offset]; - goto out; - -schedule_timeout_caller: - /* - * The schedule_timeout frame - */ frame = ((unsigned long *)p->thread.reg30)[schedule_frame.frame_offset]; + do { + int i; + for (i = ARRAY_SIZE(mfinfo) - 1; i >= 0; i--) { + if (pc >= (unsigned long) mfinfo[i].func) + break; + } + if (i < 0) + break; - /* - * frame now points to sleep_on_timeout's frame - */ - pc = ((unsigned long *)frame)[schedule_timeout_frame.pc_offset]; - - if (in_sched_functions(pc)) { - /* schedule_timeout called by [interruptible_]sleep_on_timeout */ - frame = ((unsigned long *)frame)[schedule_timeout_frame.frame_offset]; - pc = ((unsigned long *)frame)[sleep_on_timeout_frame.pc_offset]; - } + if (mfinfo[i].omit_fp) + break; + pc = ((unsigned long *)frame)[mfinfo[i].pc_offset]; + frame = ((unsigned long *)frame)[mfinfo[i].frame_offset]; + } while (in_sched_functions(pc)); out: - -#ifdef CONFIG_MIPS64 - if (current->thread.mflags & MF_32BIT_REGS) /* Kludge for 32-bit ps */ - pc &= 0xffffffffUL; -#endif - return pc; } diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/ptrace.c linux-2.6.12.6/arch/mips/kernel/ptrace.c --- linux-2.6.12.6.orig/arch/mips/kernel/ptrace.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/ptrace.c 2005-10-02 23:47:36.000000000 +0000 @@ -21,14 +21,16 @@ #include #include #include -#include #include #include #include #include -#include +#include +#include +#include #include +#include #include #include #include @@ -103,7 +105,7 @@ ret = -EIO; if (copied != sizeof(tmp)) break; - ret = put_user(tmp,(unsigned long *) data); + ret = put_user(tmp,(unsigned long __user *) data); break; } @@ -175,12 +177,36 @@ write_c0_status(flags); break; } + case DSP_BASE ... DSP_BASE + 5: { + dspreg_t *dregs; + + if (!cpu_has_dsp) { + tmp = 0; + ret = -EIO; + goto out_tsk; + } + if (child->thread.dsp.used_dsp) { + dregs = __get_dsp_regs(child); + tmp = (unsigned long) (dregs[addr - DSP_BASE]); + } else { + tmp = -1; /* DSP registers yet used */ + } + break; + } + case DSP_CONTROL: + if (!cpu_has_dsp) { + tmp = 0; + ret = -EIO; + goto out_tsk; + } + tmp = child->thread.dsp.dspcontrol; + break; default: tmp = 0; ret = -EIO; goto out_tsk; } - ret = put_user(tmp, (unsigned long *) data); + ret = put_user(tmp, (unsigned long __user *) data); break; } @@ -247,6 +273,25 @@ else child->thread.fpu.soft.fcr31 = data; break; + case DSP_BASE ... DSP_BASE + 5: { + dspreg_t *dregs; + + if (!cpu_has_dsp) { + ret = -EIO; + break; + } + + dregs = __get_dsp_regs(child); + dregs[addr - DSP_BASE] = data; + break; + } + case DSP_CONTROL: + if (!cpu_has_dsp) { + ret = -EIO; + break; + } + child->thread.dsp.dspcontrol = data; + break; default: /* The rest are not allowed. */ ret = -EIO; @@ -289,6 +334,11 @@ ret = ptrace_detach(child, data); break; + case PTRACE_GET_THREAD_AREA: + ret = put_user(child->thread_info->tp_value, + (unsigned long __user *) data); + break; + default: ret = ptrace_request(child, request, addr, data); break; @@ -303,21 +353,14 @@ static inline int audit_arch(void) { -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#ifdef CONFIG_MIPS64 - if (!(current->thread.mflags & MF_32BIT_REGS)) - return AUDIT_ARCH_MIPSEL64; -#endif /* MIPS64 */ - return AUDIT_ARCH_MIPSEL; - -#else /* big endian... */ + int arch = EM_MIPS; #ifdef CONFIG_MIPS64 - if (!(current->thread.mflags & MF_32BIT_REGS)) - return AUDIT_ARCH_MIPS64; -#endif /* MIPS64 */ - return AUDIT_ARCH_MIPS; - -#endif /* endian */ + arch |= __AUDIT_ARCH_64BIT; +#endif +#if defined(__LITTLE_ENDIAN) + arch |= __AUDIT_ARCH_LE; +#endif + return arch; } /* @@ -326,14 +369,19 @@ */ asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) { + /* do the secure computing check first */ + secure_computing(regs->orig_eax); + if (unlikely(current->audit_context) && entryexit) - audit_syscall_exit(current, AUDITSC_RESULT(regs->regs[2]), regs->regs[2]); + audit_syscall_exit(current, AUDITSC_RESULT(regs->regs[2]), + regs->regs[2]); - if (!test_thread_flag(TIF_SYSCALL_TRACE)) - goto out; if (!(current->ptrace & PT_PTRACED)) goto out; + if (!test_thread_flag(TIF_SYSCALL_TRACE)) + goto out; + /* The 0x80 provides a way for the tracing parent to distinguish between a syscall stop and SIGTRAP delivery */ ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? @@ -348,9 +396,14 @@ send_sig(current->exit_code, current, 1); current->exit_code = 0; } - out: + +out: + /* There is no ->orig_eax and that's quite intensional for now making + this work will require some work in various other place before it's + more than a placebo. */ + if (unlikely(current->audit_context) && !entryexit) - audit_syscall_entry(current, audit_arch(), regs->regs[2], - regs->regs[4], regs->regs[5], - regs->regs[6], regs->regs[7]); + audit_syscall_entry(current, audit_arch(), regs->orig_eax, + regs->regs[4], regs->regs[5], + regs->regs[6], regs->regs[7]); } diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/ptrace32.c linux-2.6.12.6/arch/mips/kernel/ptrace32.c --- linux-2.6.12.6.orig/arch/mips/kernel/ptrace32.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/ptrace32.c 2005-10-02 23:47:36.000000000 +0000 @@ -24,9 +24,9 @@ #include #include #include -#include #include +#include #include #include #include @@ -162,6 +162,27 @@ write_c0_status(flags); break; } + case DSP_BASE ... DSP_BASE + 5: + if (!cpu_has_dsp) { + tmp = 0; + ret = -EIO; + goto out_tsk; + } + if (child->thread.dsp.used_dsp) { + dspreg_t *dregs = __get_dsp_regs(child); + tmp = (unsigned long) (dregs[addr - DSP_BASE]); + } else { + tmp = -1; /* DSP registers yet used */ + } + break; + case DSP_CONTROL: + if (!cpu_has_dsp) { + tmp = 0; + ret = -EIO; + goto out_tsk; + } + tmp = child->thread.dsp.dspcontrol; + break; default: tmp = 0; ret = -EIO; @@ -231,6 +252,22 @@ else child->thread.fpu.soft.fcr31 = data; break; + case DSP_BASE ... DSP_BASE + 5: + if (!cpu_has_dsp) { + ret = -EIO; + break; + } + + dspreg_t *dregs = __get_dsp_regs(child); + dregs[addr - DSP_BASE] = data; + break; + case DSP_CONTROL: + if (!cpu_has_dsp) { + ret = -EIO; + break; + } + child->thread.dsp.dspcontrol = data; + break; default: /* The rest are not allowed. */ ret = -EIO; @@ -269,10 +306,20 @@ wake_up_process(child); break; + case PTRACE_GET_THREAD_AREA: + ret = put_user(child->thread_info->tp_value, + (unsigned int __user *) (unsigned long) data); + break; + case PTRACE_DETACH: /* detach a process that was attached. */ ret = ptrace_detach(child, data); break; + case PTRACE_GETEVENTMSG: + ret = put_user(child->ptrace_message, + (unsigned int __user *) (unsigned long) data); + break; + default: ret = ptrace_request(child, request, addr, data); break; diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/r4k_fpu.S linux-2.6.12.6/arch/mips/kernel/r4k_fpu.S --- linux-2.6.12.6.orig/arch/mips/kernel/r4k_fpu.S 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/r4k_fpu.S 2005-10-02 23:47:36.000000000 +0000 @@ -32,7 +32,7 @@ .set noreorder .set mips3 - /* Save floating point context */ + LEAF(_save_fp_context) cfc1 t1, fcr31 @@ -74,9 +74,6 @@ EX sdc1 $f28, SC_FPREGS+224(a0) EX sdc1 $f30, SC_FPREGS+240(a0) EX sw t1, SC_FPC_CSR(a0) - cfc1 t0, $0 # implementation/version - EX sw t0, SC_FPC_EIR(a0) - jr ra li v0, 0 # success END(_save_fp_context) diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/scall32-o32.S linux-2.6.12.6/arch/mips/kernel/scall32-o32.S --- linux-2.6.12.6.orig/arch/mips/kernel/scall32-o32.S 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/scall32-o32.S 2005-10-02 23:47:36.000000000 +0000 @@ -578,7 +578,7 @@ sys sys_fremovexattr 2 /* 4235 */ sys sys_tkill 2 sys sys_sendfile64 5 - sys sys_futex 2 + sys sys_futex 6 sys sys_sched_setaffinity 3 sys sys_sched_getaffinity 3 /* 4240 */ sys sys_io_setup 2 @@ -618,11 +618,12 @@ sys sys_mq_notify 2 /* 4275 */ sys sys_mq_getsetattr 3 sys sys_ni_syscall 0 /* sys_vserver */ - sys sys_waitid 4 + sys sys_waitid 5 sys sys_ni_syscall 0 /* available, was setaltroot */ - sys sys_add_key 5 + sys sys_add_key 5 /* 4280 */ sys sys_request_key 4 sys sys_keyctl 5 + sys sys_set_thread_area 1 .endm diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/scall64-64.S linux-2.6.12.6/arch/mips/kernel/scall64-64.S --- linux-2.6.12.6.orig/arch/mips/kernel/scall64-64.S 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/scall64-64.S 2005-10-02 23:47:36.000000000 +0000 @@ -449,3 +449,4 @@ PTR sys_add_key PTR sys_request_key /* 5240 */ PTR sys_keyctl + PTR sys_set_thread_area diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/scall64-n32.S linux-2.6.12.6/arch/mips/kernel/scall64-n32.S --- linux-2.6.12.6.orig/arch/mips/kernel/scall64-n32.S 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/scall64-n32.S 2005-10-02 23:47:36.000000000 +0000 @@ -176,7 +176,7 @@ PTR sys_fork PTR sys32_execve PTR sys_exit - PTR sys32_wait4 + PTR compat_sys_wait4 PTR sys_kill /* 6060 */ PTR sys32_newuname PTR sys_semget @@ -243,14 +243,14 @@ PTR sys_capget PTR sys_capset PTR sys32_rt_sigpending /* 6125 */ - PTR compat_sys_rt_sigtimedwait - PTR sys32_rt_sigqueueinfo + PTR sysn32_rt_sigtimedwait + PTR sys_rt_sigqueueinfo PTR sys32_rt_sigsuspend PTR sys32_sigaltstack PTR compat_sys_utime /* 6130 */ PTR sys_mknod PTR sys32_personality - PTR sys_ustat + PTR sys32_ustat PTR compat_sys_statfs PTR compat_sys_fstatfs /* 6135 */ PTR sys_sysfs @@ -329,7 +329,7 @@ PTR sys_epoll_wait PTR sys_remap_file_pages /* 6210 */ PTR sysn32_rt_sigreturn - PTR sys_fcntl + PTR compat_sys_fcntl64 PTR sys_set_tid_address PTR sys_restart_syscall PTR sys_semtimedop /* 6215 */ @@ -337,15 +337,15 @@ PTR compat_sys_statfs64 PTR compat_sys_fstatfs64 PTR sys_sendfile64 - PTR sys_timer_create /* 6220 */ - PTR sys_timer_settime - PTR sys_timer_gettime + PTR sys32_timer_create /* 6220 */ + PTR compat_sys_timer_settime + PTR compat_sys_timer_gettime PTR sys_timer_getoverrun PTR sys_timer_delete - PTR sys_clock_settime /* 6225 */ - PTR sys_clock_gettime - PTR sys_clock_getres - PTR sys_clock_nanosleep + PTR compat_sys_clock_settime /* 6225 */ + PTR compat_sys_clock_gettime + PTR compat_sys_clock_getres + PTR compat_sys_clock_nanosleep PTR sys_tgkill PTR compat_sys_utimes /* 6230 */ PTR sys_ni_syscall /* sys_mbind */ @@ -358,8 +358,9 @@ PTR compat_sys_mq_notify PTR compat_sys_mq_getsetattr PTR sys_ni_syscall /* 6240, sys_vserver */ - PTR sys_waitid + PTR sysn32_waitid PTR sys_ni_syscall /* available, was setaltroot */ PTR sys_add_key PTR sys_request_key PTR sys_keyctl /* 6245 */ + PTR sys_set_thread_area diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/scall64-o32.S linux-2.6.12.6/arch/mips/kernel/scall64-o32.S --- linux-2.6.12.6.orig/arch/mips/kernel/scall64-o32.S 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/scall64-o32.S 2005-10-02 23:47:36.000000000 +0000 @@ -316,13 +316,13 @@ PTR sys_vhangup PTR sys_ni_syscall /* was sys_idle */ PTR sys_ni_syscall /* sys_vm86 */ - PTR sys32_wait4 + PTR compat_sys_wait4 PTR sys_swapoff /* 4115 */ PTR sys32_sysinfo PTR sys32_ipc PTR sys_fsync PTR sys32_sigreturn - PTR sys_clone /* 4120 */ + PTR sys32_clone /* 4120 */ PTR sys_setdomainname PTR sys32_newuname PTR sys_ni_syscall /* sys_modify_ldt */ @@ -391,7 +391,7 @@ PTR sys_getresuid PTR sys_ni_syscall /* was query_module */ PTR sys_poll - PTR sys_nfsservctl + PTR compat_sys_nfsservctl PTR sys_setresgid /* 4190 */ PTR sys_getresgid PTR sys_prctl @@ -459,7 +459,7 @@ PTR sys_fadvise64_64 PTR compat_sys_statfs64 /* 4255 */ PTR compat_sys_fstatfs64 - PTR sys_timer_create + PTR sys32_timer_create PTR compat_sys_timer_settime PTR compat_sys_timer_gettime PTR sys_timer_getoverrun /* 4260 */ @@ -480,9 +480,10 @@ PTR compat_sys_mq_notify /* 4275 */ PTR compat_sys_mq_getsetattr PTR sys_ni_syscall /* sys_vserver */ - PTR sys_waitid + PTR sys32_waitid PTR sys_ni_syscall /* available, was setaltroot */ PTR sys_add_key /* 4280 */ PTR sys_request_key PTR sys_keyctl + PTR sys_set_thread_area .size sys_call_table,.-sys_call_table diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/semaphore.c linux-2.6.12.6/arch/mips/kernel/semaphore.c --- linux-2.6.12.6.orig/arch/mips/kernel/semaphore.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/semaphore.c 2005-10-02 23:47:36.000000000 +0000 @@ -42,24 +42,28 @@ if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( - "1: ll %0, %2 \n" + " .set mips3 \n" + "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" " and %1, %0, %1 \n" - " add %1, %1, %3 \n" + " addu %1, %1, %3 \n" " sc %1, %2 \n" " beqzl %1, 1b \n" + " .set mips0 \n" : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) : "r" (incr), "m" (sem->count)); } else if (cpu_has_llsc) { __asm__ __volatile__( - "1: ll %0, %2 \n" + " .set mips3 \n" + "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" " and %1, %0, %1 \n" - " add %1, %1, %3 \n" + " addu %1, %1, %3 \n" " sc %1, %2 \n" " beqz %1, 1b \n" + " .set mips0 \n" : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) : "r" (incr), "m" (sem->count)); } else { diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/setup.c linux-2.6.12.6/arch/mips/kernel/setup.c --- linux-2.6.12.6.orig/arch/mips/kernel/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/setup.c 2005-10-02 23:47:36.000000000 +0000 @@ -507,32 +507,6 @@ #undef MAXMEM #undef MAXMEM_PFN -static int __initdata earlyinit_debug; - -static int __init earlyinit_debug_setup(char *str) -{ - earlyinit_debug = 1; - return 1; -} -__setup("earlyinit_debug", earlyinit_debug_setup); - -extern initcall_t __earlyinitcall_start, __earlyinitcall_end; - -static void __init do_earlyinitcalls(void) -{ - initcall_t *call, *start, *end; - - start = &__earlyinitcall_start; - end = &__earlyinitcall_end; - - for (call = start; call < end; call++) { - if (earlyinit_debug) - printk("calling earlyinitcall 0x%p\n", *call); - - (*call)(); - } -} - void __init setup_arch(char **cmdline_p) { cpu_probe(); @@ -548,7 +522,7 @@ #endif /* call board setup routine */ - do_earlyinitcalls(); + plat_setup(); strlcpy(command_line, arcs_cmdline, sizeof(command_line)); strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE); @@ -569,3 +543,12 @@ } __setup("nofpu", fpu_disable); + +int __init dsp_disable(char *s) +{ + cpu_data[0].options &= ~MIPS_ASE_DSP; + + return 1; +} + +__setup("nodsp", dsp_disable); diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/signal-common.h linux-2.6.12.6/arch/mips/kernel/signal-common.h --- linux-2.6.12.6.orig/arch/mips/kernel/signal-common.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/signal-common.h 2005-10-02 23:47:36.000000000 +0000 @@ -8,13 +8,14 @@ * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ +#include + static inline int setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc) { int err = 0; err |= __put_user(regs->cp0_epc, &sc->sc_pc); - err |= __put_user(regs->cp0_status, &sc->sc_status); #define save_gp_reg(i) do { \ err |= __put_user(regs->regs[i], &sc->sc_regs[i]); \ @@ -30,10 +31,32 @@ save_gp_reg(31); #undef save_gp_reg +#ifdef CONFIG_MIPS32 err |= __put_user(regs->hi, &sc->sc_mdhi); err |= __put_user(regs->lo, &sc->sc_mdlo); - err |= __put_user(regs->cp0_cause, &sc->sc_cause); - err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr); + if (cpu_has_dsp) { + err |= __put_user(mfhi1(), &sc->sc_hi1); + err |= __put_user(mflo1(), &sc->sc_lo1); + err |= __put_user(mfhi2(), &sc->sc_hi2); + err |= __put_user(mflo2(), &sc->sc_lo2); + err |= __put_user(mfhi3(), &sc->sc_hi3); + err |= __put_user(mflo3(), &sc->sc_lo3); + err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp); + } +#endif +#ifdef CONFIG_MIPS64 + err |= __put_user(regs->hi, &sc->sc_hi[0]); + err |= __put_user(regs->lo, &sc->sc_lo[0]); + if (cpu_has_dsp) { + err |= __put_user(mfhi1(), &sc->sc_hi[1]); + err |= __put_user(mflo1(), &sc->sc_lo[1]); + err |= __put_user(mfhi2(), &sc->sc_hi[2]); + err |= __put_user(mflo2(), &sc->sc_lo[2]); + err |= __put_user(mfhi3(), &sc->sc_hi[3]); + err |= __put_user(mflo3(), &sc->sc_lo[3]); + err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp); + } +#endif err |= __put_user(!!used_math(), &sc->sc_used_math); @@ -61,15 +84,40 @@ static inline int restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) { - int err = 0; unsigned int used_math; + unsigned long treg; + int err = 0; /* Always make any pending restarted system calls return -EINTR */ current_thread_info()->restart_block.fn = do_no_restart_syscall; err |= __get_user(regs->cp0_epc, &sc->sc_pc); +#ifdef CONFIG_MIPS32 err |= __get_user(regs->hi, &sc->sc_mdhi); err |= __get_user(regs->lo, &sc->sc_mdlo); + if (cpu_has_dsp) { + err |= __get_user(treg, &sc->sc_hi1); mthi1(treg); + err |= __get_user(treg, &sc->sc_lo1); mtlo1(treg); + err |= __get_user(treg, &sc->sc_hi2); mthi2(treg); + err |= __get_user(treg, &sc->sc_lo2); mtlo2(treg); + err |= __get_user(treg, &sc->sc_hi3); mthi3(treg); + err |= __get_user(treg, &sc->sc_lo3); mtlo3(treg); + err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK); + } +#endif +#ifdef CONFIG_MIPS64 + err |= __get_user(regs->hi, &sc->sc_hi[0]); + err |= __get_user(regs->lo, &sc->sc_lo[0]); + if (cpu_has_dsp) { + err |= __get_user(treg, &sc->sc_hi[1]); mthi1(treg); + err |= __get_user(treg, &sc->sc_lo[1]); mthi1(treg); + err |= __get_user(treg, &sc->sc_hi[2]); mthi2(treg); + err |= __get_user(treg, &sc->sc_lo[2]); mthi2(treg); + err |= __get_user(treg, &sc->sc_hi[3]); mthi3(treg); + err |= __get_user(treg, &sc->sc_lo[3]); mthi3(treg); + err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK); + } +#endif #define restore_gp_reg(i) do { \ err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \ @@ -112,7 +160,7 @@ static inline void * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) { - unsigned long sp, almask; + unsigned long sp; /* Default to using normal stack */ sp = regs->regs[29]; @@ -128,10 +176,32 @@ if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0)) sp = current->sas_ss_sp + current->sas_ss_size; - if (PLAT_TRAMPOLINE_STUFF_LINE) - almask = ~(PLAT_TRAMPOLINE_STUFF_LINE - 1); - else - almask = ALMASK; + return (void *)((sp - frame_size) & (ICACHE_REFILLS_WORKAROUND_WAR ? 32 : ALMASK)); +} + +static inline int install_sigtramp(unsigned int __user *tramp, + unsigned int syscall) +{ + int err; + + /* + * Set up the return code ... + * + * li v0, __NR__foo_sigreturn + * syscall + */ + + err |= __put_user(0x24020000 + syscall, tramp + 0); + err |= __put_user(0x0000000c , tramp + 1); + if (ICACHE_REFILLS_WORKAROUND_WAR) { + err |= __put_user(0, tramp + 2); + err |= __put_user(0, tramp + 3); + err |= __put_user(0, tramp + 4); + err |= __put_user(0, tramp + 5); + err |= __put_user(0, tramp + 6); + err |= __put_user(0, tramp + 7); + } + flush_cache_sigtramp((unsigned long) tramp); - return (void *)((sp - frame_size) & almask); + return err; } diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/signal.c linux-2.6.12.6/arch/mips/kernel/signal.c --- linux-2.6.12.6.orig/arch/mips/kernel/signal.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/signal.c 2005-10-02 23:47:36.000000000 +0000 @@ -8,6 +8,7 @@ * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #include +#include #include #include #include @@ -21,6 +22,7 @@ #include #include +#include #include #include #include @@ -29,6 +31,7 @@ #include #include #include +#include #include "signal-common.h" @@ -36,7 +39,7 @@ #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) -static int do_signal(sigset_t *oldset, struct pt_regs *regs); +int do_signal(sigset_t *oldset, struct pt_regs *regs); /* * Atomically swap in the new signal mask, and wait for a signal. @@ -47,9 +50,10 @@ __attribute_used__ noinline static int _sys_sigsuspend(nabi_no_regargs struct pt_regs regs) { - sigset_t *uset, saveset, newset; + sigset_t saveset, newset; + sigset_t __user *uset; - uset = (sigset_t *) regs.regs[4]; + uset = (sigset_t __user *) regs.regs[4]; if (copy_from_user(&newset, uset, sizeof(sigset_t))) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); @@ -75,7 +79,8 @@ __attribute_used__ noinline static int _sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) { - sigset_t *unewset, saveset, newset; + sigset_t saveset, newset; + sigset_t __user *unewset; size_t sigsetsize; /* XXX Don't preclude handling different sized sigset_t's. */ @@ -83,7 +88,7 @@ if (sigsetsize != sizeof(sigset_t)) return -EINVAL; - unewset = (sigset_t *) regs.regs[4]; + unewset = (sigset_t __user *) regs.regs[4]; if (copy_from_user(&newset, unewset, sizeof(newset))) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); @@ -147,33 +152,46 @@ asmlinkage int sys_sigaltstack(nabi_no_regargs struct pt_regs regs) { - const stack_t *uss = (const stack_t *) regs.regs[4]; - stack_t *uoss = (stack_t *) regs.regs[5]; + const stack_t __user *uss = (const stack_t __user *) regs.regs[4]; + stack_t __user *uoss = (stack_t __user *) regs.regs[5]; unsigned long usp = regs.regs[29]; return do_sigaltstack(uss, uoss, usp); } -#if PLAT_TRAMPOLINE_STUFF_LINE -#define __tramp __attribute__((aligned(PLAT_TRAMPOLINE_STUFF_LINE))) -#else -#define __tramp -#endif - +/* + * Horribly complicated - with the bloody RM9000 workarounds enabled + * the signal trampolines is moving to the end of the structure so we can + * increase the alignment without breaking software compatibility. + */ #ifdef CONFIG_TRAD_SIGNALS struct sigframe { u32 sf_ass[4]; /* argument save space for o32 */ - u32 sf_code[2] __tramp; /* signal trampoline */ - struct sigcontext sf_sc __tramp; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 sf_pad[2]; +#else + u32 sf_code[2]; /* signal trampoline */ +#endif + struct sigcontext sf_sc; sigset_t sf_mask; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 sf_code[8] ____cacheline_aligned; /* signal trampoline */ +#endif }; #endif struct rt_sigframe { u32 rs_ass[4]; /* argument save space for o32 */ - u32 rs_code[2] __tramp; /* signal trampoline */ - struct siginfo rs_info __tramp; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_pad[2]; +#else + u32 rs_code[2]; /* signal trampoline */ +#endif + struct siginfo rs_info; struct ucontext rs_uc; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_code[8] ____cacheline_aligned; /* signal trampoline */ +#endif }; #ifdef CONFIG_TRAD_SIGNALS @@ -214,7 +232,7 @@ badframe: force_sig(SIGSEGV, current); } -#endif +#endif /* CONFIG_TRAD_SIGNALS */ save_static_function(sys_rt_sigreturn); __attribute_used__ noinline static void @@ -260,7 +278,7 @@ } #ifdef CONFIG_TRAD_SIGNALS -static void inline setup_frame(struct k_sigaction * ka, struct pt_regs *regs, +void setup_frame(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set) { struct sigframe *frame; @@ -270,17 +288,7 @@ if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - /* - * Set up the return code ... - * - * li v0, __NR_sigreturn - * syscall - */ - if (PLAT_TRAMPOLINE_STUFF_LINE) - __clear_user(frame->sf_code, PLAT_TRAMPOLINE_STUFF_LINE); - err |= __put_user(0x24020000 + __NR_sigreturn, frame->sf_code + 0); - err |= __put_user(0x0000000c , frame->sf_code + 1); - flush_cache_sigtramp((unsigned long) frame->sf_code); + install_sigtramp(frame->sf_code, __NR_sigreturn); err |= setup_sigcontext(regs, &frame->sf_sc); err |= __copy_to_user(&frame->sf_mask, set, sizeof(*set)); @@ -316,7 +324,7 @@ } #endif -static void inline setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, +void setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info) { struct rt_sigframe *frame; @@ -326,17 +334,7 @@ if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - /* - * Set up the return code ... - * - * li v0, __NR_rt_sigreturn - * syscall - */ - if (PLAT_TRAMPOLINE_STUFF_LINE) - __clear_user(frame->rs_code, PLAT_TRAMPOLINE_STUFF_LINE); - err |= __put_user(0x24020000 + __NR_rt_sigreturn, frame->rs_code + 0); - err |= __put_user(0x0000000c , frame->rs_code + 1); - flush_cache_sigtramp((unsigned long) frame->rs_code); + install_sigtramp(frame->rs_code, __NR_rt_sigreturn); /* Create siginfo. */ err |= copy_siginfo_to_user(&frame->rs_info, info); @@ -408,22 +406,10 @@ regs->regs[0] = 0; /* Don't deal with this again. */ -#ifdef CONFIG_TRAD_SIGNALS - if (ka->sa.sa_flags & SA_SIGINFO) { -#else - if (1) { -#endif -#ifdef CONFIG_MIPS32_N32 - if ((current->thread.mflags & MF_ABI_MASK) == MF_N32) - setup_rt_frame_n32 (ka, regs, sig, oldset, info); - else -#endif - setup_rt_frame(ka, regs, sig, oldset, info); - } -#ifdef CONFIG_TRAD_SIGNALS + if (sig_uses_siginfo(ka)) + current->thread.abi->setup_rt_frame(ka, regs, sig, oldset, info); else - setup_frame(ka, regs, sig, oldset); -#endif + current->thread.abi->setup_frame(ka, regs, sig, oldset); if (!(ka->sa.sa_flags & SA_NODEFER)) { spin_lock_irq(¤t->sighand->siglock); @@ -434,21 +420,12 @@ } } -extern int do_signal32(sigset_t *oldset, struct pt_regs *regs); -extern int do_irix_signal(sigset_t *oldset, struct pt_regs *regs); - -static int do_signal(sigset_t *oldset, struct pt_regs *regs) +int do_signal(sigset_t *oldset, struct pt_regs *regs) { struct k_sigaction ka; siginfo_t info; int signr; -#ifdef CONFIG_BINFMT_ELF32 - if ((current->thread.mflags & MF_ABI_MASK) == MF_O32) { - return do_signal32(oldset, regs); - } -#endif - /* * We want the common case to go fast, which is why we may in certain * cases get here from kernel mode. Just return without doing anything @@ -500,18 +477,6 @@ { /* deal with pending signal delivery */ if (thread_info_flags & _TIF_SIGPENDING) { -#ifdef CONFIG_BINFMT_ELF32 - if (likely((current->thread.mflags & MF_ABI_MASK) == MF_O32)) { - do_signal32(oldset, regs); - return; - } -#endif -#ifdef CONFIG_BINFMT_IRIX - if (unlikely(current->personality != PER_LINUX)) { - do_irix_signal(oldset, regs); - return; - } -#endif - do_signal(oldset, regs); + current->thread.abi->do_signal(oldset, regs); } } diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/signal32.c linux-2.6.12.6/arch/mips/kernel/signal32.c --- linux-2.6.12.6.orig/arch/mips/kernel/signal32.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/signal32.c 2005-10-02 23:47:36.000000000 +0000 @@ -7,6 +7,7 @@ * Copyright (C) 1994 - 2000 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ +#include #include #include #include @@ -21,6 +22,7 @@ #include #include +#include #include #include #include @@ -29,6 +31,7 @@ #include #include #include +#include #define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3) @@ -76,8 +79,10 @@ /* POSIX.1b timers */ struct { - unsigned int _timer1; - unsigned int _timer2; + timer_t _tid; /* timer id */ + int _overrun; /* overrun count */ + compat_sigval_t _sigval;/* same as below */ + int _sys_private; /* not to be passed to user */ } _timer; /* POSIX.1b signals */ @@ -259,11 +264,12 @@ if (act) { old_sigset_t mask; + s32 handler; if (!access_ok(VERIFY_READ, act, sizeof(*act))) return -EFAULT; - err |= __get_user((u32)(u64)new_ka.sa.sa_handler, - &act->sa_handler); + err |= __get_user(handler, &act->sa_handler); + new_ka.sa.sa_handler = (void*)(s64)handler; err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags); err |= __get_user(mask, &act->sa_mask.sig[0]); if (err) @@ -331,8 +337,9 @@ static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 *sc) { + u32 used_math; int err = 0; - __u32 used_math; + s32 treg; /* Always make any pending restarted system calls return -EINTR */ current_thread_info()->restart_block.fn = do_no_restart_syscall; @@ -340,6 +347,15 @@ err |= __get_user(regs->cp0_epc, &sc->sc_pc); err |= __get_user(regs->hi, &sc->sc_mdhi); err |= __get_user(regs->lo, &sc->sc_mdlo); + if (cpu_has_dsp) { + err |= __get_user(treg, &sc->sc_hi1); mthi1(treg); + err |= __get_user(treg, &sc->sc_lo1); mtlo1(treg); + err |= __get_user(treg, &sc->sc_hi2); mthi2(treg); + err |= __get_user(treg, &sc->sc_lo2); mtlo2(treg); + err |= __get_user(treg, &sc->sc_hi3); mthi3(treg); + err |= __get_user(treg, &sc->sc_lo3); mtlo3(treg); + err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK); + } #define restore_gp_reg(i) do { \ err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \ @@ -378,16 +394,30 @@ struct sigframe { u32 sf_ass[4]; /* argument save space for o32 */ +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 sf_pad[2]; +#else u32 sf_code[2]; /* signal trampoline */ +#endif struct sigcontext32 sf_sc; sigset_t sf_mask; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 sf_code[8] ____cacheline_aligned; /* signal trampoline */ +#endif }; struct rt_sigframe32 { u32 rs_ass[4]; /* argument save space for o32 */ +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_pad[2]; +#else u32 rs_code[2]; /* signal trampoline */ +#endif compat_siginfo_t rs_info; struct ucontext32 rs_uc; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_code[8] __attribute__((aligned(32))); /* signal trampoline */ +#endif }; int copy_siginfo_to_user32(compat_siginfo_t *to, siginfo_t *from) @@ -411,6 +441,11 @@ err |= __copy_to_user(&to->_sifields._pad, &from->_sifields._pad, SI_PAD_SIZE); else { switch (from->si_code >> 16) { + case __SI_TIMER >> 16: + err |= __put_user(from->si_tid, &to->si_tid); + err |= __put_user(from->si_overrun, &to->si_overrun); + err |= __put_user(from->si_int, &to->si_int); + break; case __SI_CHLD >> 16: err |= __put_user(from->si_utime, &to->si_utime); err |= __put_user(from->si_stime, &to->si_stime); @@ -480,6 +515,7 @@ _sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) { struct rt_sigframe32 *frame; + mm_segment_t old_fs; sigset_t set; stack_t st; s32 sp; @@ -510,7 +546,10 @@ /* It is more difficult to avoid calling this function than to call it and ignore errors. */ + old_fs = get_fs(); + set_fs (KERNEL_DS); do_sigaltstack(&st, NULL, regs.regs[29]); + set_fs (old_fs); /* * Don't let your children do this ... @@ -550,8 +589,15 @@ err |= __put_user(regs->hi, &sc->sc_mdhi); err |= __put_user(regs->lo, &sc->sc_mdlo); - err |= __put_user(regs->cp0_cause, &sc->sc_cause); - err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr); + if (cpu_has_dsp) { + err |= __put_user(rddsp(DSP_MASK), &sc->sc_hi1); + err |= __put_user(mfhi1(), &sc->sc_hi1); + err |= __put_user(mflo1(), &sc->sc_lo1); + err |= __put_user(mfhi2(), &sc->sc_hi2); + err |= __put_user(mflo2(), &sc->sc_lo2); + err |= __put_user(mfhi3(), &sc->sc_hi3); + err |= __put_user(mflo3(), &sc->sc_lo3); + } err |= __put_user(!!used_math(), &sc->sc_used_math); @@ -601,7 +647,7 @@ return (void *)((sp - frame_size) & ALMASK); } -static inline void setup_frame(struct k_sigaction * ka, struct pt_regs *regs, +void setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set) { struct sigframe *frame; @@ -654,9 +700,7 @@ force_sigsegv(signr, current); } -static inline void setup_rt_frame(struct k_sigaction * ka, - struct pt_regs *regs, int signr, - sigset_t *set, siginfo_t *info) +void setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info) { struct rt_sigframe32 *frame; int err = 0; @@ -747,9 +791,9 @@ regs->regs[0] = 0; /* Don't deal with this again. */ if (ka->sa.sa_flags & SA_SIGINFO) - setup_rt_frame(ka, regs, sig, oldset, info); + current->thread.abi->setup_rt_frame(ka, regs, sig, oldset, info); else - setup_frame(ka, regs, sig, oldset); + current->thread.abi->setup_frame(ka, regs, sig, oldset); if (!(ka->sa.sa_flags & SA_NODEFER)) { spin_lock_irq(¤t->sighand->siglock); @@ -820,12 +864,13 @@ goto out; if (act) { + s32 handler; int err = 0; if (!access_ok(VERIFY_READ, act, sizeof(*act))) return -EFAULT; - err |= __get_user((u32)(u64)new_sa.sa.sa_handler, - &act->sa_handler); + err |= __get_user(handler, &act->sa_handler); + new_sa.sa.sa_handler = (void*)(s64)handler; err |= __get_user(new_sa.sa.sa_flags, &act->sa_flags); err |= get_sigset(&new_sa.sa.sa_mask, &act->sa_mask); if (err) @@ -903,3 +948,30 @@ set_fs (old_fs); return ret; } + +asmlinkage long +sys32_waitid(int which, compat_pid_t pid, + compat_siginfo_t __user *uinfo, int options, + struct compat_rusage __user *uru) +{ + siginfo_t info; + struct rusage ru; + long ret; + mm_segment_t old_fs = get_fs(); + + info.si_signo = 0; + set_fs (KERNEL_DS); + ret = sys_waitid(which, pid, (siginfo_t __user *) &info, options, + uru ? (struct rusage __user *) &ru : NULL); + set_fs (old_fs); + + if (ret < 0 || info.si_signo == 0) + return ret; + + if (uru && (ret = put_compat_rusage(&ru, uru))) + return ret; + + BUG_ON(info.si_code & __SI_MASK); + info.si_code |= __SI_CHLD; + return copy_siginfo_to_user32(uinfo, &info); +} diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/signal_n32.c linux-2.6.12.6/arch/mips/kernel/signal_n32.c --- linux-2.6.12.6.orig/arch/mips/kernel/signal_n32.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/signal_n32.c 2005-10-02 23:47:36.000000000 +0000 @@ -15,6 +15,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include +#include #include #include #include @@ -36,6 +38,7 @@ #include #include #include +#include #include "signal-common.h" @@ -62,17 +65,18 @@ sigset_t uc_sigmask; /* mask last for extensibility */ }; -#if PLAT_TRAMPOLINE_STUFF_LINE -#define __tramp __attribute__((aligned(PLAT_TRAMPOLINE_STUFF_LINE))) -#else -#define __tramp -#endif - struct rt_sigframe_n32 { u32 rs_ass[4]; /* argument save space for o32 */ - u32 rs_code[2] __tramp; /* signal trampoline */ - struct siginfo rs_info __tramp; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_pad[2]; +#else + u32 rs_code[2]; /* signal trampoline */ +#endif + struct siginfo rs_info; struct ucontextn32 rs_uc; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_code[8] ____cacheline_aligned; /* signal trampoline */ +#endif }; save_static_function(sysn32_rt_sigreturn); @@ -137,17 +141,7 @@ if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - /* - * Set up the return code ... - * - * li v0, __NR_rt_sigreturn - * syscall - */ - if (PLAT_TRAMPOLINE_STUFF_LINE) - __clear_user(frame->rs_code, PLAT_TRAMPOLINE_STUFF_LINE); - err |= __put_user(0x24020000 + __NR_N32_rt_sigreturn, frame->rs_code + 0); - err |= __put_user(0x0000000c , frame->rs_code + 1); - flush_cache_sigtramp((unsigned long) frame->rs_code); + install_sigtramp(frame->rs_code, __NR_N32_rt_sigreturn); /* Create siginfo. */ err |= copy_siginfo_to_user(&frame->rs_info, info); diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/smp.c linux-2.6.12.6/arch/mips/kernel/smp.c --- linux-2.6.12.6.orig/arch/mips/kernel/smp.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/smp.c 2005-10-02 23:47:36.000000000 +0000 @@ -121,7 +121,19 @@ * or are or have executed. * * You must not call this function with disabled interrupts or from a - * hardware interrupt handler or from a bottom half handler. + * hardware interrupt handler or from a bottom half handler: + * + * CPU A CPU B + * Disable interrupts + * smp_call_function() + * Take call_lock + * Send IPIs + * Wait for all cpus to acknowledge IPI + * CPU A has not responded, spin waiting + * for cpu A to respond, holding call_lock + * smp_call_function() + * Spin waiting for call_lock + * Deadlock Deadlock */ int smp_call_function (void (*func) (void *info), void *info, int retry, int wait) @@ -214,7 +226,6 @@ /* called from main before smp_init() */ void __init smp_prepare_cpus(unsigned int max_cpus) { - cpu_data[0].udelay_val = loops_per_jiffy; init_new_context(current, &init_mm); current_thread_info()->cpu = 0; smp_tune_scheduling(); @@ -236,23 +247,28 @@ } /* - * Startup the CPU with this logical number + * Called once for each "cpu_possible(cpu)". Needs to spin up the cpu + * and keep control until "cpu_online(cpu)" is set. Note: cpu is + * physical, not logical. */ -static int __init do_boot_cpu(int cpu) +int __devinit __cpu_up(unsigned int cpu) { struct task_struct *idle; /* + * Processor goes to start_secondary(), sets online flag * The following code is purely to make sure * Linux can schedule processes on this slave. */ idle = fork_idle(cpu); if (IS_ERR(idle)) - panic("failed fork for CPU %d\n", cpu); + panic(KERN_ERR "Fork failed for CPU %d\n", cpu); prom_boot_secondary(cpu, idle); - /* XXXKW timeout */ + /* + * Trust is futile. We should really have timeouts ... + */ while (!cpu_isset(cpu, cpu_callin_map)) udelay(100); @@ -261,23 +277,6 @@ return 0; } -/* - * Called once for each "cpu_possible(cpu)". Needs to spin up the cpu - * and keep control until "cpu_online(cpu)" is set. Note: cpu is - * physical, not logical. - */ -int __devinit __cpu_up(unsigned int cpu) -{ - int ret; - - /* Processor goes to start_secondary(), sets online flag */ - ret = do_boot_cpu(cpu); - if (ret < 0) - return ret; - - return 0; -} - /* Not really SMP stuff ... */ int setup_profiling_timer(unsigned int multiplier) { diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/syscall.c linux-2.6.12.6/arch/mips/kernel/syscall.c --- linux-2.6.12.6.orig/arch/mips/kernel/syscall.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/syscall.c 2005-10-02 23:47:36.000000000 +0000 @@ -7,6 +7,7 @@ * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. */ +#include #include #include #include @@ -26,6 +27,7 @@ #include #include #include +#include #include #include @@ -56,6 +58,8 @@ unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */ +EXPORT_SYMBOL(shm_align_mask); + #define COLOUR_ALIGN(addr,pgoff) \ ((((addr) + shm_align_mask) & ~shm_align_mask) + \ (((pgoff) << PAGE_SHIFT) & shm_align_mask)) @@ -173,14 +177,28 @@ { unsigned long clone_flags; unsigned long newsp; - int *parent_tidptr, *child_tidptr; + int __user *parent_tidptr, *child_tidptr; clone_flags = regs.regs[4]; newsp = regs.regs[5]; if (!newsp) newsp = regs.regs[29]; - parent_tidptr = (int *) regs.regs[6]; - child_tidptr = (int *) regs.regs[7]; + parent_tidptr = (int __user *) regs.regs[6]; +#ifdef CONFIG_MIPS32 + /* We need to fetch the fifth argument off the stack. */ + child_tidptr = NULL; + if (clone_flags & (CLONE_CHILD_SETTID | CLONE_CHILD_CLEARTID)) { + int __user *__user *usp = (int __user *__user *) regs.regs[29]; + if (regs.regs[2] == __NR_syscall) { + if (get_user (child_tidptr, &usp[5])) + return -EFAULT; + } + else if (get_user (child_tidptr, &usp[4])) + return -EFAULT; + } +#else + child_tidptr = (int __user *) regs.regs[8]; +#endif return do_fork(clone_flags, newsp, ®s, 0, parent_tidptr, child_tidptr); } @@ -242,6 +260,16 @@ return error; } +void sys_set_thread_area(unsigned long addr) +{ + struct thread_info *ti = current->thread_info; + + ti->tp_value = addr; + + /* If some future MIPS implementation has this register in hardware, + * we will need to update it here (and in context switches). */ +} + asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3) { int tmp, len; diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/sysirix.c linux-2.6.12.6/arch/mips/kernel/sysirix.c --- linux-2.6.12.6.orig/arch/mips/kernel/sysirix.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/sysirix.c 2005-10-02 23:47:37.000000000 +0000 @@ -73,32 +73,30 @@ } /* The prctl commands. */ -#define PR_MAXPROCS 1 /* Tasks/user. */ -#define PR_ISBLOCKED 2 /* If blocked, return 1. */ -#define PR_SETSTACKSIZE 3 /* Set largest task stack size. */ -#define PR_GETSTACKSIZE 4 /* Get largest task stack size. */ -#define PR_MAXPPROCS 5 /* Num parallel tasks. */ -#define PR_UNBLKONEXEC 6 /* When task exec/exit's, unblock. */ -#define PR_SETEXITSIG 8 /* When task exit's, set signal. */ -#define PR_RESIDENT 9 /* Make task unswappable. */ -#define PR_ATTACHADDR 10 /* (Re-)Connect a vma to a task. */ -#define PR_DETACHADDR 11 /* Disconnect a vma from a task. */ -#define PR_TERMCHILD 12 /* When parent sleeps with fishes, kill child. */ -#define PR_GETSHMASK 13 /* Get the sproc() share mask. */ -#define PR_GETNSHARE 14 /* Number of share group members. */ -#define PR_COREPID 15 /* Add task pid to name when it core. */ -#define PR_ATTACHADDRPERM 16 /* (Re-)Connect vma, with specified prot. */ -#define PR_PTHREADEXIT 17 /* Kill a pthread without prejudice. */ +#define PR_MAXPROCS 1 /* Tasks/user. */ +#define PR_ISBLOCKED 2 /* If blocked, return 1. */ +#define PR_SETSTACKSIZE 3 /* Set largest task stack size. */ +#define PR_GETSTACKSIZE 4 /* Get largest task stack size. */ +#define PR_MAXPPROCS 5 /* Num parallel tasks. */ +#define PR_UNBLKONEXEC 6 /* When task exec/exit's, unblock. */ +#define PR_SETEXITSIG 8 /* When task exit's, set signal. */ +#define PR_RESIDENT 9 /* Make task unswappable. */ +#define PR_ATTACHADDR 10 /* (Re-)Connect a vma to a task. */ +#define PR_DETACHADDR 11 /* Disconnect a vma from a task. */ +#define PR_TERMCHILD 12 /* Kill child if the parent dies. */ +#define PR_GETSHMASK 13 /* Get the sproc() share mask. */ +#define PR_GETNSHARE 14 /* Number of share group members. */ +#define PR_COREPID 15 /* Add task pid to name when it core. */ +#define PR_ATTACHADDRPERM 16 /* (Re-)Connect vma, with specified prot. */ +#define PR_PTHREADEXIT 17 /* Kill a pthread, only for IRIX 6.[234] */ -asmlinkage int irix_prctl(struct pt_regs *regs) +asmlinkage int irix_prctl(unsigned option, ...) { - unsigned long cmd; - int error = 0, base = 0; + va_list args; + int error = 0; - if (regs->regs[2] == 1000) - base = 1; - cmd = regs->regs[base + 4]; - switch (cmd) { + va_start(args, option); + switch (option) { case PR_MAXPROCS: printk("irix_prctl[%s:%d]: Wants PR_MAXPROCS\n", current->comm, current->pid); @@ -111,7 +109,7 @@ printk("irix_prctl[%s:%d]: Wants PR_ISBLOCKED\n", current->comm, current->pid); read_lock(&tasklist_lock); - task = find_task_by_pid(regs->regs[base + 5]); + task = find_task_by_pid(va_arg(args, pid_t)); error = -ESRCH; if (error) error = (task->run_list.next != NULL); @@ -121,7 +119,7 @@ } case PR_SETSTACKSIZE: { - long value = regs->regs[base + 5]; + long value = va_arg(args, long); printk("irix_prctl[%s:%d]: Wants PR_SETSTACKSIZE<%08lx>\n", current->comm, current->pid, (unsigned long) value); @@ -222,24 +220,20 @@ error = -EINVAL; break; - case PR_PTHREADEXIT: - printk("irix_prctl[%s:%d]: Wants PR_PTHREADEXIT\n", - current->comm, current->pid); - do_exit(regs->regs[base + 5]); - default: printk("irix_prctl[%s:%d]: Non-existant opcode %d\n", - current->comm, current->pid, (int)cmd); + current->comm, current->pid, option); error = -EINVAL; break; } + va_end(args); return error; } #undef DEBUG_PROCGRPS -extern unsigned long irix_mapelf(int fd, struct elf_phdr *user_phdrp, int cnt); +extern unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt); extern int getrusage(struct task_struct *p, int who, struct rusage __user *ru); extern char *prom_getenv(char *name); extern long prom_setenv(char *name, char *value); @@ -276,23 +270,19 @@ cmd = regs->regs[base + 4]; switch(cmd) { case SGI_SYSID: { - char *buf = (char *) regs->regs[base + 5]; + char __user *buf = (char __user *) regs->regs[base + 5]; /* XXX Use ethernet addr.... */ - retval = clear_user(buf, 64); + retval = clear_user(buf, 64) ? -EFAULT : 0; break; } #if 0 case SGI_RDNAME: { int pid = (int) regs->regs[base + 5]; - char *buf = (char *) regs->regs[base + 6]; + char __user *buf = (char *) regs->regs[base + 6]; struct task_struct *p; char tcomm[sizeof(current->comm)]; - if (!access_ok(VERIFY_WRITE, buf, sizeof(tcomm))) { - retval = -EFAULT; - break; - } read_lock(&tasklist_lock); p = find_task_by_pid(pid); if (!p) { @@ -304,34 +294,28 @@ read_unlock(&tasklist_lock); /* XXX Need to check sizes. */ - copy_to_user(buf, tcomm, sizeof(tcomm)); - retval = 0; + retval = copy_to_user(buf, tcomm, sizeof(tcomm)) ? -EFAULT : 0; break; } case SGI_GETNVRAM: { - char *name = (char *) regs->regs[base+5]; - char *buf = (char *) regs->regs[base+6]; + char __user *name = (char __user *) regs->regs[base+5]; + char __user *buf = (char __user *) regs->regs[base+6]; char *value; return -EINVAL; /* til I fix it */ - if (!access_ok(VERIFY_WRITE, buf, 128)) { - retval = -EFAULT; - break; - } value = prom_getenv(name); /* PROM lock? */ if (!value) { retval = -EINVAL; break; } /* Do I strlen() for the length? */ - copy_to_user(buf, value, 128); - retval = 0; + retval = copy_to_user(buf, value, 128) ? -EFAULT : 0; break; } case SGI_SETNVRAM: { - char *name = (char *) regs->regs[base+5]; - char *value = (char *) regs->regs[base+6]; + char __user *name = (char __user *) regs->regs[base+5]; + char __user *value = (char __user *) regs->regs[base+6]; return -EINVAL; /* til I fix it */ retval = prom_setenv(name, value); /* XXX make sure retval conforms to syssgi(2) */ @@ -407,16 +391,16 @@ case SGI_SETGROUPS: retval = sys_setgroups((int) regs->regs[base + 5], - (gid_t *) regs->regs[base + 6]); + (gid_t __user *) regs->regs[base + 6]); break; case SGI_GETGROUPS: retval = sys_getgroups((int) regs->regs[base + 5], - (gid_t *) regs->regs[base + 6]); + (gid_t __user *) regs->regs[base + 6]); break; case SGI_RUSAGE: { - struct rusage *ru = (struct rusage *) regs->regs[base + 6]; + struct rusage __user *ru = (struct rusage __user *) regs->regs[base + 6]; switch((int) regs->regs[base + 5]) { case 0: @@ -453,7 +437,7 @@ case SGI_ELFMAP: retval = irix_mapelf((int) regs->regs[base + 5], - (struct elf_phdr *) regs->regs[base + 6], + (struct elf_phdr __user *) regs->regs[base + 6], (int) regs->regs[base + 7]); break; @@ -468,24 +452,24 @@ case SGI_PHYSP: { unsigned long addr = regs->regs[base + 5]; - int *pageno = (int *) (regs->regs[base + 6]); + int __user *pageno = (int __user *) (regs->regs[base + 6]); struct mm_struct *mm = current->mm; pgd_t *pgdp; + pud_t *pudp; pmd_t *pmdp; pte_t *ptep; - if (!access_ok(VERIFY_WRITE, pageno, sizeof(int))) - return -EFAULT; - down_read(&mm->mmap_sem); pgdp = pgd_offset(mm, addr); - pmdp = pmd_offset(pgdp, addr); + pudp = pud_offset(pgdp, addr); + pmdp = pmd_offset(pudp, addr); ptep = pte_offset(pmdp, addr); retval = -EINVAL; if (ptep) { pte_t pte = *ptep; if (pte_val(pte) & (_PAGE_VALID | _PAGE_PRESENT)) { + /* b0rked on 64-bit */ retval = put_user((pte_val(pte) & PAGE_MASK) >> PAGE_SHIFT, pageno); } @@ -496,7 +480,7 @@ case SGI_INVENT: { int arg1 = (int) regs->regs [base + 5]; - void *buffer = (void *) regs->regs [base + 6]; + void __user *buffer = (void __user *) regs->regs [base + 6]; int count = (int) regs->regs [base + 7]; switch (arg1) { @@ -700,8 +684,8 @@ } /* XXX need more than this... */ -asmlinkage int irix_mount(char *dev_name, char *dir_name, unsigned long flags, - char *type, void *data, int datalen) +asmlinkage int irix_mount(char __user *dev_name, char __user *dir_name, + unsigned long flags, char __user *type, void __user *data, int datalen) { printk("[%s:%d] irix_mount(%p,%p,%08lx,%p,%p,%d)\n", current->comm, current->pid, @@ -716,8 +700,8 @@ char f_fname[6], f_fpack[6]; }; -asmlinkage int irix_statfs(const char *path, struct irix_statfs *buf, - int len, int fs_type) +asmlinkage int irix_statfs(const char __user *path, + struct irix_statfs __user *buf, int len, int fs_type) { struct nameidata nd; struct kstatfs kbuf; @@ -732,6 +716,7 @@ error = -EFAULT; goto out; } + error = user_path_walk(path, &nd); if (error) goto out; @@ -740,18 +725,17 @@ if (error) goto dput_and_out; - __put_user(kbuf.f_type, &buf->f_type); - __put_user(kbuf.f_bsize, &buf->f_bsize); - __put_user(kbuf.f_frsize, &buf->f_frsize); - __put_user(kbuf.f_blocks, &buf->f_blocks); - __put_user(kbuf.f_bfree, &buf->f_bfree); - __put_user(kbuf.f_files, &buf->f_files); - __put_user(kbuf.f_ffree, &buf->f_ffree); + error = __put_user(kbuf.f_type, &buf->f_type); + error |= __put_user(kbuf.f_bsize, &buf->f_bsize); + error |= __put_user(kbuf.f_frsize, &buf->f_frsize); + error |= __put_user(kbuf.f_blocks, &buf->f_blocks); + error |= __put_user(kbuf.f_bfree, &buf->f_bfree); + error |= __put_user(kbuf.f_files, &buf->f_files); + error |= __put_user(kbuf.f_ffree, &buf->f_ffree); for (i = 0; i < 6; i++) { - __put_user(0, &buf->f_fname[i]); - __put_user(0, &buf->f_fpack[i]); + error |= __put_user(0, &buf->f_fname[i]); + error |= __put_user(0, &buf->f_fpack[i]); } - error = 0; dput_and_out: path_release(&nd); @@ -759,7 +743,7 @@ return error; } -asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs *buf) +asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs __user *buf) { struct kstatfs kbuf; struct file *file; @@ -769,6 +753,7 @@ error = -EFAULT; goto out; } + if (!(file = fget(fd))) { error = -EBADF; goto out; @@ -778,16 +763,17 @@ if (error) goto out_f; - __put_user(kbuf.f_type, &buf->f_type); - __put_user(kbuf.f_bsize, &buf->f_bsize); - __put_user(kbuf.f_frsize, &buf->f_frsize); - __put_user(kbuf.f_blocks, &buf->f_blocks); - __put_user(kbuf.f_bfree, &buf->f_bfree); - __put_user(kbuf.f_files, &buf->f_files); - __put_user(kbuf.f_ffree, &buf->f_ffree); - for(i = 0; i < 6; i++) { - __put_user(0, &buf->f_fname[i]); - __put_user(0, &buf->f_fpack[i]); + error = __put_user(kbuf.f_type, &buf->f_type); + error |= __put_user(kbuf.f_bsize, &buf->f_bsize); + error |= __put_user(kbuf.f_frsize, &buf->f_frsize); + error |= __put_user(kbuf.f_blocks, &buf->f_blocks); + error |= __put_user(kbuf.f_bfree, &buf->f_bfree); + error |= __put_user(kbuf.f_files, &buf->f_files); + error |= __put_user(kbuf.f_ffree, &buf->f_ffree); + + for (i = 0; i < 6; i++) { + error |= __put_user(0, &buf->f_fname[i]); + error |= __put_user(0, &buf->f_fpack[i]); } out_f: @@ -814,14 +800,15 @@ return error; } -asmlinkage int irix_times(struct tms * tbuf) +asmlinkage int irix_times(struct tms __user *tbuf) { int err = 0; if (tbuf) { if (!access_ok(VERIFY_WRITE,tbuf,sizeof *tbuf)) return -EFAULT; - err |= __put_user(current->utime, &tbuf->tms_utime); + + err = __put_user(current->utime, &tbuf->tms_utime); err |= __put_user(current->stime, &tbuf->tms_stime); err |= __put_user(current->signal->cutime, &tbuf->tms_cutime); err |= __put_user(current->signal->cstime, &tbuf->tms_cstime); @@ -837,13 +824,13 @@ if(regs->regs[2] == 1000) base = 1; - filename = getname((char *) (long)regs->regs[base + 4]); + filename = getname((char __user *) (long)regs->regs[base + 4]); error = PTR_ERR(filename); if (IS_ERR(filename)) return error; - error = do_execve(filename, (char **) (long)regs->regs[base + 5], - (char **) 0, regs); + error = do_execve(filename, (char __user * __user *) (long)regs->regs[base + 5], + NULL, regs); putname(filename); return error; @@ -856,12 +843,12 @@ if (regs->regs[2] == 1000) base = 1; - filename = getname((char *) (long)regs->regs[base + 4]); + filename = getname((char __user *) (long)regs->regs[base + 4]); error = PTR_ERR(filename); if (IS_ERR(filename)) return error; - error = do_execve(filename, (char **) (long)regs->regs[base + 5], - (char **) (long)regs->regs[base + 6], regs); + error = do_execve(filename, (char __user * __user *) (long)regs->regs[base + 5], + (char __user * __user *) (long)regs->regs[base + 6], regs); putname(filename); return error; @@ -917,22 +904,17 @@ return sys_socket(family, type, protocol); } -asmlinkage int irix_getdomainname(char *name, int len) +asmlinkage int irix_getdomainname(char __user *name, int len) { - int error; - - if (!access_ok(VERIFY_WRITE, name, len)) - return -EFAULT; + int err; down_read(&uts_sem); if (len > __NEW_UTS_LEN) len = __NEW_UTS_LEN; - error = 0; - if (copy_to_user(name, system_utsname.domainname, len)) - error = -EFAULT; + err = copy_to_user(name, system_utsname.domainname, len) ? -EFAULT : 0; up_read(&uts_sem); - return error; + return err; } asmlinkage unsigned long irix_getpagesize(void) @@ -948,12 +930,13 @@ case 0: return sys_msgget((key_t) arg0, (int) arg1); case 1: - return sys_msgctl((int) arg0, (int) arg1, (struct msqid_ds *)arg2); + return sys_msgctl((int) arg0, (int) arg1, + (struct msqid_ds __user *)arg2); case 2: - return sys_msgrcv((int) arg0, (struct msgbuf *) arg1, + return sys_msgrcv((int) arg0, (struct msgbuf __user *) arg1, (size_t) arg2, (long) arg3, (int) arg4); case 3: - return sys_msgsnd((int) arg0, (struct msgbuf *) arg1, + return sys_msgsnd((int) arg0, (struct msgbuf __user *) arg1, (size_t) arg2, (int) arg3); default: return -EINVAL; @@ -965,12 +948,13 @@ { switch (opcode) { case 0: - return do_shmat((int) arg0, (char *)arg1, (int) arg2, + return do_shmat((int) arg0, (char __user *) arg1, (int) arg2, (unsigned long *) arg3); case 1: - return sys_shmctl((int)arg0, (int)arg1, (struct shmid_ds *)arg2); + return sys_shmctl((int)arg0, (int)arg1, + (struct shmid_ds __user *)arg2); case 2: - return sys_shmdt((char *)arg0); + return sys_shmdt((char __user *)arg0); case 3: return sys_shmget((key_t) arg0, (int) arg1, (int) arg2); default: @@ -988,7 +972,7 @@ case 1: return sys_semget((key_t) arg0, (int) arg1, (int) arg2); case 2: - return sys_semop((int) arg0, (struct sembuf *)arg1, + return sys_semop((int) arg0, (struct sembuf __user *)arg1, (unsigned int) arg2); default: return -EINVAL; @@ -1006,15 +990,16 @@ lock_kernel(); retval = fn(file, offset, origin); unlock_kernel(); + return retval; } asmlinkage int irix_lseek64(int fd, int _unused, int offhi, int offlow, int origin) { - int retval; struct file * file; loff_t offset; + int retval; retval = -EBADF; file = fget(fd); @@ -1040,12 +1025,12 @@ return 0; } -asmlinkage int irix_sgikopt(char *istring, char *ostring, int len) +asmlinkage int irix_sgikopt(char __user *istring, char __user *ostring, int len) { return -EINVAL; } -asmlinkage int irix_gettimeofday(struct timeval *tv) +asmlinkage int irix_gettimeofday(struct timeval __user *tv) { time_t sec; long nsec, seq; @@ -1086,7 +1071,7 @@ if (max_size > file->f_dentry->d_inode->i_size) { old_pos = sys_lseek (fd, max_size - 1, 0); - sys_write (fd, "", 1); + sys_write (fd, (void __user *) "", 1); sys_lseek (fd, old_pos, 0); } } @@ -1111,7 +1096,7 @@ return -EINVAL; } -asmlinkage int irix_pagelock(char *addr, int len, int op) +asmlinkage int irix_pagelock(char __user *addr, int len, int op) { printk("[%s:%d] Wheee.. irix_pagelock(%p,%d,%d)\n", current->comm, current->pid, addr, len, op); @@ -1151,7 +1136,7 @@ return error; } -asmlinkage int irix_systeminfo(int cmd, char *buf, int cnt) +asmlinkage int irix_systeminfo(int cmd, char __user *buf, int cnt) { printk("[%s:%d] Wheee.. irix_systeminfo(%d,%p,%d)\n", current->comm, current->pid, cmd, buf, cnt); @@ -1167,14 +1152,14 @@ char _unused3[257], _unused4[257], _unused5[257]; }; -asmlinkage int irix_uname(struct iuname *buf) +asmlinkage int irix_uname(struct iuname __user *buf) { down_read(&uts_sem); - if (copy_to_user(system_utsname.sysname, buf->sysname, 65) - || copy_to_user(system_utsname.nodename, buf->nodename, 65) - || copy_to_user(system_utsname.release, buf->release, 65) - || copy_to_user(system_utsname.version, buf->version, 65) - || copy_to_user(system_utsname.machine, buf->machine, 65)) { + if (copy_from_user(system_utsname.sysname, buf->sysname, 65) + || copy_from_user(system_utsname.nodename, buf->nodename, 65) + || copy_from_user(system_utsname.release, buf->release, 65) + || copy_from_user(system_utsname.version, buf->version, 65) + || copy_from_user(system_utsname.machine, buf->machine, 65)) { return -EFAULT; } up_read(&uts_sem); @@ -1184,7 +1169,7 @@ #undef DEBUG_XSTAT -static int irix_xstat32_xlate(struct kstat *stat, void *ubuf) +static int irix_xstat32_xlate(struct kstat *stat, void __user *ubuf) { struct xstat32 { u32 st_dev, st_pad1[3], st_ino, st_mode, st_nlink, st_uid, st_gid; @@ -1224,7 +1209,7 @@ return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0; } -static int irix_xstat64_xlate(struct kstat *stat, void *ubuf) +static int irix_xstat64_xlate(struct kstat *stat, void __user *ubuf) { struct xstat64 { u32 st_dev; s32 st_pad1[3]; @@ -1274,7 +1259,7 @@ return copy_to_user(ubuf, &ks, sizeof(ks)) ? -EFAULT : 0; } -asmlinkage int irix_xstat(int version, char *filename, struct stat *statbuf) +asmlinkage int irix_xstat(int version, char __user *filename, struct stat __user *statbuf) { int retval; struct kstat stat; @@ -1300,7 +1285,7 @@ return retval; } -asmlinkage int irix_lxstat(int version, char *filename, struct stat *statbuf) +asmlinkage int irix_lxstat(int version, char __user *filename, struct stat __user *statbuf) { int error; struct kstat stat; @@ -1327,7 +1312,7 @@ return error; } -asmlinkage int irix_fxstat(int version, int fd, struct stat *statbuf) +asmlinkage int irix_fxstat(int version, int fd, struct stat __user *statbuf) { int error; struct kstat stat; @@ -1353,7 +1338,7 @@ return error; } -asmlinkage int irix_xmknod(int ver, char *filename, int mode, unsigned dev) +asmlinkage int irix_xmknod(int ver, char __user *filename, int mode, unsigned dev) { int retval; printk("[%s:%d] Wheee.. irix_xmknod(%d,%s,%x,%x)\n", @@ -1373,7 +1358,7 @@ return retval; } -asmlinkage int irix_swapctl(int cmd, char *arg) +asmlinkage int irix_swapctl(int cmd, char __user *arg) { printk("[%s:%d] Wheee.. irix_swapctl(%d,%p)\n", current->comm, current->pid, cmd, arg); @@ -1389,7 +1374,7 @@ char f_fstr[32]; u32 f_filler[16]; }; -asmlinkage int irix_statvfs(char *fname, struct irix_statvfs *buf) +asmlinkage int irix_statvfs(char __user *fname, struct irix_statvfs __user *buf) { struct nameidata nd; struct kstatfs kbuf; @@ -1397,10 +1382,9 @@ printk("[%s:%d] Wheee.. irix_statvfs(%s,%p)\n", current->comm, current->pid, fname, buf); - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) { - error = -EFAULT; - goto out; - } + if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) + return -EFAULT; + error = user_path_walk(fname, &nd); if (error) goto out; @@ -1408,27 +1392,25 @@ if (error) goto dput_and_out; - __put_user(kbuf.f_bsize, &buf->f_bsize); - __put_user(kbuf.f_frsize, &buf->f_frsize); - __put_user(kbuf.f_blocks, &buf->f_blocks); - __put_user(kbuf.f_bfree, &buf->f_bfree); - __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - __put_user(kbuf.f_files, &buf->f_files); - __put_user(kbuf.f_ffree, &buf->f_ffree); - __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ + error |= __put_user(kbuf.f_bsize, &buf->f_bsize); + error |= __put_user(kbuf.f_frsize, &buf->f_frsize); + error |= __put_user(kbuf.f_blocks, &buf->f_blocks); + error |= __put_user(kbuf.f_bfree, &buf->f_bfree); + error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ + error |= __put_user(kbuf.f_files, &buf->f_files); + error |= __put_user(kbuf.f_ffree, &buf->f_ffree); + error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ #ifdef __MIPSEB__ - __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); #else - __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); #endif for (i = 0; i < 16; i++) - __put_user(0, &buf->f_basetype[i]); - __put_user(0, &buf->f_flag); - __put_user(kbuf.f_namelen, &buf->f_namemax); + error |= __put_user(0, &buf->f_basetype[i]); + error |= __put_user(0, &buf->f_flag); + error |= __put_user(kbuf.f_namelen, &buf->f_namemax); for (i = 0; i < 32; i++) - __put_user(0, &buf->f_fstr[i]); - - error = 0; + error |= __put_user(0, &buf->f_fstr[i]); dput_and_out: path_release(&nd); @@ -1436,7 +1418,7 @@ return error; } -asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs *buf) +asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs __user *buf) { struct kstatfs kbuf; struct file *file; @@ -1445,10 +1427,9 @@ printk("[%s:%d] Wheee.. irix_fstatvfs(%d,%p)\n", current->comm, current->pid, fd, buf); - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) { - error = -EFAULT; - goto out; - } + if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) + return -EFAULT; + if (!(file = fget(fd))) { error = -EBADF; goto out; @@ -1457,24 +1438,24 @@ if (error) goto out_f; - __put_user(kbuf.f_bsize, &buf->f_bsize); - __put_user(kbuf.f_frsize, &buf->f_frsize); - __put_user(kbuf.f_blocks, &buf->f_blocks); - __put_user(kbuf.f_bfree, &buf->f_bfree); - __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - __put_user(kbuf.f_files, &buf->f_files); - __put_user(kbuf.f_ffree, &buf->f_ffree); - __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ + error = __put_user(kbuf.f_bsize, &buf->f_bsize); + error |= __put_user(kbuf.f_frsize, &buf->f_frsize); + error |= __put_user(kbuf.f_blocks, &buf->f_blocks); + error |= __put_user(kbuf.f_bfree, &buf->f_bfree); + error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ + error |= __put_user(kbuf.f_files, &buf->f_files); + error |= __put_user(kbuf.f_ffree, &buf->f_ffree); + error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ #ifdef __MIPSEB__ - __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); #else - __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); #endif for(i = 0; i < 16; i++) - __put_user(0, &buf->f_basetype[i]); - __put_user(0, &buf->f_flag); - __put_user(kbuf.f_namelen, &buf->f_namemax); - __clear_user(&buf->f_fstr, sizeof(buf->f_fstr)); + error |= __put_user(0, &buf->f_basetype[i]); + error |= __put_user(0, &buf->f_flag); + error |= __put_user(kbuf.f_namelen, &buf->f_namemax); + error |= __clear_user(&buf->f_fstr, sizeof(buf->f_fstr)) ? -EFAULT : 0; out_f: fput(file); @@ -1498,7 +1479,7 @@ return -EINVAL; } -asmlinkage int irix_truncate64(char *name, int pad, int size1, int size2) +asmlinkage int irix_truncate64(char __user *name, int pad, int size1, int size2) { int retval; @@ -1531,6 +1512,7 @@ int len, prot, flags, fd, off1, off2, error, base = 0; unsigned long addr, pgoff, *sp; struct file *file = NULL; + int err; if (regs->regs[2] == 1000) base = 1; @@ -1540,36 +1522,31 @@ prot = regs->regs[base + 6]; if (!base) { flags = regs->regs[base + 7]; - if (!access_ok(VERIFY_READ, sp, (4 * sizeof(unsigned long)))) { - error = -EFAULT; - goto out; - } + if (!access_ok(VERIFY_READ, sp, (4 * sizeof(unsigned long)))) + return -EFAULT; fd = sp[0]; - __get_user(off1, &sp[1]); - __get_user(off2, &sp[2]); + err = __get_user(off1, &sp[1]); + err |= __get_user(off2, &sp[2]); } else { - if (!access_ok(VERIFY_READ, sp, (5 * sizeof(unsigned long)))) { - error = -EFAULT; - goto out; - } - __get_user(flags, &sp[0]); - __get_user(fd, &sp[1]); - __get_user(off1, &sp[2]); - __get_user(off2, &sp[3]); + if (!access_ok(VERIFY_READ, sp, (5 * sizeof(unsigned long)))) + return -EFAULT; + err = __get_user(flags, &sp[0]); + err |= __get_user(fd, &sp[1]); + err |= __get_user(off1, &sp[2]); + err |= __get_user(off2, &sp[3]); } - if (off1 & PAGE_MASK) { - error = -EOVERFLOW; - goto out; - } + if (err) + return err; + + if (off1 & PAGE_MASK) + return -EOVERFLOW; pgoff = (off1 << (32 - PAGE_SHIFT)) | (off2 >> PAGE_SHIFT); if (!(flags & MAP_ANONYMOUS)) { - if (!(file = fget(fd))) { - error = -EBADF; - goto out; - } + if (!(file = fget(fd))) + return -EBADF; /* Ok, bad taste hack follows, try to think in something else when reading this */ @@ -1579,7 +1556,7 @@ if (max_size > file->f_dentry->d_inode->i_size) { old_pos = sys_lseek (fd, max_size - 1, 0); - sys_write (fd, "", 1); + sys_write (fd, (void __user *) "", 1); sys_lseek (fd, old_pos, 0); } } @@ -1594,7 +1571,6 @@ if (file) fput(file); -out: return error; } @@ -1606,7 +1582,7 @@ return -EINVAL; } -asmlinkage int irix_pread(int fd, char *buf, int cnt, int off64, +asmlinkage int irix_pread(int fd, char __user *buf, int cnt, int off64, int off1, int off2) { printk("[%s:%d] Wheee.. irix_pread(%d,%p,%d,%d,%d,%d)\n", @@ -1615,7 +1591,7 @@ return -EINVAL; } -asmlinkage int irix_pwrite(int fd, char *buf, int cnt, int off64, +asmlinkage int irix_pwrite(int fd, char __user *buf, int cnt, int off64, int off1, int off2) { printk("[%s:%d] Wheee.. irix_pwrite(%d,%p,%d,%d,%d,%d)\n", @@ -1647,7 +1623,7 @@ u32 f_filler[16]; }; -asmlinkage int irix_statvfs64(char *fname, struct irix_statvfs64 *buf) +asmlinkage int irix_statvfs64(char __user *fname, struct irix_statvfs64 __user *buf) { struct nameidata nd; struct kstatfs kbuf; @@ -1659,6 +1635,7 @@ error = -EFAULT; goto out; } + error = user_path_walk(fname, &nd); if (error) goto out; @@ -1666,27 +1643,25 @@ if (error) goto dput_and_out; - __put_user(kbuf.f_bsize, &buf->f_bsize); - __put_user(kbuf.f_frsize, &buf->f_frsize); - __put_user(kbuf.f_blocks, &buf->f_blocks); - __put_user(kbuf.f_bfree, &buf->f_bfree); - __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - __put_user(kbuf.f_files, &buf->f_files); - __put_user(kbuf.f_ffree, &buf->f_ffree); - __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ + error = __put_user(kbuf.f_bsize, &buf->f_bsize); + error |= __put_user(kbuf.f_frsize, &buf->f_frsize); + error |= __put_user(kbuf.f_blocks, &buf->f_blocks); + error |= __put_user(kbuf.f_bfree, &buf->f_bfree); + error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ + error |= __put_user(kbuf.f_files, &buf->f_files); + error |= __put_user(kbuf.f_ffree, &buf->f_ffree); + error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ #ifdef __MIPSEB__ - __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); #else - __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); #endif for(i = 0; i < 16; i++) - __put_user(0, &buf->f_basetype[i]); - __put_user(0, &buf->f_flag); - __put_user(kbuf.f_namelen, &buf->f_namemax); + error |= __put_user(0, &buf->f_basetype[i]); + error |= __put_user(0, &buf->f_flag); + error |= __put_user(kbuf.f_namelen, &buf->f_namemax); for(i = 0; i < 32; i++) - __put_user(0, &buf->f_fstr[i]); - - error = 0; + error |= __put_user(0, &buf->f_fstr[i]); dput_and_out: path_release(&nd); @@ -1694,7 +1669,7 @@ return error; } -asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs *buf) +asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs __user *buf) { struct kstatfs kbuf; struct file *file; @@ -1715,24 +1690,24 @@ if (error) goto out_f; - __put_user(kbuf.f_bsize, &buf->f_bsize); - __put_user(kbuf.f_frsize, &buf->f_frsize); - __put_user(kbuf.f_blocks, &buf->f_blocks); - __put_user(kbuf.f_bfree, &buf->f_bfree); - __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - __put_user(kbuf.f_files, &buf->f_files); - __put_user(kbuf.f_ffree, &buf->f_ffree); - __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ + error = __put_user(kbuf.f_bsize, &buf->f_bsize); + error |= __put_user(kbuf.f_frsize, &buf->f_frsize); + error |= __put_user(kbuf.f_blocks, &buf->f_blocks); + error |= __put_user(kbuf.f_bfree, &buf->f_bfree); + error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ + error |= __put_user(kbuf.f_files, &buf->f_files); + error |= __put_user(kbuf.f_ffree, &buf->f_ffree); + error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ #ifdef __MIPSEB__ - __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); #else - __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); + error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); #endif for(i = 0; i < 16; i++) - __put_user(0, &buf->f_basetype[i]); - __put_user(0, &buf->f_flag); - __put_user(kbuf.f_namelen, &buf->f_namemax); - __clear_user(buf->f_fstr, sizeof(buf->f_fstr[i])); + error |= __put_user(0, &buf->f_basetype[i]); + error |= __put_user(0, &buf->f_flag); + error |= __put_user(kbuf.f_namelen, &buf->f_namemax); + error |= __clear_user(buf->f_fstr, sizeof(buf->f_fstr[i])) ? -EFAULT : 0; out_f: fput(file); @@ -1740,9 +1715,9 @@ return error; } -asmlinkage int irix_getmountid(char *fname, unsigned long *midbuf) +asmlinkage int irix_getmountid(char __user *fname, unsigned long __user *midbuf) { - int err = 0; + int err; printk("[%s:%d] irix_getmountid(%s, %p)\n", current->comm, current->pid, fname, midbuf); @@ -1755,7 +1730,7 @@ * fsid of the filesystem to try and make the right decision, but * we don't have this so for now. XXX */ - err |= __put_user(0, &midbuf[0]); + err = __put_user(0, &midbuf[0]); err |= __put_user(0, &midbuf[1]); err |= __put_user(0, &midbuf[2]); err |= __put_user(0, &midbuf[3]); @@ -1782,8 +1757,8 @@ }; struct irix_dirent32_callback { - struct irix_dirent32 *current_dir; - struct irix_dirent32 *previous; + struct irix_dirent32 __user *current_dir; + struct irix_dirent32 __user *previous; int count; int error; }; @@ -1791,13 +1766,13 @@ #define NAME_OFFSET32(de) ((int) ((de)->d_name - (char *) (de))) #define ROUND_UP32(x) (((x)+sizeof(u32)-1) & ~(sizeof(u32)-1)) -static int irix_filldir32(void *__buf, const char *name, int namlen, - loff_t offset, ino_t ino, unsigned int d_type) +static int irix_filldir32(void *__buf, const char *name, + int namlen, loff_t offset, ino_t ino, unsigned int d_type) { - struct irix_dirent32 *dirent; - struct irix_dirent32_callback *buf = - (struct irix_dirent32_callback *)__buf; + struct irix_dirent32 __user *dirent; + struct irix_dirent32_callback *buf = __buf; unsigned short reclen = ROUND_UP32(NAME_OFFSET32(dirent) + namlen + 1); + int err = 0; #ifdef DEBUG_GETDENTS printk("\nirix_filldir32[reclen<%d>namlen<%d>count<%d>]", @@ -1808,25 +1783,26 @@ return -EINVAL; dirent = buf->previous; if (dirent) - __put_user(offset, &dirent->d_off); + err = __put_user(offset, &dirent->d_off); dirent = buf->current_dir; - buf->previous = dirent; - __put_user(ino, &dirent->d_ino); - __put_user(reclen, &dirent->d_reclen); - copy_to_user(dirent->d_name, name, namlen); - __put_user(0, &dirent->d_name[namlen]); - ((char *) dirent) += reclen; + err |= __put_user(dirent, &buf->previous); + err |= __put_user(ino, &dirent->d_ino); + err |= __put_user(reclen, &dirent->d_reclen); + err |= copy_to_user((char __user *)dirent->d_name, name, namlen) ? -EFAULT : 0; + err |= __put_user(0, &dirent->d_name[namlen]); + dirent = (struct irix_dirent32 __user *) ((char __user *) dirent + reclen); + buf->current_dir = dirent; buf->count -= reclen; - return 0; + return err; } -asmlinkage int irix_ngetdents(unsigned int fd, void * dirent, - unsigned int count, int *eob) +asmlinkage int irix_ngetdents(unsigned int fd, void __user * dirent, + unsigned int count, int __user *eob) { struct file *file; - struct irix_dirent32 *lastdirent; + struct irix_dirent32 __user *lastdirent; struct irix_dirent32_callback buf; int error; @@ -1839,7 +1815,7 @@ if (!file) goto out; - buf.current_dir = (struct irix_dirent32 *) dirent; + buf.current_dir = (struct irix_dirent32 __user *) dirent; buf.previous = NULL; buf.count = count; buf.error = 0; @@ -1879,8 +1855,8 @@ }; struct irix_dirent64_callback { - struct irix_dirent64 *curr; - struct irix_dirent64 *previous; + struct irix_dirent64 __user *curr; + struct irix_dirent64 __user *previous; int count; int error; }; @@ -1888,37 +1864,44 @@ #define NAME_OFFSET64(de) ((int) ((de)->d_name - (char *) (de))) #define ROUND_UP64(x) (((x)+sizeof(u64)-1) & ~(sizeof(u64)-1)) -static int irix_filldir64(void * __buf, const char * name, int namlen, - loff_t offset, ino_t ino, unsigned int d_type) +static int irix_filldir64(void *__buf, const char *name, + int namlen, loff_t offset, ino_t ino, unsigned int d_type) { - struct irix_dirent64 *dirent; - struct irix_dirent64_callback * buf = - (struct irix_dirent64_callback *) __buf; + struct irix_dirent64 __user *dirent; + struct irix_dirent64_callback * buf = __buf; unsigned short reclen = ROUND_UP64(NAME_OFFSET64(dirent) + namlen + 1); + int err = 0; - buf->error = -EINVAL; /* only used if we fail.. */ + if (!access_ok(VERIFY_WRITE, buf, sizeof(*buf))) + return -EFAULT; + + if (__put_user(-EINVAL, &buf->error)) /* only used if we fail.. */ + return -EFAULT; if (reclen > buf->count) return -EINVAL; dirent = buf->previous; if (dirent) - __put_user(offset, &dirent->d_off); + err = __put_user(offset, &dirent->d_off); dirent = buf->curr; buf->previous = dirent; - __put_user(ino, &dirent->d_ino); - __put_user(reclen, &dirent->d_reclen); - __copy_to_user(dirent->d_name, name, namlen); - __put_user(0, &dirent->d_name[namlen]); - ((char *) dirent) += reclen; + err |= __put_user(ino, &dirent->d_ino); + err |= __put_user(reclen, &dirent->d_reclen); + err |= __copy_to_user((char __user *)dirent->d_name, name, namlen) + ? -EFAULT : 0; + err |= __put_user(0, &dirent->d_name[namlen]); + + dirent = (struct irix_dirent64 __user *) ((char __user *) dirent + reclen); + buf->curr = dirent; buf->count -= reclen; - return 0; + return err; } -asmlinkage int irix_getdents64(int fd, void *dirent, int cnt) +asmlinkage int irix_getdents64(int fd, void __user *dirent, int cnt) { struct file *file; - struct irix_dirent64 *lastdirent; + struct irix_dirent64 __user *lastdirent; struct irix_dirent64_callback buf; int error; @@ -1938,7 +1921,7 @@ if (cnt < (sizeof(struct irix_dirent64) + 255)) goto out_f; - buf.curr = (struct irix_dirent64 *) dirent; + buf.curr = (struct irix_dirent64 __user *) dirent; buf.previous = NULL; buf.count = cnt; buf.error = 0; @@ -1950,7 +1933,8 @@ error = buf.error; goto out_f; } - lastdirent->d_off = (u64) file->f_pos; + if (put_user(file->f_pos, &lastdirent->d_off)) + return -EFAULT; #ifdef DEBUG_GETDENTS printk("returning %d\n", cnt - buf.count); #endif @@ -1962,10 +1946,10 @@ return error; } -asmlinkage int irix_ngetdents64(int fd, void *dirent, int cnt, int *eob) +asmlinkage int irix_ngetdents64(int fd, void __user *dirent, int cnt, int *eob) { struct file *file; - struct irix_dirent64 *lastdirent; + struct irix_dirent64 __user *lastdirent; struct irix_dirent64_callback buf; int error; @@ -1987,7 +1971,7 @@ goto out_f; *eob = 0; - buf.curr = (struct irix_dirent64 *) dirent; + buf.curr = (struct irix_dirent64 __user *) dirent; buf.previous = NULL; buf.count = cnt; buf.error = 0; @@ -1999,7 +1983,8 @@ error = buf.error; goto out_f; } - lastdirent->d_off = (u64) file->f_pos; + if (put_user(file->f_pos, &lastdirent->d_off)) + return -EFAULT; #ifdef DEBUG_GETDENTS printk("eob=%d returning %d\n", *eob, cnt - buf.count); #endif @@ -2062,14 +2047,14 @@ return retval; } -asmlinkage int irix_utssys(char *inbuf, int arg, int type, char *outbuf) +asmlinkage int irix_utssys(char __user *inbuf, int arg, int type, char __user *outbuf) { int retval; switch(type) { case 0: /* uname() */ - retval = irix_uname((struct iuname *)inbuf); + retval = irix_uname((struct iuname __user *)inbuf); goto out; case 2: diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/traps.c linux-2.6.12.6/arch/mips/kernel/traps.c --- linux-2.6.12.6.orig/arch/mips/kernel/traps.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/traps.c 2005-10-02 23:47:37.000000000 +0000 @@ -9,7 +9,7 @@ * Copyright (C) 1999 Silicon Graphics, Inc. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000, 01 MIPS Technologies, Inc. - * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki */ #include #include @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -54,6 +55,7 @@ extern asmlinkage void handle_fpe(void); extern asmlinkage void handle_mdmx(void); extern asmlinkage void handle_watch(void); +extern asmlinkage void handle_dsp(void); extern asmlinkage void handle_mcheck(void); extern asmlinkage void handle_reserved(void); @@ -201,32 +203,47 @@ printk("Status: %08x ", (uint32_t) regs->cp0_status); - if (regs->cp0_status & ST0_KX) - printk("KX "); - if (regs->cp0_status & ST0_SX) - printk("SX "); - if (regs->cp0_status & ST0_UX) - printk("UX "); - switch (regs->cp0_status & ST0_KSU) { - case KSU_USER: - printk("USER "); - break; - case KSU_SUPERVISOR: - printk("SUPERVISOR "); - break; - case KSU_KERNEL: - printk("KERNEL "); - break; - default: - printk("BAD_MODE "); - break; + if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { + if (regs->cp0_status & ST0_KUO) + printk("KUo "); + if (regs->cp0_status & ST0_IEO) + printk("IEo "); + if (regs->cp0_status & ST0_KUP) + printk("KUp "); + if (regs->cp0_status & ST0_IEP) + printk("IEp "); + if (regs->cp0_status & ST0_KUC) + printk("KUc "); + if (regs->cp0_status & ST0_IEC) + printk("IEc "); + } else { + if (regs->cp0_status & ST0_KX) + printk("KX "); + if (regs->cp0_status & ST0_SX) + printk("SX "); + if (regs->cp0_status & ST0_UX) + printk("UX "); + switch (regs->cp0_status & ST0_KSU) { + case KSU_USER: + printk("USER "); + break; + case KSU_SUPERVISOR: + printk("SUPERVISOR "); + break; + case KSU_KERNEL: + printk("KERNEL "); + break; + default: + printk("BAD_MODE "); + break; + } + if (regs->cp0_status & ST0_ERL) + printk("ERL "); + if (regs->cp0_status & ST0_EXL) + printk("EXL "); + if (regs->cp0_status & ST0_IE) + printk("IE "); } - if (regs->cp0_status & ST0_ERL) - printk("ERL "); - if (regs->cp0_status & ST0_EXL) - printk("EXL "); - if (regs->cp0_status & ST0_IE) - printk("IE "); printk("\n"); printk("Cause : %08x\n", cause); @@ -252,8 +269,9 @@ static DEFINE_SPINLOCK(die_lock); -NORET_TYPE void __die(const char * str, struct pt_regs * regs, - const char * file, const char * func, unsigned long line) +NORET_TYPE void ATTRIB_NORET __die(const char * str, struct pt_regs * regs, + const char * file, const char * func, + unsigned long line) { static int die_counter; @@ -339,9 +357,9 @@ static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode) { - unsigned int *epc; + unsigned int __user *epc; - epc = (unsigned int *) regs->cp0_epc + + epc = (unsigned int __user *) regs->cp0_epc + ((regs->cp0_cause & CAUSEF_BD) != 0); if (!get_user(*opcode, epc)) return 0; @@ -360,6 +378,10 @@ #define OFFSET 0x0000ffff #define LL 0xc0000000 #define SC 0xe0000000 +#define SPEC3 0x7c000000 +#define RD 0x0000f800 +#define FUNC 0x0000003f +#define RDHWR 0x0000003b /* * The ll_bit is cleared by r*_switch.S @@ -371,7 +393,7 @@ static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) { - unsigned long value, *vaddr; + unsigned long value, __user *vaddr; long offset; int signal = 0; @@ -385,7 +407,8 @@ offset <<= 16; offset >>= 16; - vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset); + vaddr = (unsigned long __user *) + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); if ((unsigned long)vaddr & 3) { signal = SIGBUS; @@ -407,9 +430,10 @@ preempt_enable(); + compute_return_epc(regs); + regs->regs[(opcode & RT) >> 16] = value; - compute_return_epc(regs); return; sig: @@ -418,7 +442,8 @@ static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) { - unsigned long *vaddr, reg; + unsigned long __user *vaddr; + unsigned long reg; long offset; int signal = 0; @@ -432,7 +457,8 @@ offset <<= 16; offset >>= 16; - vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset); + vaddr = (unsigned long __user *) + ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); reg = (opcode & RT) >> 16; if ((unsigned long)vaddr & 3) { @@ -443,9 +469,9 @@ preempt_disable(); if (ll_bit == 0 || ll_task != current) { + compute_return_epc(regs); regs->regs[reg] = 0; preempt_enable(); - compute_return_epc(regs); return; } @@ -456,9 +482,9 @@ goto sig; } + compute_return_epc(regs); regs->regs[reg] = 1; - compute_return_epc(regs); return; sig: @@ -491,6 +517,37 @@ return -EFAULT; /* Strange things going on ... */ } +/* + * Simulate trapping 'rdhwr' instructions to provide user accessible + * registers not implemented in hardware. The only current use of this + * is the thread area pointer. + */ +static inline int simulate_rdhwr(struct pt_regs *regs) +{ + struct thread_info *ti = current->thread_info; + unsigned int opcode; + + if (unlikely(get_insn_opcode(regs, &opcode))) + return -EFAULT; + + if (unlikely(compute_return_epc(regs))) + return -EFAULT; + + if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { + int rd = (opcode & RD) >> 11; + int rt = (opcode & RT) >> 16; + switch (rd) { + case 29: + regs->regs[rt] = ti->tp_value; + break; + default: + return -EFAULT; + } + } + + return 0; +} + asmlinkage void do_ov(struct pt_regs *regs) { siginfo_t info; @@ -498,7 +555,7 @@ info.si_code = FPE_INTOVF; info.si_signo = SIGFPE; info.si_errno = 0; - info.si_addr = (void *)regs->cp0_epc; + info.si_addr = (void __user *) regs->cp0_epc; force_sig_info(SIGFPE, &info, current); } @@ -512,6 +569,14 @@ preempt_disable(); +#ifdef CONFIG_PREEMPT + if (!is_fpu_owner()) { + /* We might lose fpu before disabling preempt... */ + own_fpu(); + BUG_ON(!used_math()); + restore_fp(current); + } +#endif /* * Unimplemented operation exception. If we've got the full * software emulator on-board, let's use it... @@ -523,11 +588,18 @@ * a bit extreme for what should be an infrequent event. */ save_fp(current); + /* Ensure 'resume' not overwrite saved fp context again. */ + lose_fpu(); + + preempt_enable(); /* Run the emulator */ sig = fpu_emulator_cop1Handler (0, regs, ¤t->thread.fpu.soft); + preempt_disable(); + + own_fpu(); /* Using the FPU again. */ /* * We can't allow the emulated instruction to leave any of * the cause bit set in $fcr31. @@ -584,7 +656,7 @@ info.si_code = FPE_INTOVF; info.si_signo = SIGFPE; info.si_errno = 0; - info.si_addr = (void *)regs->cp0_epc; + info.si_addr = (void __user *) regs->cp0_epc; force_sig_info(SIGFPE, &info, current); break; default: @@ -621,7 +693,7 @@ info.si_code = FPE_INTOVF; info.si_signo = SIGFPE; info.si_errno = 0; - info.si_addr = (void *)regs->cp0_epc; + info.si_addr = (void __user *) regs->cp0_epc; force_sig_info(SIGFPE, &info, current); break; default: @@ -637,6 +709,9 @@ if (!simulate_llsc(regs)) return; + if (!simulate_rdhwr(regs)) + return; + force_sig(SIGILL, current); } @@ -650,11 +725,13 @@ switch (cpid) { case 0: - if (cpu_has_llsc) - break; + if (!cpu_has_llsc) + if (!simulate_llsc(regs)) + return; - if (!simulate_llsc(regs)) + if (!simulate_rdhwr(regs)) return; + break; case 1: @@ -668,6 +745,8 @@ set_used_math(); } + preempt_enable(); + if (!cpu_has_fpu) { int sig = fpu_emulator_cop1Handler(0, regs, ¤t->thread.fpu.soft); @@ -675,8 +754,6 @@ force_sig(sig, current); } - preempt_enable(); - return; case 2: @@ -716,6 +793,14 @@ (regs->cp0_status & ST0_TS) ? "" : "not "); } +asmlinkage void do_dsp(struct pt_regs *regs) +{ + if (cpu_has_dsp) + panic("Unexpected DSP exception\n"); + + force_sig(SIGILL, current); +} + asmlinkage void do_reserved(struct pt_regs *regs) { /* @@ -736,16 +821,12 @@ { switch (current_cpu_data.cputype) { case CPU_24K: - /* 24K cache parity not currently implemented in FPGA */ - printk(KERN_INFO "Disable cache parity protection for " - "MIPS 24K CPU.\n"); - write_c0_ecc(read_c0_ecc() & ~0x80000000); - break; case CPU_5KC: - /* Set the PE bit (bit 31) in the c0_ecc register. */ - printk(KERN_INFO "Enable cache parity protection for " - "MIPS 5KC/24K CPUs.\n"); - write_c0_ecc(read_c0_ecc() | 0x80000000); + write_c0_ecc(0x80000000); + back_to_back_c0_hazard(); + /* Set the PE bit (bit 31) in the c0_errctl register. */ + printk(KERN_INFO "Cache parity protection %sabled\n", + (read_c0_ecc() & 0x80000000) ? "en" : "dis"); break; case CPU_20KC: case CPU_25KF: @@ -927,11 +1008,15 @@ #ifdef CONFIG_MIPS64 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; #endif - if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) + if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV + || current_cpu_data.cputype == CPU_SB1) status_set |= ST0_XX; - change_c0_status(ST0_CU|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, + change_c0_status(ST0_CU|ST0_MX|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, status_set); + if (cpu_has_dsp) + set_c0_status(ST0_MX); + /* * Some MIPS CPUs have a dedicated interrupt vector which reduces the * interrupt processing overhead. Use it where available. @@ -1023,21 +1108,6 @@ set_except_vector(11, handle_cpu); set_except_vector(12, handle_ov); set_except_vector(13, handle_tr); - set_except_vector(22, handle_mdmx); - - if (cpu_has_fpu && !cpu_has_nofpuex) - set_except_vector(15, handle_fpe); - - if (cpu_has_mcheck) - set_except_vector(24, handle_mcheck); - - if (cpu_has_vce) - /* Special exception: R4[04]00 uses also the divec space. */ - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); - else if (cpu_has_4kex) - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); - else - memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); if (current_cpu_data.cputype == CPU_R6000 || current_cpu_data.cputype == CPU_R6000A) { @@ -1053,6 +1123,25 @@ //set_except_vector(15, handle_ndc); } + if (cpu_has_fpu && !cpu_has_nofpuex) + set_except_vector(15, handle_fpe); + + set_except_vector(22, handle_mdmx); + + if (cpu_has_mcheck) + set_except_vector(24, handle_mcheck); + + if (cpu_has_dsp) + set_except_vector(26, handle_dsp); + + if (cpu_has_vce) + /* Special exception: R4[04]00 uses also the divec space. */ + memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); + else if (cpu_has_4kex) + memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); + else + memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); + signal_init(); #ifdef CONFIG_MIPS32_COMPAT signal32_init(); diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/unaligned.c linux-2.6.12.6/arch/mips/kernel/unaligned.c --- linux-2.6.12.6.orig/arch/mips/kernel/unaligned.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/unaligned.c 2005-10-02 23:47:37.000000000 +0000 @@ -94,7 +94,7 @@ #endif static inline int emulate_load_store_insn(struct pt_regs *regs, - void *addr, unsigned long pc, + void __user *addr, unsigned int __user *pc, unsigned long **regptr, unsigned long *newvalue) { union mips_instruction insn; @@ -107,7 +107,7 @@ /* * This load never faults. */ - __get_user(insn.word, (unsigned int *)pc); + __get_user(insn.word, pc); switch (insn.i_format.opcode) { /* @@ -494,8 +494,8 @@ { unsigned long *regptr, newval; extern int do_dsemulret(struct pt_regs *); + unsigned int __user *pc; mm_segment_t seg; - unsigned long pc; /* * Address errors may be deliberately induced by the FPU emulator to @@ -515,7 +515,7 @@ if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1)) goto sigbus; - pc = exception_epc(regs); + pc = (unsigned int __user *) exception_epc(regs); if ((current->thread.mflags & MF_FIXADE) == 0) goto sigbus; @@ -526,7 +526,7 @@ seg = get_fs(); if (!user_mode(regs)) set_fs(KERNEL_DS); - if (!emulate_load_store_insn(regs, (void *)regs->cp0_badvaddr, pc, + if (!emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc, ®ptr, &newval)) { compute_return_epc(regs); /* diff -Naur linux-2.6.12.6.orig/arch/mips/kernel/vmlinux.lds.S linux-2.6.12.6/arch/mips/kernel/vmlinux.lds.S --- linux-2.6.12.6.orig/arch/mips/kernel/vmlinux.lds.S 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/kernel/vmlinux.lds.S 2005-10-02 23:47:37.000000000 +0000 @@ -54,13 +54,6 @@ *(.data) - /* Align the initial ramdisk image (INITRD) on page boundaries. */ - . = ALIGN(4096); - __rd_start = .; - *(.initrd) - . = ALIGN(4096); - __rd_end = .; - CONSTRUCTORS } _gp = . + 0x8000; @@ -96,12 +89,6 @@ .init.setup : { *(.init.setup) } __setup_end = .; - .early_initcall.init : { - __earlyinitcall_start = .; - *(.initcall.early1.init) - } - __earlyinitcall_end = .; - __initcall_start = .; .initcall.init : { *(.initcall1.init) diff -Naur linux-2.6.12.6.orig/arch/mips/lasat/Kconfig linux-2.6.12.6/arch/mips/lasat/Kconfig --- linux-2.6.12.6.orig/arch/mips/lasat/Kconfig 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/lasat/Kconfig 2005-10-02 23:47:37.000000000 +0000 @@ -0,0 +1,15 @@ +config PICVUE + tristate "PICVUE LCD display driver" + depends on LASAT + +config PICVUE_PROC + tristate "PICVUE LCD display driver /proc interface" + depends on PICVUE + +config DS1603 + bool "DS1603 RTC driver" + depends on LASAT + +config LASAT_SYSCTL + bool "LASAT sysctl interface" + depends on LASAT diff -Naur linux-2.6.12.6.orig/arch/mips/lasat/interrupt.c linux-2.6.12.6/arch/mips/lasat/interrupt.c --- linux-2.6.12.6.orig/arch/mips/lasat/interrupt.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/lasat/interrupt.c 2005-10-02 23:47:37.000000000 +0000 @@ -71,14 +71,13 @@ } static struct hw_interrupt_type lasat_irq_type = { - "Lasat", - startup_lasat_irq, - shutdown_lasat_irq, - enable_lasat_irq, - disable_lasat_irq, - mask_and_ack_lasat_irq, - end_lasat_irq, - NULL + .typename = "Lasat", + .startup = startup_lasat_irq, + .shutdown = shutdown_lasat_irq, + .enable = enable_lasat_irq, + .disable = disable_lasat_irq, + .ack = mask_and_ack_lasat_irq, + .end = end_lasat_irq, }; static inline int ls1bit32(unsigned int x) diff -Naur linux-2.6.12.6.orig/arch/mips/lasat/setup.c linux-2.6.12.6/arch/mips/lasat/setup.c --- linux-2.6.12.6.orig/arch/mips/lasat/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/lasat/setup.c 2005-10-02 23:47:37.000000000 +0000 @@ -155,7 +155,7 @@ } #endif -static int __init lasat_setup(void) +void __init plat_setup(void) { int i; lasat_misc = &lasat_misc_info[mips_machtype]; @@ -185,8 +185,4 @@ change_c0_status(ST0_BEV,0); prom_printf("Lasat specific initialization complete\n"); - - return 0; } - -early_initcall(lasat_setup); diff -Naur linux-2.6.12.6.orig/arch/mips/lib/Makefile linux-2.6.12.6/arch/mips/lib/Makefile --- linux-2.6.12.6.orig/arch/mips/lib/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/lib/Makefile 2005-10-02 23:48:07.000000000 +0000 @@ -3,7 +3,7 @@ # lib-y += csum_partial_copy.o dec_and_lock.o memcpy.o promlib.o \ - strlen_user.o strncpy_user.o strnlen_user.o + strlen_user.o strncpy_user.o strnlen_user.o uncached.o obj-y += iomap.o diff -Naur linux-2.6.12.6.orig/arch/mips/lib/csum_partial_copy.c linux-2.6.12.6/arch/mips/lib/csum_partial_copy.c --- linux-2.6.12.6.orig/arch/mips/lib/csum_partial_copy.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/lib/csum_partial_copy.c 2005-10-02 23:47:37.000000000 +0000 @@ -16,8 +16,8 @@ /* * copy while checksumming, otherwise like csum_partial */ -unsigned int csum_partial_copy_nocheck(const unsigned char *src, unsigned char *dst, - int len, unsigned int sum) +unsigned int csum_partial_copy_nocheck(const unsigned char *src, + unsigned char *dst, int len, unsigned int sum) { /* * It's 2:30 am and I don't feel like doing it real ... @@ -33,8 +33,8 @@ * Copy from userspace and compute checksum. If we catch an exception * then zero the rest of the buffer. */ -unsigned int csum_partial_copy_from_user (const unsigned char *src, unsigned char *dst, - int len, unsigned int sum, int *err_ptr) +unsigned int csum_partial_copy_from_user (const unsigned char *src, + unsigned char *dst, int len, unsigned int sum, int *err_ptr) { int missing; diff -Naur linux-2.6.12.6.orig/arch/mips/lib/uncached.c linux-2.6.12.6/arch/mips/lib/uncached.c --- linux-2.6.12.6.orig/arch/mips/lib/uncached.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/lib/uncached.c 2005-10-02 23:47:37.000000000 +0000 @@ -0,0 +1,36 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005 Thiemo Seufer + */ +#include + +#include + +/* + * FUNC is executed in the uncached segment CKSEG1. This works only if + * both code and stack live in CKSEG0. The stack handling works because + * we don't handle stack arguments or more complex return values, so we + * can avoid to share the same stack area between cached and uncached + * mode. + */ +unsigned long __init run_uncached(void *func) +{ + register unsigned long sp __asm__("$sp"); + register unsigned long ret __asm__("$2"); + unsigned long usp = sp - CAC_BASE + UNCAC_BASE; + unsigned long ufunc = func - CAC_BASE + UNCAC_BASE; + + __asm__ __volatile__ ( + " move $16, $sp\n" + " move $sp, %1\n" + " jalr $ra, %2\n" + " move $sp, $16" + : "=&r" (ret) + : "r" (usp), "r" (ufunc) + : "$16", "$31"); + + return ret; +} diff -Naur linux-2.6.12.6.orig/arch/mips/lib-32/dump_tlb.c linux-2.6.12.6/arch/mips/lib-32/dump_tlb.c --- linux-2.6.12.6.orig/arch/mips/lib-32/dump_tlb.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/lib-32/dump_tlb.c 2005-10-02 23:47:37.000000000 +0000 @@ -32,8 +32,6 @@ case PM_256M: return "256Mb"; #endif } - - return "unknown"; } #define BARRIER() \ @@ -139,6 +137,7 @@ void dump_list_process(struct task_struct *t, void *address) { pgd_t *page_dir, *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte, page; unsigned long addr, val; @@ -162,7 +161,10 @@ pgd = pgd_offset(t->mm, addr); printk("pgd == %08x, ", (unsigned int) pgd); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + printk("pud == %08x, ", (unsigned int) pud); + + pmd = pmd_offset(pud, addr); printk("pmd == %08x, ", (unsigned int) pmd); pte = pte_offset(pmd, addr); @@ -195,13 +197,15 @@ unsigned int vtop(void *address) { pgd_t *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte; unsigned int addr, paddr; addr = (unsigned long) address; pgd = pgd_offset(current->mm, addr); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + pmd = pmd_offset(pud, addr); pte = pte_offset(pmd, addr); paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK; paddr |= (addr & ~PAGE_MASK); diff -Naur linux-2.6.12.6.orig/arch/mips/lib-32/r3k_dump_tlb.c linux-2.6.12.6/arch/mips/lib-32/r3k_dump_tlb.c --- linux-2.6.12.6.orig/arch/mips/lib-32/r3k_dump_tlb.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/lib-32/r3k_dump_tlb.c 2005-10-02 23:47:37.000000000 +0000 @@ -105,6 +105,7 @@ void dump_list_process(struct task_struct *t, void *address) { pgd_t *page_dir, *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte, page; unsigned int addr; @@ -121,7 +122,10 @@ pgd = pgd_offset(t->mm, addr); printk("pgd == %08x, ", (unsigned int) pgd); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + printk("pud == %08x, ", (unsigned int) pud); + + pmd = pmd_offset(pud, addr); printk("pmd == %08x, ", (unsigned int) pmd); pte = pte_offset(pmd, addr); @@ -149,13 +153,15 @@ unsigned int vtop(void *address) { pgd_t *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte; unsigned int addr, paddr; addr = (unsigned long) address; pgd = pgd_offset(current->mm, addr); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + pmd = pmd_offset(pud, addr); pte = pte_offset(pmd, addr); paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK; paddr |= (addr & ~PAGE_MASK); diff -Naur linux-2.6.12.6.orig/arch/mips/lib-64/dump_tlb.c linux-2.6.12.6/arch/mips/lib-64/dump_tlb.c --- linux-2.6.12.6.orig/arch/mips/lib-64/dump_tlb.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/lib-64/dump_tlb.c 2005-10-02 23:47:37.000000000 +0000 @@ -32,8 +32,6 @@ case PM_256M: return "256Mb"; #endif } - - return "unknown"; } #define BARRIER() \ @@ -140,6 +138,7 @@ void dump_list_process(struct task_struct *t, void *address) { pgd_t *page_dir, *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte, page; unsigned long addr, val; @@ -155,7 +154,10 @@ pgd = pgd_offset(t->mm, addr); printk("pgd == %016lx\n", (unsigned long) pgd); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + printk("pud == %016lx\n", (unsigned long) pud); + + pmd = pmd_offset(pud, addr); printk("pmd == %016lx\n", (unsigned long) pmd); pte = pte_offset(pmd, addr); @@ -184,13 +186,15 @@ unsigned int vtop(void *address) { pgd_t *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte; unsigned int addr, paddr; addr = (unsigned long) address; pgd = pgd_offset(current->mm, addr); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + pmd = pmd_offset(pud, addr); pte = pte_offset(pmd, addr); paddr = (CKSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK; paddr |= (addr & ~PAGE_MASK); diff -Naur linux-2.6.12.6.orig/arch/mips/math-emu/cp1emu.c linux-2.6.12.6/arch/mips/math-emu/cp1emu.c --- linux-2.6.12.6.orig/arch/mips/math-emu/cp1emu.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/math-emu/cp1emu.c 2005-10-02 23:47:37.000000000 +0000 @@ -70,7 +70,7 @@ /* Further private data for which no space exists in mips_fpu_soft_struct */ -struct mips_fpu_emulator_private fpuemuprivate; +struct mips_fpu_emulator_stats fpuemustats; /* Control registers */ @@ -79,7 +79,17 @@ /* Convert Mips rounding mode (0..3) to IEEE library modes. */ static const unsigned char ieee_rm[4] = { - IEEE754_RN, IEEE754_RZ, IEEE754_RU, IEEE754_RD + [FPU_CSR_RN] = IEEE754_RN, + [FPU_CSR_RZ] = IEEE754_RZ, + [FPU_CSR_RU] = IEEE754_RU, + [FPU_CSR_RD] = IEEE754_RD, +}; +/* Convert IEEE library modes to Mips rounding mode (0..3). */ +static const unsigned char mips_rm[4] = { + [IEEE754_RN] = FPU_CSR_RN, + [IEEE754_RZ] = FPU_CSR_RZ, + [IEEE754_RD] = FPU_CSR_RD, + [IEEE754_RU] = FPU_CSR_RU, }; #if __mips >= 4 @@ -196,11 +206,11 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) { mips_instruction ir; - vaddr_t emulpc, contpc; + void * emulpc, *contpc; unsigned int cond; if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } @@ -221,41 +231,40 @@ * Linux MIPS branch emulator operates on context, updating the * cp0_epc. */ - emulpc = REG_TO_VA(xcp->cp0_epc + 4); /* Snapshot emulation target */ + emulpc = (void *) (xcp->cp0_epc + 4); /* Snapshot emulation target */ if (__compute_return_epc(xcp)) { #ifdef CP1DBG printk("failed to emulate branch at %p\n", - REG_TO_VA(xcp->cp0_epc)); + (void *) (xcp->cp0_epc)); #endif return SIGILL; } if (get_user(ir, (mips_instruction *) emulpc)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } /* __compute_return_epc() will have updated cp0_epc */ - contpc = REG_TO_VA xcp->cp0_epc; + contpc = (void *) xcp->cp0_epc; /* In order not to confuse ptrace() et al, tweak context */ - xcp->cp0_epc = VA_TO_REG emulpc - 4; - } - else { - emulpc = REG_TO_VA xcp->cp0_epc; - contpc = REG_TO_VA(xcp->cp0_epc + 4); + xcp->cp0_epc = (unsigned long) emulpc - 4; + } else { + emulpc = (void *) xcp->cp0_epc; + contpc = (void *) (xcp->cp0_epc + 4); } emul: - fpuemuprivate.stats.emulated++; + fpuemustats.emulated++; switch (MIPSInst_OPCODE(ir)) { #ifndef SINGLE_ONLY_FPU case ldc1_op:{ - u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + + u64 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] + MIPSInst_SIMM(ir)); u64 val; - fpuemuprivate.stats.loads++; + fpuemustats.loads++; if (get_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } DITOREG(val, MIPSInst_RT(ir)); @@ -263,14 +272,14 @@ } case sdc1_op:{ - u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + + u64 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] + MIPSInst_SIMM(ir)); u64 val; - fpuemuprivate.stats.stores++; + fpuemustats.stores++; DIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } break; @@ -278,13 +287,13 @@ #endif case lwc1_op:{ - u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + + u32 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] + MIPSInst_SIMM(ir)); u32 val; - fpuemuprivate.stats.loads++; + fpuemustats.loads++; if (get_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } #ifdef SINGLE_ONLY_FPU @@ -298,11 +307,11 @@ } case swc1_op:{ - u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + + u32 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] + MIPSInst_SIMM(ir)); u32 val; - fpuemuprivate.stats.stores++; + fpuemustats.stores++; #ifdef SINGLE_ONLY_FPU if (MIPSInst_RT(ir) & 1) { /* illegal register in single-float mode */ @@ -311,7 +320,7 @@ #endif SIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } break; @@ -369,9 +378,10 @@ } if (MIPSInst_RD(ir) == FPCREG_CSR) { value = ctx->fcr31; + value = (value & ~0x3) | mips_rm[value & 0x3]; #ifdef CSRTRACE printk("%p gpr[%d]<-csr=%08x\n", - REG_TO_VA(xcp->cp0_epc), + (void *) (xcp->cp0_epc), MIPSInst_RT(ir), value); #endif } @@ -398,14 +408,13 @@ if (MIPSInst_RD(ir) == FPCREG_CSR) { #ifdef CSRTRACE printk("%p gpr[%d]->csr=%08x\n", - REG_TO_VA(xcp->cp0_epc), + (void *) (xcp->cp0_epc), MIPSInst_RT(ir), value); #endif - ctx->fcr31 = value; - /* copy new rounding mode and - flush bit to ieee library state! */ - ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0; - ieee754_csr.rm = ieee_rm[value & 0x3]; + value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); + ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); + /* convert to ieee library modes */ + ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3]; } if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { return SIGFPE; @@ -445,13 +454,13 @@ * instruction */ xcp->cp0_epc += 4; - contpc = REG_TO_VA + contpc = (void *) (xcp->cp0_epc + (MIPSInst_SIMM(ir) << 2)); if (get_user(ir, (mips_instruction *) - REG_TO_VA xcp->cp0_epc)) { - fpuemuprivate.stats.errors++; + (void *) xcp->cp0_epc)) { + fpuemustats.errors++; return SIGBUS; } @@ -480,7 +489,7 @@ * Single step the non-cp1 * instruction in the dslot */ - return mips_dsemul(xcp, ir, VA_TO_REG contpc); + return mips_dsemul(xcp, ir, (unsigned long) contpc); } else { /* branch not taken */ @@ -539,8 +548,9 @@ } /* we did it !! */ - xcp->cp0_epc = VA_TO_REG(contpc); + xcp->cp0_epc = (unsigned long) contpc; xcp->cp0_cause &= ~CAUSEF_BD; + return 0; } @@ -570,7 +580,7 @@ static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \ ieee754##p t) \ { \ - struct ieee754_csr ieee754_csr_save; \ + struct _ieee754_csr ieee754_csr_save; \ s = f1 (s, t); \ ieee754_csr_save = ieee754_csr; \ s = f2 (s, r); \ @@ -616,7 +626,7 @@ { unsigned rcsr = 0; /* resulting csr */ - fpuemuprivate.stats.cp1xops++; + fpuemustats.cp1xops++; switch (MIPSInst_FMA_FFMT(ir)) { case s_fmt:{ /* 0 */ @@ -628,12 +638,12 @@ switch (MIPSInst_FUNC(ir)) { case lwxc1_op: - va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + + va = (void *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemuprivate.stats.loads++; + fpuemustats.loads++; if (get_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } #ifdef SINGLE_ONLY_FPU @@ -648,10 +658,10 @@ break; case swxc1_op: - va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + + va = (void *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemuprivate.stats.stores++; + fpuemustats.stores++; #ifdef SINGLE_ONLY_FPU if (MIPSInst_FS(ir) & 1) { /* illegal register in single-float @@ -663,7 +673,7 @@ SIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } break; @@ -699,8 +709,6 @@ rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; - if (ieee754_csr.nod) - ctx->fcr31 |= 0x1000000; if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { /*printk ("SIGFPE: fpu csr = %08x\n", ctx->fcr31); */ @@ -724,25 +732,25 @@ switch (MIPSInst_FUNC(ir)) { case ldxc1_op: - va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + + va = (void *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemuprivate.stats.loads++; + fpuemustats.loads++; if (get_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } DITOREG(val, MIPSInst_FD(ir)); break; case sdxc1_op: - va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + + va = (void *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemuprivate.stats.stores++; + fpuemustats.stores++; DIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } break; @@ -810,7 +818,7 @@ #endif } rv; /* resulting value */ - fpuemuprivate.stats.cp1ops++; + fpuemustats.cp1ops++; switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { case s_fmt:{ /* 0 */ union { @@ -1282,7 +1290,7 @@ int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) { - gpreg_t oldepc, prevepc; + unsigned long oldepc, prevepc; mips_instruction insn; int sig = 0; @@ -1291,18 +1299,23 @@ prevepc = xcp->cp0_epc; if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } if (insn == 0) xcp->cp0_epc += 4; /* skip nops */ else { - /* Update ieee754_csr. Only relevant if we have a - h/w FPU */ - ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0; - ieee754_csr.rm = ieee_rm[ctx->fcr31 & 0x3]; - ieee754_csr.cx = (ctx->fcr31 >> 12) & 0x1f; + /* + * The 'ieee754_csr' is an alias of + * ctx->fcr31. No need to copy ctx->fcr31 to + * ieee754_csr. But ieee754_csr.rm is ieee + * library modes. (not mips rounding mode) + */ + /* convert to ieee library modes */ + ieee754_csr.rm = ieee_rm[ieee754_csr.rm]; sig = cop1Emulate(xcp, ctx); + /* revert to mips rounding mode */ + ieee754_csr.rm = mips_rm[ieee754_csr.rm]; } if (cpu_has_fpu) diff -Naur linux-2.6.12.6.orig/arch/mips/math-emu/dp_sqrt.c linux-2.6.12.6/arch/mips/math-emu/dp_sqrt.c --- linux-2.6.12.6.orig/arch/mips/math-emu/dp_sqrt.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/math-emu/dp_sqrt.c 2005-10-02 23:47:37.000000000 +0000 @@ -37,7 +37,7 @@ ieee754dp ieee754dp_sqrt(ieee754dp x) { - struct ieee754_csr oldcsr; + struct _ieee754_csr oldcsr; ieee754dp y, z, t; unsigned scalx, yh; COMPXDP; diff -Naur linux-2.6.12.6.orig/arch/mips/math-emu/dsemul.c linux-2.6.12.6/arch/mips/math-emu/dsemul.c --- linux-2.6.12.6.orig/arch/mips/math-emu/dsemul.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/math-emu/dsemul.c 2005-10-02 23:47:37.000000000 +0000 @@ -28,9 +28,6 @@ #endif #define __mips 4 -extern struct mips_fpu_emulator_private fpuemuprivate; - - /* * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when * we have to emulate the instruction in a COP1 branch delay slot. Do @@ -52,10 +49,10 @@ mips_instruction emul; mips_instruction badinst; mips_instruction cookie; - gpreg_t epc; + unsigned long epc; }; -int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc) +int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) { extern asmlinkage void handle_dsemulret(void); mips_instruction *dsemul_insns; @@ -91,7 +88,7 @@ */ /* Ensure that the two instructions are in the same cache line */ - dsemul_insns = (mips_instruction *) REG_TO_VA ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); + dsemul_insns = (mips_instruction *) ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); fr = (struct emuframe *) dsemul_insns; /* Verify that the stack pointer is not competely insane */ @@ -104,11 +101,11 @@ err |= __put_user(cpc, &fr->epc); if (unlikely(err)) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return SIGBUS; } - regs->cp0_epc = VA_TO_REG & fr->emul; + regs->cp0_epc = (unsigned long) &fr->emul; flush_cache_sigtramp((unsigned long)&fr->badinst); @@ -118,7 +115,7 @@ int do_dsemulret(struct pt_regs *xcp) { struct emuframe *fr; - gpreg_t epc; + unsigned long epc; u32 insn, cookie; int err = 0; @@ -141,7 +138,7 @@ err |= __get_user(cookie, &fr->cookie); if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) { - fpuemuprivate.stats.errors++; + fpuemustats.errors++; return 0; } diff -Naur linux-2.6.12.6.orig/arch/mips/math-emu/dsemul.h linux-2.6.12.6/arch/mips/math-emu/dsemul.h --- linux-2.6.12.6.orig/arch/mips/math-emu/dsemul.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/math-emu/dsemul.h 2005-10-02 23:47:37.000000000 +0000 @@ -1,11 +1,5 @@ -typedef long gpreg_t; -typedef void *vaddr_t; - -#define REG_TO_VA (vaddr_t) -#define VA_TO_REG (gpreg_t) - -int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc); -int do_dsemulret(struct pt_regs *xcp); +extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc); +extern int do_dsemulret(struct pt_regs *xcp); /* Instruction which will always cause an address error */ #define AdELOAD 0x8c000001 /* lw $0,1($0) */ diff -Naur linux-2.6.12.6.orig/arch/mips/math-emu/ieee754.c linux-2.6.12.6/arch/mips/math-emu/ieee754.c --- linux-2.6.12.6.orig/arch/mips/math-emu/ieee754.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/math-emu/ieee754.c 2005-10-02 23:47:37.000000000 +0000 @@ -50,10 +50,6 @@ "SNaN", }; -/* the control status register -*/ -struct ieee754_csr ieee754_csr; - /* special constants */ diff -Naur linux-2.6.12.6.orig/arch/mips/math-emu/ieee754.h linux-2.6.12.6/arch/mips/math-emu/ieee754.h --- linux-2.6.12.6.orig/arch/mips/math-emu/ieee754.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/math-emu/ieee754.h 2005-10-02 23:47:37.000000000 +0000 @@ -1,13 +1,8 @@ -/* single and double precision fp ops - * missing extended precision. -*/ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. * http://www.algor.co.uk * - * ######################################################################## - * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -21,20 +16,16 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * ######################################################################## - */ - -/************************************************************************** * Nov 7, 2000 * Modification to allow integration with Linux kernel * * Kevin D. Kissell, kevink@mips.com and Carsten Langgard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - *************************************************************************/ + */ -#ifdef __KERNEL__ -/* Going from Algorithmics to Linux native environment, add this */ +#include #include +#include /* * Not very pretty, but the Linux kernel's normal va_list definition @@ -44,18 +35,7 @@ #include #endif -#else - -/* Note that __KERNEL__ is taken to mean Linux kernel */ - -#if #system(OpenBSD) -#include -#endif -#include - -#endif /* __KERNEL__ */ - -#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__) +#ifdef __LITTLE_ENDIAN struct ieee754dp_konst { unsigned mantlo:32; unsigned manthi:20; @@ -86,13 +66,14 @@ } ieee754sp; #endif -#if (defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN) || defined(__MIPSEB__) +#ifdef __BIG_ENDIAN struct ieee754dp_konst { unsigned sign:1; unsigned bexp:11; unsigned manthi:20; unsigned mantlo:32; }; + typedef union _ieee754dp { struct ieee754dp_konst oparts; struct { @@ -251,93 +232,109 @@ /* "normal" comparisons */ -static __inline int ieee754sp_eq(ieee754sp x, ieee754sp y) +static inline int ieee754sp_eq(ieee754sp x, ieee754sp y) { return ieee754sp_cmp(x, y, IEEE754_CEQ, 0); } -static __inline int ieee754sp_ne(ieee754sp x, ieee754sp y) +static inline int ieee754sp_ne(ieee754sp x, ieee754sp y) { return ieee754sp_cmp(x, y, IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0); } -static __inline int ieee754sp_lt(ieee754sp x, ieee754sp y) +static inline int ieee754sp_lt(ieee754sp x, ieee754sp y) { return ieee754sp_cmp(x, y, IEEE754_CLT, 0); } -static __inline int ieee754sp_le(ieee754sp x, ieee754sp y) +static inline int ieee754sp_le(ieee754sp x, ieee754sp y) { return ieee754sp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0); } -static __inline int ieee754sp_gt(ieee754sp x, ieee754sp y) +static inline int ieee754sp_gt(ieee754sp x, ieee754sp y) { return ieee754sp_cmp(x, y, IEEE754_CGT, 0); } -static __inline int ieee754sp_ge(ieee754sp x, ieee754sp y) +static inline int ieee754sp_ge(ieee754sp x, ieee754sp y) { return ieee754sp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0); } -static __inline int ieee754dp_eq(ieee754dp x, ieee754dp y) +static inline int ieee754dp_eq(ieee754dp x, ieee754dp y) { return ieee754dp_cmp(x, y, IEEE754_CEQ, 0); } -static __inline int ieee754dp_ne(ieee754dp x, ieee754dp y) +static inline int ieee754dp_ne(ieee754dp x, ieee754dp y) { return ieee754dp_cmp(x, y, IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0); } -static __inline int ieee754dp_lt(ieee754dp x, ieee754dp y) +static inline int ieee754dp_lt(ieee754dp x, ieee754dp y) { return ieee754dp_cmp(x, y, IEEE754_CLT, 0); } -static __inline int ieee754dp_le(ieee754dp x, ieee754dp y) +static inline int ieee754dp_le(ieee754dp x, ieee754dp y) { return ieee754dp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0); } -static __inline int ieee754dp_gt(ieee754dp x, ieee754dp y) +static inline int ieee754dp_gt(ieee754dp x, ieee754dp y) { return ieee754dp_cmp(x, y, IEEE754_CGT, 0); } -static __inline int ieee754dp_ge(ieee754dp x, ieee754dp y) +static inline int ieee754dp_ge(ieee754dp x, ieee754dp y) { return ieee754dp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0); } -/* like strtod -*/ +/* + * Like strtod + */ ieee754dp ieee754dp_fstr(const char *s, char **endp); char *ieee754dp_tstr(ieee754dp x, int prec, int fmt, int af); -/* the control status register -*/ -struct ieee754_csr { - unsigned pad:13; +/* + * The control status register + */ +struct _ieee754_csr { +#ifdef __BIG_ENDIAN + unsigned pad0:7; unsigned nod:1; /* set 1 for no denormalised numbers */ - unsigned cx:5; /* exceptions this operation */ + unsigned c:1; /* condition */ + unsigned pad1:5; + unsigned cx:6; /* exceptions this operation */ unsigned mx:5; /* exception enable mask */ unsigned sx:5; /* exceptions total */ unsigned rm:2; /* current rounding mode */ +#endif +#ifdef __LITTLE_ENDIAN + unsigned rm:2; /* current rounding mode */ + unsigned sx:5; /* exceptions total */ + unsigned mx:5; /* exception enable mask */ + unsigned cx:6; /* exceptions this operation */ + unsigned pad1:5; + unsigned c:1; /* condition */ + unsigned nod:1; /* set 1 for no denormalised numbers */ + unsigned pad0:7; +#endif }; -extern struct ieee754_csr ieee754_csr; +#define ieee754_csr (*(struct _ieee754_csr *)(¤t->thread.fpu.soft.fcr31)) -static __inline unsigned ieee754_getrm(void) +static inline unsigned ieee754_getrm(void) { return (ieee754_csr.rm); } -static __inline unsigned ieee754_setrm(unsigned rm) +static inline unsigned ieee754_setrm(unsigned rm) { return (ieee754_csr.rm = rm); } @@ -345,14 +342,14 @@ /* * get current exceptions */ -static __inline unsigned ieee754_getcx(void) +static inline unsigned ieee754_getcx(void) { return (ieee754_csr.cx); } /* test for current exception condition */ -static __inline int ieee754_cxtest(unsigned n) +static inline int ieee754_cxtest(unsigned n) { return (ieee754_csr.cx & n); } @@ -360,21 +357,21 @@ /* * get sticky exceptions */ -static __inline unsigned ieee754_getsx(void) +static inline unsigned ieee754_getsx(void) { return (ieee754_csr.sx); } /* clear sticky conditions */ -static __inline unsigned ieee754_clrsx(void) +static inline unsigned ieee754_clrsx(void) { return (ieee754_csr.sx = 0); } /* test for sticky exception condition */ -static __inline int ieee754_sxtest(unsigned n) +static inline int ieee754_sxtest(unsigned n) { return (ieee754_csr.sx & n); } @@ -406,52 +403,34 @@ #define ieee754dp_spcvals ((const ieee754dp *)__ieee754dp_spcvals) #define ieee754sp_spcvals ((const ieee754sp *)__ieee754sp_spcvals) -/* return infinity with given sign -*/ -#define ieee754dp_inf(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)]) -#define ieee754dp_zero(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PZERO+(sn)]) -#define ieee754dp_one(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PONE+(sn)]) -#define ieee754dp_ten(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PTEN+(sn)]) -#define ieee754dp_indef() \ - (ieee754dp_spcvals[IEEE754_SPCVAL_INDEF]) -#define ieee754dp_max(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PMAX+(sn)]) -#define ieee754dp_min(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PMIN+(sn)]) -#define ieee754dp_mind(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PMIND+(sn)]) -#define ieee754dp_1e31() \ - (ieee754dp_spcvals[IEEE754_SPCVAL_P1E31]) -#define ieee754dp_1e63() \ - (ieee754dp_spcvals[IEEE754_SPCVAL_P1E63]) - -#define ieee754sp_inf(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)]) -#define ieee754sp_zero(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PZERO+(sn)]) -#define ieee754sp_one(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PONE+(sn)]) -#define ieee754sp_ten(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PTEN+(sn)]) -#define ieee754sp_indef() \ - (ieee754sp_spcvals[IEEE754_SPCVAL_INDEF]) -#define ieee754sp_max(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PMAX+(sn)]) -#define ieee754sp_min(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PMIN+(sn)]) -#define ieee754sp_mind(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PMIND+(sn)]) -#define ieee754sp_1e31() \ - (ieee754sp_spcvals[IEEE754_SPCVAL_P1E31]) -#define ieee754sp_1e63() \ - (ieee754sp_spcvals[IEEE754_SPCVAL_P1E63]) +/* + * Return infinity with given sign + */ +#define ieee754dp_inf(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)]) +#define ieee754dp_zero(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PZERO+(sn)]) +#define ieee754dp_one(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PONE+(sn)]) +#define ieee754dp_ten(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PTEN+(sn)]) +#define ieee754dp_indef() (ieee754dp_spcvals[IEEE754_SPCVAL_INDEF]) +#define ieee754dp_max(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMAX+(sn)]) +#define ieee754dp_min(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMIN+(sn)]) +#define ieee754dp_mind(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMIND+(sn)]) +#define ieee754dp_1e31() (ieee754dp_spcvals[IEEE754_SPCVAL_P1E31]) +#define ieee754dp_1e63() (ieee754dp_spcvals[IEEE754_SPCVAL_P1E63]) + +#define ieee754sp_inf(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)]) +#define ieee754sp_zero(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PZERO+(sn)]) +#define ieee754sp_one(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PONE+(sn)]) +#define ieee754sp_ten(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PTEN+(sn)]) +#define ieee754sp_indef() (ieee754sp_spcvals[IEEE754_SPCVAL_INDEF]) +#define ieee754sp_max(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMAX+(sn)]) +#define ieee754sp_min(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMIN+(sn)]) +#define ieee754sp_mind(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMIND+(sn)]) +#define ieee754sp_1e31() (ieee754sp_spcvals[IEEE754_SPCVAL_P1E31]) +#define ieee754sp_1e63() (ieee754sp_spcvals[IEEE754_SPCVAL_P1E63]) -/* indefinite integer value -*/ +/* + * Indefinite integer value + */ #define ieee754si_indef() INT_MAX #ifdef LONG_LONG_MAX #define ieee754di_indef() LONG_LONG_MAX diff -Naur linux-2.6.12.6.orig/arch/mips/math-emu/kernel_linkage.c linux-2.6.12.6/arch/mips/math-emu/kernel_linkage.c --- linux-2.6.12.6.orig/arch/mips/math-emu/kernel_linkage.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/math-emu/kernel_linkage.c 2005-10-02 23:47:37.000000000 +0000 @@ -27,8 +27,6 @@ #include -extern struct mips_fpu_emulator_private fpuemuprivate; - #define SIGNALLING_NAN 0x7ff800007ff80000LL void fpu_emulator_init_fpu(void) @@ -65,7 +63,6 @@ &sc->sc_fpregs[i]); } err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); - err |= __put_user(fpuemuprivate.eir, &sc->sc_fpc_eir); return err; } @@ -81,7 +78,6 @@ &sc->sc_fpregs[i]); } err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); - err |= __get_user(fpuemuprivate.eir, &sc->sc_fpc_eir); return err; } @@ -102,7 +98,6 @@ &sc->sc_fpregs[i]); } err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); - err |= __put_user(fpuemuprivate.eir, &sc->sc_fpc_eir); return err; } @@ -118,7 +113,6 @@ &sc->sc_fpregs[i]); } err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); - err |= __get_user(fpuemuprivate.eir, &sc->sc_fpc_eir); return err; } diff -Naur linux-2.6.12.6.orig/arch/mips/mips-boards/atlas/atlas_int.c linux-2.6.12.6/arch/mips/mips-boards/atlas/atlas_int.c --- linux-2.6.12.6.orig/arch/mips/mips-boards/atlas/atlas_int.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mips-boards/atlas/atlas_int.c 2005-10-02 23:47:37.000000000 +0000 @@ -76,14 +76,13 @@ } static struct hw_interrupt_type atlas_irq_type = { - "Atlas", - startup_atlas_irq, - shutdown_atlas_irq, - enable_atlas_irq, - disable_atlas_irq, - mask_and_ack_atlas_irq, - end_atlas_irq, - NULL + .typename = "Atlas", + .startup = startup_atlas_irq, + .shutdown = shutdown_atlas_irq, + .enable = enable_atlas_irq, + .disable = disable_atlas_irq, + .ack = mask_and_ack_atlas_irq, + .end = end_atlas_irq, }; static inline int ls1bit32(unsigned int x) diff -Naur linux-2.6.12.6.orig/arch/mips/mips-boards/atlas/atlas_setup.c linux-2.6.12.6/arch/mips/mips-boards/atlas/atlas_setup.c --- linux-2.6.12.6.orig/arch/mips/mips-boards/atlas/atlas_setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mips-boards/atlas/atlas_setup.c 2005-10-02 23:47:37.000000000 +0000 @@ -50,8 +50,10 @@ return "MIPS Atlas"; } -static int __init atlas_setup(void) +void __init plat_setup(void) { + mips_pcibios_init(); + ioport_resource.end = 0x7fffffff; serial_init (); @@ -64,12 +66,8 @@ board_time_init = mips_time_init; board_timer_setup = mips_timer_setup; rtc_get_time = mips_rtc_get_time; - - return 0; } -early_initcall(atlas_setup); - static void __init serial_init(void) { #ifdef CONFIG_SERIAL_8250 diff -Naur linux-2.6.12.6.orig/arch/mips/mips-boards/generic/init.c linux-2.6.12.6/arch/mips/mips-boards/generic/init.c --- linux-2.6.12.6.orig/arch/mips/mips-boards/generic/init.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mips-boards/generic/init.c 2005-10-02 23:47:37.000000000 +0000 @@ -1,6 +1,8 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -22,18 +24,17 @@ #include #include -#include #include +#include +#include +#include + #include #include -#ifdef CONFIG_MIPS_GT64120 -#include -#endif -#include #include -#ifdef CONFIG_MIPS_MALTA +#include + #include -#endif #ifdef CONFIG_KGDB extern int rs_kgdb_hook(int, int); @@ -225,6 +226,8 @@ void __init prom_init(void) { + u32 start, map, mask, data; + prom_argc = fw_arg0; _prom_argv = (int *) fw_arg1; _prom_envp = (int *) fw_arg2; @@ -266,12 +269,15 @@ #else GT_WRITE(GT_PCI0_CMD_OFS, 0); #endif + /* Fix up PCI I/O mapping if necessary (for Atlas). */ + start = GT_READ(GT_PCI0IOLD_OFS); + map = GT_READ(GT_PCI0IOREMAP_OFS); + if ((start & map) != 0) { + map &= ~start; + GT_WRITE(GT_PCI0IOREMAP_OFS, map); + } -#ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_GT_PORT_BASE); -#else - set_io_port_base((unsigned long)ioremap(0, 0x20000000)); -#endif break; case MIPS_REVISION_CORID_CORE_EMUL_BON: @@ -300,11 +306,7 @@ BONITO_BONGENCFG_BYTESWAP; #endif -#ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_BONITO_PORT_BASE); -#else - set_io_port_base((unsigned long)ioremap(0, 0x20000000)); -#endif break; case MIPS_REVISION_CORID_CORE_MSC: @@ -312,6 +314,12 @@ case MIPS_REVISION_CORID_CORE_EMUL_MSC: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); + mb(); + MSC_READ(MSC01_PCI_CFG, data); + MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); + wmb(); + + /* Fix up lane swapping. */ #ifdef CONFIG_CPU_LITTLE_ENDIAN MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); #else @@ -320,12 +328,23 @@ MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); #endif + /* Fix up target memory mapping. */ + MSC_READ(MSC01_PCI_BAR0, mask); + MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); + + /* Don't handle target retries indefinitely. */ + if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == + MSC01_PCI_CFG_MAXRTRY_MSK) + data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << + MSC01_PCI_CFG_MAXRTRY_SHF)) | + ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << + MSC01_PCI_CFG_MAXRTRY_SHF); + + wmb(); + MSC_WRITE(MSC01_PCI_CFG, data); + mb(); -#ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_MSC_PORT_BASE); -#else - set_io_port_base((unsigned long)ioremap(0, 0x20000000)); -#endif break; default: diff -Naur linux-2.6.12.6.orig/arch/mips/mips-boards/generic/pci.c linux-2.6.12.6/arch/mips/mips-boards/generic/pci.c --- linux-2.6.12.6.orig/arch/mips/mips-boards/generic/pci.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mips-boards/generic/pci.c 2005-10-02 23:47:37.000000000 +0000 @@ -1,6 +1,8 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki * * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) * @@ -19,65 +21,46 @@ * * MIPS boards specific PCI support. */ -#include #include #include #include #include -#include #include + +#include #include #include -#ifdef CONFIG_MIPS_MALTA -#include -#endif static struct resource bonito64_mem_resource = { .name = "Bonito PCI MEM", - .start = 0x10000000UL, - .end = 0x1bffffffUL, .flags = IORESOURCE_MEM, }; static struct resource bonito64_io_resource = { - .name = "Bonito IO MEM", - .start = 0x00002000UL, /* avoid conflicts with YAMON allocated I/O addresses */ + .name = "Bonito PCI I/O", + .start = 0x00000000UL, .end = 0x000fffffUL, .flags = IORESOURCE_IO, }; static struct resource gt64120_mem_resource = { - .name = "GT64120 PCI MEM", - .start = 0x10000000UL, - .end = 0x1bdfffffUL, + .name = "GT-64120 PCI MEM", .flags = IORESOURCE_MEM, }; static struct resource gt64120_io_resource = { - .name = "GT64120 IO MEM", -#ifdef CONFIG_MIPS_ATLAS - .start = 0x18000000UL, - .end = 0x181fffffUL, -#endif -#ifdef CONFIG_MIPS_MALTA - .start = 0x00002000UL, - .end = 0x001fffffUL, -#endif + .name = "GT-64120 PCI I/O", .flags = IORESOURCE_IO, }; static struct resource msc_mem_resource = { .name = "MSC PCI MEM", - .start = 0x10000000UL, - .end = 0x1fffffffUL, .flags = IORESOURCE_MEM, }; static struct resource msc_io_resource = { - .name = "MSC IO MEM", - .start = 0x00002000UL, - .end = 0x007fffffUL, + .name = "MSC PCI I/O", .flags = IORESOURCE_IO, }; @@ -89,7 +72,6 @@ .pci_ops = &bonito64_pci_ops, .io_resource = &bonito64_io_resource, .mem_resource = &bonito64_mem_resource, - .mem_offset = 0x10000000UL, .io_offset = 0x00000000UL, }; @@ -97,21 +79,18 @@ .pci_ops = >64120_pci_ops, .io_resource = >64120_io_resource, .mem_resource = >64120_mem_resource, - .mem_offset = 0x00000000UL, - .io_offset = 0x00000000UL, }; -static struct pci_controller msc_controller = { +static struct pci_controller msc_controller = { .pci_ops = &msc_pci_ops, .io_resource = &msc_io_resource, .mem_resource = &msc_mem_resource, - .mem_offset = 0x10000000UL, - .io_offset = 0x00000000UL, }; -static int __init pcibios_init(void) +void __init mips_pcibios_init(void) { struct pci_controller *controller; + unsigned long start, end, map, start1, end1, map1, map2, map3, mask; switch (mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: @@ -130,34 +109,139 @@ (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ - GT_PCI0_CFGADDR_CONFIGEN_BIT ); + GT_PCI0_CFGADDR_CONFIGEN_BIT); /* Perform the write */ GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); + /* Set up resource ranges from the controller's registers. */ + start = GT_READ(GT_PCI0M0LD_OFS); + end = GT_READ(GT_PCI0M0HD_OFS); + map = GT_READ(GT_PCI0M0REMAP_OFS); + end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); + start1 = GT_READ(GT_PCI0M1LD_OFS); + end1 = GT_READ(GT_PCI0M1HD_OFS); + map1 = GT_READ(GT_PCI0M1REMAP_OFS); + end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK); + /* Cannot support multiple windows, use the wider. */ + if (end1 - start1 > end - start) { + start = start1; + end = end1; + map = map1; + } + mask = ~(start ^ end); + /* We don't support remapping with a discontiguous mask. */ + BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && + mask != ~((mask & -mask) - 1)); + gt64120_mem_resource.start = start; + gt64120_mem_resource.end = end; + gt64120_controller.mem_offset = (start & mask) - (map & mask); + /* Addresses are 36-bit, so do shifts in the destinations. */ + gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF; + gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; + gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; + gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF; + + start = GT_READ(GT_PCI0IOLD_OFS); + end = GT_READ(GT_PCI0IOHD_OFS); + map = GT_READ(GT_PCI0IOREMAP_OFS); + end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); + mask = ~(start ^ end); + /* We don't support remapping with a discontiguous mask. */ + BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && + mask != ~((mask & -mask) - 1)); + gt64120_io_resource.start = map & mask; + gt64120_io_resource.end = (map & mask) | ~mask; + gt64120_controller.io_offset = 0; + /* Addresses are 36-bit, so do shifts in the destinations. */ + gt64120_io_resource.start <<= GT_PCI_DCRM_SHF; + gt64120_io_resource.end <<= GT_PCI_DCRM_SHF; + gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; + controller = >64120_controller; break; case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: case MIPS_REVISION_CORID_CORE_EMUL_BON: + /* Set up resource ranges from the controller's registers. */ + map = BONITO_PCIMAP; + map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >> + BONITO_PCIMAP_PCIMAP_LO0_SHIFT; + map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >> + BONITO_PCIMAP_PCIMAP_LO1_SHIFT; + map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >> + BONITO_PCIMAP_PCIMAP_LO2_SHIFT; + /* Combine as many adjacent windows as possible. */ + map = map1; + start = BONITO_PCILO0_BASE; + end = 1; + if (map3 == map2 + 1) { + map = map2; + start = BONITO_PCILO1_BASE; + end++; + } + if (map2 == map1 + 1) { + map = map1; + start = BONITO_PCILO0_BASE; + end++; + } + bonito64_mem_resource.start = start; + bonito64_mem_resource.end = start + + BONITO_PCIMAP_WINBASE(end) - 1; + bonito64_controller.mem_offset = start - + BONITO_PCIMAP_WINBASE(map); + controller = &bonito64_controller; break; case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_EMUL_MSC: + /* Set up resource ranges from the controller's registers. */ + MSC_READ(MSC01_PCI_SC2PMBASL, start); + MSC_READ(MSC01_PCI_SC2PMMSKL, mask); + MSC_READ(MSC01_PCI_SC2PMMAPL, map); + msc_mem_resource.start = start & mask; + msc_mem_resource.end = (start & mask) | ~mask; + msc_controller.mem_offset = (start & mask) - (map & mask); + + MSC_READ(MSC01_PCI_SC2PIOBASL, start); + MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); + MSC_READ(MSC01_PCI_SC2PIOMAPL, map); + msc_io_resource.start = map & mask; + msc_io_resource.end = (map & mask) | ~mask; + msc_controller.io_offset = 0; + ioport_resource.end = ~mask; + + /* If ranges overlap I/O takes precedence. */ + start = start & mask; + end = start | ~mask; + if ((start >= msc_mem_resource.start && + start <= msc_mem_resource.end) || + (end >= msc_mem_resource.start && + end <= msc_mem_resource.end)) { + /* Use the larger space. */ + start = max(start, msc_mem_resource.start); + end = min(end, msc_mem_resource.end); + if (start - msc_mem_resource.start >= + msc_mem_resource.end - end) + msc_mem_resource.end = start - 1; + else + msc_mem_resource.start = end + 1; + } + controller = &msc_controller; break; default: - return 1; + return; } + if (controller->io_resource->start < 0x00001000UL) /* FIXME */ + controller->io_resource->start = 0x00001000UL; + + iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ ioport_resource.end = controller->io_resource->end; register_pci_controller (controller); - - return 0; } - -early_initcall(pcibios_init); diff -Naur linux-2.6.12.6.orig/arch/mips/mips-boards/malta/malta_setup.c linux-2.6.12.6/arch/mips/mips-boards/malta/malta_setup.c --- linux-2.6.12.6.orig/arch/mips/mips-boards/malta/malta_setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mips-boards/malta/malta_setup.c 2005-10-02 23:47:37.000000000 +0000 @@ -111,10 +111,12 @@ } #endif -static int __init malta_setup(void) +void __init plat_setup(void) { unsigned int i; + mips_pcibios_init(); + /* Request I/O space for devices used on the Malta board. */ for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) request_resource(&ioport_resource, standard_io_resources+i); @@ -224,8 +226,4 @@ board_time_init = mips_time_init; board_timer_setup = mips_timer_setup; rtc_get_time = mips_rtc_get_time; - - return 0; } - -early_initcall(malta_setup); diff -Naur linux-2.6.12.6.orig/arch/mips/mips-boards/sead/sead_int.c linux-2.6.12.6/arch/mips/mips-boards/sead/sead_int.c --- linux-2.6.12.6.orig/arch/mips/mips-boards/sead/sead_int.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mips-boards/sead/sead_int.c 2005-10-02 23:47:37.000000000 +0000 @@ -2,6 +2,7 @@ * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2004 Maciej W. Rozycki * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -21,7 +22,9 @@ */ #include #include -#include + +#include +#include #include @@ -39,13 +42,8 @@ void __init arch_init_irq(void) { - /* - * Mask out all interrupt - */ - clear_c0_status(0x0000ff00); + mips_cpu_irq_init(0); /* Now safe to set the exception vector. */ set_except_vector(0, mipsIRQ); - - mips_cpu_irq_init(0); } diff -Naur linux-2.6.12.6.orig/arch/mips/mips-boards/sead/sead_setup.c linux-2.6.12.6/arch/mips/mips-boards/sead/sead_setup.c --- linux-2.6.12.6.orig/arch/mips/mips-boards/sead/sead_setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mips-boards/sead/sead_setup.c 2005-10-02 23:47:37.000000000 +0000 @@ -57,8 +57,6 @@ mips_reboot_setup(); } -early_initcall(sead_setup); - static void __init serial_init(void) { #ifdef CONFIG_SERIAL_8250 diff -Naur linux-2.6.12.6.orig/arch/mips/mm/c-r3k.c linux-2.6.12.6/arch/mips/mm/c-r3k.c --- linux-2.6.12.6.orig/arch/mips/mm/c-r3k.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/c-r3k.c 2005-10-02 23:47:37.000000000 +0000 @@ -221,12 +221,14 @@ struct mm_struct *mm) { pgd_t *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte; unsigned long physpage; pgd = pgd_offset(mm, addr); - pmd = pmd_offset(pgd, addr); + pud = pud_offset(pgd, addr); + pmd = pmd_offset(pud, addr); pte = pte_offset(pmd, addr); if ((physpage = pte_val(*pte)) & _PAGE_VALID) diff -Naur linux-2.6.12.6.orig/arch/mips/mm/c-r4k.c linux-2.6.12.6/arch/mips/mm/c-r4k.c --- linux-2.6.12.6.orig/arch/mips/mm/c-r4k.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/c-r4k.c 2005-10-02 23:47:37.000000000 +0000 @@ -26,6 +26,7 @@ #include #include #include +#include /* for run_uncached() */ static unsigned long icache_size, dcache_size, scache_size; @@ -238,22 +239,6 @@ r4k_blast_scache_page = blast_scache128_page; } -static void (* r4k_blast_scache_page_indexed)(unsigned long addr); - -static inline void r4k_blast_scache_page_indexed_setup(void) -{ - unsigned long sc_lsize = cpu_scache_line_size(); - - if (sc_lsize == 16) - r4k_blast_scache_page_indexed = blast_scache16_page_indexed; - else if (sc_lsize == 32) - r4k_blast_scache_page_indexed = blast_scache32_page_indexed; - else if (sc_lsize == 64) - r4k_blast_scache_page_indexed = blast_scache64_page_indexed; - else if (sc_lsize == 128) - r4k_blast_scache_page_indexed = blast_scache128_page_indexed; -} - static void (* r4k_blast_scache)(void); static inline void r4k_blast_scache_setup(void) @@ -334,6 +319,9 @@ { struct mm_struct *mm = args; + if (!cpu_has_dc_aliases) + return; + if (!cpu_context(smp_processor_id(), mm)) return; @@ -353,9 +341,6 @@ static void r4k_flush_cache_mm(struct mm_struct *mm) { - if (!cpu_has_dc_aliases) - return; - on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1); } @@ -372,12 +357,28 @@ int exec = vma->vm_flags & VM_EXEC; struct mm_struct *mm = vma->vm_mm; pgd_t *pgdp; + pud_t *pudp; pmd_t *pmdp; pte_t *ptep; + /* + * If ownes no valid ASID yet, cannot possibly have gotten + * this page into the cache. + */ + if (cpu_context(smp_processor_id(), mm) == 0) + return; + + /* + * If ownes no valid ASID yet, cannot possibly have gotten + * this page into the cache. + */ + if (cpu_context(smp_processor_id(), mm) == 0) + return; + page &= PAGE_MASK; pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); + pudp = pud_offset(pgdp, page); + pmdp = pmd_offset(pudp, page); ptep = pte_offset(pmdp, page); /* @@ -394,11 +395,8 @@ * in that case, which doesn't overly flush the cache too much. */ if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { - if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { + if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) r4k_blast_dcache_page(page); - if (exec && !cpu_icache_snoops_remote_store) - r4k_blast_scache_page(page); - } if (exec) r4k_blast_icache_page(page); @@ -410,17 +408,14 @@ * to work correctly. */ page = INDEX_BASE + (page & (dcache_size - 1)); - if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { + if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) r4k_blast_dcache_page_indexed(page); - if (exec && !cpu_icache_snoops_remote_store) - r4k_blast_scache_page_indexed(page); - } if (exec) { if (cpu_has_vtag_icache) { int cpu = smp_processor_id(); - if (cpu_context(cpu, vma->vm_mm) != 0) - drop_mmu_context(vma->vm_mm, cpu); + if (cpu_context(cpu, mm) != 0) + drop_mmu_context(mm, cpu); } else r4k_blast_icache_page_indexed(page); } @@ -430,13 +425,6 @@ { struct flush_cache_page_args args; - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (cpu_context(smp_processor_id(), vma->vm_mm) == 0) - return; - args.vma = vma; args.page = page; @@ -454,8 +442,8 @@ } struct flush_icache_range_args { - unsigned long start; - unsigned long end; + unsigned long __user start; + unsigned long __user end; }; static inline void local_r4k_flush_icache_range(void *args) @@ -463,15 +451,14 @@ struct flush_icache_range_args *fir_args = args; unsigned long dc_lsize = current_cpu_data.dcache.linesz; unsigned long ic_lsize = current_cpu_data.icache.linesz; - unsigned long sc_lsize = current_cpu_data.scache.linesz; unsigned long start = fir_args->start; unsigned long end = fir_args->end; unsigned long addr, aend; if (!cpu_has_ic_fills_f_dc) { - if (end - start > dcache_size) { + if (end - start > dcache_size) r4k_blast_dcache(); - } else { + else { addr = start & ~(dc_lsize - 1); aend = (end - 1) & ~(dc_lsize - 1); @@ -483,23 +470,6 @@ addr += dc_lsize; } } - - if (!cpu_icache_snoops_remote_store) { - if (end - start > scache_size) { - r4k_blast_scache(); - } else { - addr = start & ~(sc_lsize - 1); - aend = (end - 1) & ~(sc_lsize - 1); - - while (1) { - /* Hit_Writeback_Inv_D */ - protected_writeback_scache_line(addr); - if (addr == aend) - break; - addr += sc_lsize; - } - } - } } if (end - start > icache_size) @@ -517,7 +487,8 @@ } } -static void r4k_flush_icache_range(unsigned long start, unsigned long end) +static void r4k_flush_icache_range(unsigned long __user start, + unsigned long __user end) { struct flush_icache_range_args args; @@ -566,8 +537,6 @@ if (!cpu_has_ic_fills_f_dc) { unsigned long addr = (unsigned long) page_address(page); r4k_blast_dcache_page(addr); - if (!cpu_icache_snoops_remote_store) - r4k_blast_scache_page(addr); ClearPageDcacheDirty(page); } @@ -665,32 +634,24 @@ if (cpu_has_subset_pcaches) { unsigned long sc_lsize = current_cpu_data.scache.linesz; - if (size >= scache_size) { - r4k_blast_scache(); - return; - } - a = addr & ~(sc_lsize - 1); end = (addr + size - 1) & ~(sc_lsize - 1); while (1) { - flush_scache_line(a); /* Hit_Writeback_Inv_SD */ + invalidate_scache_line(a); /* Hit_Invalidate_SD/S */ if (a == end) break; a += sc_lsize; } return; } - - if (size >= dcache_size) { - r4k_blast_dcache(); - } else { + { unsigned long dc_lsize = current_cpu_data.dcache.linesz; R4600_HIT_CACHEOP_WAR_IMPL; a = addr & ~(dc_lsize - 1); end = (addr + size - 1) & ~(dc_lsize - 1); while (1) { - flush_dcache_line(a); /* Hit_Writeback_Inv_D */ + invalidate_dcache_line(a); /* Hit_Invalidate_D */ if (a == end) break; a += dc_lsize; @@ -710,13 +671,10 @@ { unsigned long ic_lsize = current_cpu_data.icache.linesz; unsigned long dc_lsize = current_cpu_data.dcache.linesz; - unsigned long sc_lsize = current_cpu_data.scache.linesz; unsigned long addr = (unsigned long) arg; R4600_HIT_CACHEOP_WAR_IMPL; protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); - if (!cpu_icache_snoops_remote_store) - protected_writeback_scache_line(addr & ~(sc_lsize - 1)); protected_flush_icache_line(addr & ~(ic_lsize - 1)); if (MIPS4K_ICACHE_REFILL_WAR) { __asm__ __volatile__ ( @@ -783,8 +741,8 @@ } } -static char *way_string[] __initdata = { NULL, "direct mapped", "2-way", - "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" +static char *way_string[] = { NULL, "direct mapped", "2-way", "3-way", "4-way", + "5-way", "6-way", "7-way", "8-way" }; static void __init probe_pcache(void) @@ -1011,9 +969,19 @@ * normally they'd suffer from aliases but magic in the hardware deals * with that for us so we don't need to take care ourselves. */ - if (c->cputype != CPU_R10000 && c->cputype != CPU_R12000) - if (c->dcache.waysize > PAGE_SIZE) - c->dcache.flags |= MIPS_CACHE_ALIASES; + switch (c->cputype) { + case CPU_20KC: + case CPU_25KF: + case CPU_R10000: + case CPU_R12000: + case CPU_SB1: + break; + case CPU_24K: + if (!(read_c0_config7() & (1 << 16))) + default: + if (c->dcache.waysize > PAGE_SIZE) + c->dcache.flags |= MIPS_CACHE_ALIASES; + } switch (c->cputype) { case CPU_20KC: @@ -1024,7 +992,11 @@ c->icache.flags |= MIPS_CACHE_VTAG; break; + case CPU_AU1000: case CPU_AU1500: + case CPU_AU1100: + case CPU_AU1550: + case CPU_AU1200: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; } @@ -1102,7 +1074,6 @@ return 1; } -typedef int (*probe_func_t)(unsigned long); extern int r5k_sc_init(void); extern int rm7k_sc_init(void); @@ -1110,7 +1081,6 @@ { struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config = read_c0_config(); - probe_func_t probe_scache_kseg1; int sc_present = 0; /* @@ -1123,8 +1093,7 @@ case CPU_R4000MC: case CPU_R4400SC: case CPU_R4400MC: - probe_scache_kseg1 = (probe_func_t) (CKSEG1ADDR(&probe_scache)); - sc_present = probe_scache_kseg1(config); + sc_present = run_uncached(probe_scache); if (sc_present) c->options |= MIPS_CPU_CACHE_CDEX_S; break; @@ -1212,9 +1181,6 @@ probe_pcache(); setup_scache(); - if (c->dcache.sets * c->dcache.ways > PAGE_SIZE) - c->dcache.flags |= MIPS_CACHE_ALIASES; - r4k_blast_dcache_page_setup(); r4k_blast_dcache_page_indexed_setup(); r4k_blast_dcache_setup(); @@ -1222,7 +1188,6 @@ r4k_blast_icache_page_indexed_setup(); r4k_blast_icache_setup(); r4k_blast_scache_page_setup(); - r4k_blast_scache_page_indexed_setup(); r4k_blast_scache_setup(); /* diff -Naur linux-2.6.12.6.orig/arch/mips/mm/c-sb1.c linux-2.6.12.6/arch/mips/mm/c-sb1.c --- linux-2.6.12.6.orig/arch/mips/mm/c-sb1.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/c-sb1.c 2005-10-02 23:47:37.000000000 +0000 @@ -235,7 +235,7 @@ /* * Invalidate all caches on this CPU */ -static void local_sb1___flush_cache_all(void) +static void __attribute_used__ local_sb1___flush_cache_all(void) { __sb1_writeback_inv_dcache_all(); __sb1_flush_icache_all(); diff -Naur linux-2.6.12.6.orig/arch/mips/mm/c-tx39.c linux-2.6.12.6/arch/mips/mm/c-tx39.c --- linux-2.6.12.6.orig/arch/mips/mm/c-tx39.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/c-tx39.c 2005-10-02 23:47:37.000000000 +0000 @@ -183,6 +183,7 @@ int exec = vma->vm_flags & VM_EXEC; struct mm_struct *mm = vma->vm_mm; pgd_t *pgdp; + pud_t *pudp; pmd_t *pmdp; pte_t *ptep; @@ -195,7 +196,8 @@ page &= PAGE_MASK; pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); + pudp = pud_offset(pgdp, page); + pmdp = pmd_offset(pudp, page); ptep = pte_offset(pmdp, page); /* diff -Naur linux-2.6.12.6.orig/arch/mips/mm/cache.c linux-2.6.12.6/arch/mips/mm/cache.c --- linux-2.6.12.6.orig/arch/mips/mm/cache.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/cache.c 2005-10-02 23:47:37.000000000 +0000 @@ -23,8 +23,10 @@ void (*flush_cache_mm)(struct mm_struct *mm); void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, unsigned long end); -void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); -void (*flush_icache_range)(unsigned long start, unsigned long end); +void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, + unsigned long pfn); +void (*flush_icache_range)(unsigned long __user start, + unsigned long __user end); void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); /* MIPS specific cache operations */ @@ -32,6 +34,8 @@ void (*flush_data_cache_page)(unsigned long addr); void (*flush_icache_all)(void); +EXPORT_SYMBOL(flush_data_cache_page); + #ifdef CONFIG_DMA_NONCOHERENT /* DMA cache operations. */ @@ -49,10 +53,10 @@ * We could optimize the case where the cache argument is not BCACHE but * that seems very atypical use ... */ -asmlinkage int sys_cacheflush(unsigned long addr, unsigned long int bytes, - unsigned int cache) +asmlinkage int sys_cacheflush(unsigned long __user addr, + unsigned long bytes, unsigned int cache) { - if (!access_ok(VERIFY_WRITE, (void *) addr, bytes)) + if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes)) return -EFAULT; flush_icache_range(addr, addr + bytes); diff -Naur linux-2.6.12.6.orig/arch/mips/mm/dma-coherent.c linux-2.6.12.6/arch/mips/mm/dma-coherent.c --- linux-2.6.12.6.orig/arch/mips/mm/dma-coherent.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/dma-coherent.c 2005-10-02 23:47:37.000000000 +0000 @@ -9,16 +9,16 @@ */ #include #include +#include #include #include #include -#include #include #include void *dma_alloc_noncoherent(struct device *dev, size_t size, - dma_addr_t * dma_handle, int gfp) + dma_addr_t * dma_handle, unsigned int __nocast gfp) { void *ret; /* ignore region specifiers */ @@ -39,7 +39,7 @@ EXPORT_SYMBOL(dma_alloc_noncoherent); void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t * dma_handle, int gfp) + dma_addr_t * dma_handle, unsigned int __nocast gfp) __attribute__((alias("dma_alloc_noncoherent"))); EXPORT_SYMBOL(dma_alloc_coherent); diff -Naur linux-2.6.12.6.orig/arch/mips/mm/dma-ip27.c linux-2.6.12.6/arch/mips/mm/dma-ip27.c --- linux-2.6.12.6.orig/arch/mips/mm/dma-ip27.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/dma-ip27.c 2005-10-02 23:47:37.000000000 +0000 @@ -22,7 +22,7 @@ pdev_to_baddr(to_pci_dev(dev), (addr)) void *dma_alloc_noncoherent(struct device *dev, size_t size, - dma_addr_t * dma_handle, int gfp) + dma_addr_t * dma_handle, unsigned int __nocast gfp) { void *ret; @@ -44,7 +44,7 @@ EXPORT_SYMBOL(dma_alloc_noncoherent); void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t * dma_handle, int gfp) + dma_addr_t * dma_handle, unsigned int __nocast gfp) __attribute__((alias("dma_alloc_noncoherent"))); EXPORT_SYMBOL(dma_alloc_coherent); diff -Naur linux-2.6.12.6.orig/arch/mips/mm/dma-ip32.c linux-2.6.12.6/arch/mips/mm/dma-ip32.c --- linux-2.6.12.6.orig/arch/mips/mm/dma-ip32.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/dma-ip32.c 2005-10-02 23:47:37.000000000 +0000 @@ -37,7 +37,7 @@ #define RAM_OFFSET_MASK 0x3fffffff void *dma_alloc_noncoherent(struct device *dev, size_t size, - dma_addr_t * dma_handle, int gfp) + dma_addr_t * dma_handle, unsigned int __nocast gfp) { void *ret; /* ignore region specifiers */ @@ -61,7 +61,7 @@ EXPORT_SYMBOL(dma_alloc_noncoherent); void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t * dma_handle, int gfp) + dma_addr_t * dma_handle, unsigned int __nocast gfp) { void *ret; @@ -175,7 +175,7 @@ for (i = 0; i < nents; i++, sg++) { unsigned long addr; - + addr = (unsigned long) page_address(sg->page)+sg->offset; if (addr) __dma_sync(addr, sg->length, direction); @@ -251,9 +251,9 @@ size_t size, enum dma_data_direction direction) { unsigned long addr; - + BUG_ON(direction == DMA_NONE); - + dma_handle&=RAM_OFFSET_MASK; addr = dma_handle + PAGE_OFFSET; if(dma_handle>=256*1024*1024) @@ -315,9 +315,9 @@ enum dma_data_direction direction) { int i; - + BUG_ON(direction == DMA_NONE); - + /* Make sure that gcc doesn't leave the empty loop body. */ for (i = 0; i < nelems; i++, sg++) __dma_sync((unsigned long)page_address(sg->page), diff -Naur linux-2.6.12.6.orig/arch/mips/mm/dma-noncoherent.c linux-2.6.12.6/arch/mips/mm/dma-noncoherent.c --- linux-2.6.12.6.orig/arch/mips/mm/dma-noncoherent.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/dma-noncoherent.c 2005-10-02 23:47:37.000000000 +0000 @@ -24,7 +24,7 @@ */ void *dma_alloc_noncoherent(struct device *dev, size_t size, - dma_addr_t * dma_handle, int gfp) + dma_addr_t * dma_handle, unsigned int __nocast gfp) { void *ret; /* ignore region specifiers */ @@ -45,7 +45,7 @@ EXPORT_SYMBOL(dma_alloc_noncoherent); void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t * dma_handle, int gfp) + dma_addr_t * dma_handle, unsigned int __nocast gfp) { void *ret; diff -Naur linux-2.6.12.6.orig/arch/mips/mm/fault.c linux-2.6.12.6/arch/mips/mm/fault.c --- linux-2.6.12.6.orig/arch/mips/mm/fault.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/fault.c 2005-10-02 23:47:37.000000000 +0000 @@ -25,6 +25,7 @@ #include #include #include +#include /* For VMALLOC_END */ /* * This routine handles page faults. It determines the address, @@ -57,7 +58,7 @@ * only copy the information from the master page table, * nothing more. */ - if (unlikely(address >= VMALLOC_START)) + if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END)) goto vmalloc_fault; /* @@ -140,7 +141,7 @@ info.si_signo = SIGSEGV; info.si_errno = 0; /* info.si_code has been set above */ - info.si_addr = (void *) address; + info.si_addr = (void __user *) address; force_sig_info(SIGSEGV, &info, tsk); return; } @@ -196,7 +197,7 @@ info.si_signo = SIGBUS; info.si_errno = 0; info.si_code = BUS_ADRERR; - info.si_addr = (void *) address; + info.si_addr = (void __user *) address; force_sig_info(SIGBUS, &info, tsk); return; @@ -212,6 +213,7 @@ */ int offset = __pgd_offset(address); pgd_t *pgd, *pgd_k; + pud_t *pud, *pud_k; pmd_t *pmd, *pmd_k; pte_t *pte_k; @@ -222,8 +224,13 @@ goto no_context; set_pgd(pgd, *pgd_k); - pmd = pmd_offset(pgd, address); - pmd_k = pmd_offset(pgd_k, address); + pud = pud_offset(pgd, address); + pud_k = pud_offset(pgd_k, address); + if (!pud_present(*pud_k)) + goto no_context; + + pmd = pmd_offset(pud, address); + pmd_k = pmd_offset(pud_k, address); if (!pmd_present(*pmd_k)) goto no_context; set_pmd(pmd, *pmd_k); diff -Naur linux-2.6.12.6.orig/arch/mips/mm/init.c linux-2.6.12.6/arch/mips/mm/init.c --- linux-2.6.12.6.orig/arch/mips/mm/init.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/init.c 2005-10-02 23:47:37.000000000 +0000 @@ -83,7 +83,7 @@ pgprot_t kmap_prot; #define kmap_get_fixmap_pte(vaddr) \ - pte_offset_kernel(pmd_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)) + pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) static void __init kmap_init(void) { @@ -96,36 +96,42 @@ kmap_prot = PAGE_KERNEL; } -#ifdef CONFIG_MIPS64 -static void __init fixrange_init(unsigned long start, unsigned long end, +#ifdef CONFIG_MIPS32 +void __init fixrange_init(unsigned long start, unsigned long end, pgd_t *pgd_base) { pgd_t *pgd; + pud_t *pud; pmd_t *pmd; pte_t *pte; - int i, j; + int i, j, k; unsigned long vaddr; vaddr = start; i = __pgd_offset(vaddr); - j = __pmd_offset(vaddr); + j = __pud_offset(vaddr); + k = __pmd_offset(vaddr); pgd = pgd_base + i; for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) { - pmd = (pmd_t *)pgd; - for (; (j < PTRS_PER_PMD) && (vaddr != end); pmd++, j++) { - if (pmd_none(*pmd)) { - pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); - set_pmd(pmd, __pmd(pte)); - if (pte != pte_offset_kernel(pmd, 0)) - BUG(); + pud = (pud_t *)pgd; + for ( ; (j < PTRS_PER_PUD) && (vaddr != end); pud++, j++) { + pmd = (pmd_t *)pud; + for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) { + if (pmd_none(*pmd)) { + pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); + set_pmd(pmd, __pmd(pte)); + if (pte != pte_offset_kernel(pmd, 0)) + BUG(); + } + vaddr += PMD_SIZE; } - vaddr += PMD_SIZE; + k = 0; } j = 0; } } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_MIPS32 */ #endif /* CONFIG_HIGHMEM */ #ifndef CONFIG_DISCONTIGMEM diff -Naur linux-2.6.12.6.orig/arch/mips/mm/ioremap.c linux-2.6.12.6/arch/mips/mm/ioremap.c --- linux-2.6.12.6.orig/arch/mips/mm/ioremap.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/ioremap.c 2005-10-02 23:47:37.000000000 +0000 @@ -79,9 +79,14 @@ BUG(); spin_lock(&init_mm.page_table_lock); do { + pud_t *pud; pmd_t *pmd; - pmd = pmd_alloc(&init_mm, dir, address); + error = -ENOMEM; + pud = pud_alloc(&init_mm, dir, address); + if (!pud) + break; + pmd = pmd_alloc(&init_mm, pud, address); if (!pmd) break; if (remap_area_pmd(pmd, address, end - address, @@ -97,15 +102,6 @@ } /* - * Allow physical addresses to be fixed up to help 36 bit peripherals. - */ -phys_t __attribute__ ((weak)) -fixup_bigphys_addr(phys_t phys_addr, phys_t size) -{ - return phys_addr; -} - -/* * Generic mapping function (not visible outside): */ @@ -141,7 +137,7 @@ */ if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) && flags == _CACHE_UNCACHED) - return (void *) KSEG1ADDR(phys_addr); + return (void *) CKSEG1ADDR(phys_addr); /* * Don't allow anybody to remap normal RAM that we're using.. @@ -180,7 +176,7 @@ return (void *) (offset + (char *)addr); } -#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == KSEG1) +#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) void __iounmap(volatile void __iomem *addr) { diff -Naur linux-2.6.12.6.orig/arch/mips/mm/pg-sb1.c linux-2.6.12.6/arch/mips/mm/pg-sb1.c --- linux-2.6.12.6.orig/arch/mips/mm/pg-sb1.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/pg-sb1.c 2005-10-02 23:47:37.000000000 +0000 @@ -60,7 +60,8 @@ " .set noreorder \n" #ifdef CONFIG_CPU_HAS_PREFETCH " daddiu %0, %0, 128 \n" - " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n" /* Prefetch the first 4 lines */ + " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n" + /* Prefetch the first 4 lines */ " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%0) \n" " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%0) \n" " pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%0) \n" @@ -106,7 +107,8 @@ #ifdef CONFIG_CPU_HAS_PREFETCH " daddiu %0, %0, 128 \n" " daddiu %1, %1, 128 \n" - " pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n" /* Prefetch the first 4 lines */ + " pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n" + /* Prefetch the first 4 lines */ " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%1)\n" " pref " SB1_PREF_LOAD_STREAMED_HINT ", -96(%0)\n" " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%1)\n" @@ -207,66 +209,73 @@ u64 pad_b; } dmadscr_t; -static dmadscr_t page_descr[NR_CPUS] __attribute__((aligned(SMP_CACHE_BYTES))); +static dmadscr_t page_descr[DM_NUM_CHANNELS] + __attribute__((aligned(SMP_CACHE_BYTES))); void sb1_dma_init(void) { - int cpu = smp_processor_id(); - u64 base_val = CPHYSADDR(&page_descr[cpu]) | V_DM_DSCR_BASE_RINGSZ(1); + int i; - bus_writeq(base_val, - (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); - bus_writeq(base_val | M_DM_DSCR_BASE_RESET, - (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); - bus_writeq(base_val | M_DM_DSCR_BASE_ENABL, - (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); + for (i = 0; i < DM_NUM_CHANNELS; i++) { + const u64 base_val = CPHYSADDR(&page_descr[i]) | + V_DM_DSCR_BASE_RINGSZ(1); + volatile void *base_reg = + IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE)); + + __raw_writeq(base_val, base_reg); + __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg); + __raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, base_reg); + } } void clear_page(void *page) { - int cpu = smp_processor_id(); + u64 to_phys = CPHYSADDR(page); + unsigned int cpu = smp_processor_id(); - /* if the page is above Kseg0, use old way */ + /* if the page is not in KSEG0, use old way */ if ((long)KSEGX(page) != (long)CKSEG0) return clear_page_cpu(page); - page_descr[cpu].dscr_a = CPHYSADDR(page) | M_DM_DSCRA_ZERO_MEM | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; + page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM | + M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); - bus_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); + __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); /* * Don't really want to do it this way, but there's no * reliable way to delay completion detection. */ - while (!(bus_readq((void *)(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) & - M_DM_DSCR_BASE_INTERRUPT)))) + while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) + & M_DM_DSCR_BASE_INTERRUPT)) ; - bus_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); + __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); } void copy_page(void *to, void *from) { - unsigned long from_phys = CPHYSADDR(from); - unsigned long to_phys = CPHYSADDR(to); - int cpu = smp_processor_id(); + u64 from_phys = CPHYSADDR(from); + u64 to_phys = CPHYSADDR(to); + unsigned int cpu = smp_processor_id(); - /* if either page is above Kseg0, use old way */ + /* if any page is not in KSEG0, use old way */ if ((long)KSEGX(to) != (long)CKSEG0 || (long)KSEGX(from) != (long)CKSEG0) return copy_page_cpu(to, from); - page_descr[cpu].dscr_a = CPHYSADDR(to_phys) | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; - page_descr[cpu].dscr_b = CPHYSADDR(from_phys) | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); - bus_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); + page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST | + M_DM_DSCRA_INTERRUPT; + page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); + __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); /* * Don't really want to do it this way, but there's no * reliable way to delay completion detection. */ - while (!(bus_readq((void *)(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) & - M_DM_DSCR_BASE_INTERRUPT)))) + while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) + & M_DM_DSCR_BASE_INTERRUPT)) ; - bus_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); + __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); } #else /* !CONFIG_SIBYTE_DMA_PAGEOPS */ diff -Naur linux-2.6.12.6.orig/arch/mips/mm/pgtable-32.c linux-2.6.12.6/arch/mips/mm/pgtable-32.c --- linux-2.6.12.6.orig/arch/mips/mm/pgtable-32.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/pgtable-32.c 2005-10-02 23:47:37.000000000 +0000 @@ -10,6 +10,7 @@ #include #include #include +#include #include void pgd_init(unsigned long page) @@ -29,42 +30,12 @@ } } -#ifdef CONFIG_HIGHMEM -static void __init fixrange_init (unsigned long start, unsigned long end, - pgd_t *pgd_base) -{ - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - int i, j; - unsigned long vaddr; - - vaddr = start; - i = __pgd_offset(vaddr); - j = __pmd_offset(vaddr); - pgd = pgd_base + i; - - for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) { - pmd = (pmd_t *)pgd; - for (; (j < PTRS_PER_PMD) && (vaddr != end); pmd++, j++) { - if (pmd_none(*pmd)) { - pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); - set_pmd(pmd, __pmd((unsigned long)pte)); - if (pte != pte_offset_kernel(pmd, 0)) - BUG(); - } - vaddr += PMD_SIZE; - } - j = 0; - } -} -#endif - void __init pagetable_init(void) { #ifdef CONFIG_HIGHMEM unsigned long vaddr; pgd_t *pgd, *pgd_base; + pud_t *pud; pmd_t *pmd; pte_t *pte; #endif @@ -90,7 +61,8 @@ fixrange_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base); pgd = swapper_pg_dir + __pgd_offset(vaddr); - pmd = pmd_offset(pgd, vaddr); + pud = pud_offset(pgd, vaddr); + pmd = pmd_offset(pud, vaddr); pte = pte_offset_kernel(pmd, vaddr); pkmap_page_table = pte; #endif diff -Naur linux-2.6.12.6.orig/arch/mips/mm/sc-rm7k.c linux-2.6.12.6/arch/mips/mm/sc-rm7k.c --- linux-2.6.12.6.orig/arch/mips/mm/sc-rm7k.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/sc-rm7k.c 2005-10-02 23:47:37.000000000 +0000 @@ -15,6 +15,7 @@ #include #include #include +#include /* for run_uncached() */ /* Primary cache parameters. */ #define sc_lsize 32 @@ -96,25 +97,13 @@ } /* - * This function is executed in the uncached segment CKSEG1. - * It must not touch the stack, because the stack pointer still points - * into CKSEG0. - * - * Three options: - * - Write it in assembly and guarantee that we don't use the stack. - * - Disable caching for CKSEG0 before calling it. - * - Pray that GCC doesn't randomly start using the stack. - * - * This being Linux, we obviously take the least sane of those options - - * following DaveM's lead in c-r4k.c - * - * It seems we get our kicks from relying on unguaranteed behaviour in GCC + * This function is executed in uncached address space. */ static __init void __rm7k_sc_enable(void) { int i; - set_c0_config(1 << 3); /* CONF_SE */ + set_c0_config(RM7K_CONF_SE); write_c0_taglo(0); write_c0_taghi(0); @@ -127,24 +116,22 @@ ".set mips0\n\t" ".set reorder" : - : "r" (KSEG0ADDR(i)), "i" (Index_Store_Tag_SD)); + : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD)); } } static __init void rm7k_sc_enable(void) { - void (*func)(void) = (void *) KSEG1ADDR(&__rm7k_sc_enable); - - if (read_c0_config() & 0x08) /* CONF_SE */ + if (read_c0_config() & RM7K_CONF_SE) return; - printk(KERN_INFO "Enabling secondary cache..."); - func(); + printk(KERN_INFO "Enabling secondary cache...\n"); + run_uncached(__rm7k_sc_enable); } static void rm7k_sc_disable(void) { - clear_c0_config(1<<3); /* CONF_SE */ + clear_c0_config(RM7K_CONF_SE); } struct bcache_ops rm7k_sc_ops = { @@ -158,19 +145,19 @@ { unsigned int config = read_c0_config(); - if ((config >> 31) & 1) /* Bit 31 set -> no S-Cache */ + if ((config & RM7K_CONF_SC)) return; printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n", (scache_size >> 10), sc_lsize); - if (!((config >> 3) & 1)) /* CONF_SE */ + if (!(config & RM7K_CONF_SE)) rm7k_sc_enable(); /* * While we're at it let's deal with the tertiary cache. */ - if (!((config >> 17) & 1)) { + if (!(config & RM7K_CONF_TC)) { /* * We can't enable the L3 cache yet. There may be board-specific @@ -183,9 +170,9 @@ * to probe it. */ printk(KERN_INFO "Tertiary cache present, %s enabled\n", - config&(1<<12) ? "already" : "not (yet)"); + (config & RM7K_CONF_TE) ? "already" : "not (yet)"); - if ((config >> 12) & 1) + if ((config & RM7K_CONF_TE)) rm7k_tcache_enabled = 1; } diff -Naur linux-2.6.12.6.orig/arch/mips/mm/tlb-andes.c linux-2.6.12.6/arch/mips/mm/tlb-andes.c --- linux-2.6.12.6.orig/arch/mips/mm/tlb-andes.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/tlb-andes.c 2005-10-02 23:47:37.000000000 +0000 @@ -195,6 +195,7 @@ { unsigned long flags; pgd_t *pgdp; + pud_t *pudp; pmd_t *pmdp; pte_t *ptep; int idx, pid; @@ -220,7 +221,8 @@ write_c0_entryhi(address | (pid)); pgdp = pgd_offset(vma->vm_mm, address); tlb_probe(); - pmdp = pmd_offset(pgdp, address); + pudp = pud_offset(pgdp, address); + pmdp = pmd_offset(pudp, address); idx = read_c0_index(); ptep = pte_offset_map(pmdp, address); write_c0_entrylo0(pte_val(*ptep++) >> 6); diff -Naur linux-2.6.12.6.orig/arch/mips/mm/tlb-r4k.c linux-2.6.12.6/arch/mips/mm/tlb-r4k.c --- linux-2.6.12.6.orig/arch/mips/mm/tlb-r4k.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/tlb-r4k.c 2005-10-02 23:47:37.000000000 +0000 @@ -21,6 +21,12 @@ extern void build_tlb_refill_handler(void); +/* + * Make sure all entries differ. If they're not different + * MIPS32 will take revenge ... + */ +#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) + /* CP0 hazard avoidance. */ #define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ "nop; nop; nop; nop; nop; nop;\n\t" \ @@ -42,11 +48,8 @@ /* Blast 'em all away. */ while (entry < current_cpu_data.tlbsize) { - /* - * Make sure all entries differ. If they're not different - * MIPS32 will take revenge ... - */ - write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1))); + /* Make sure all entries differ. */ + write_c0_entryhi(UNIQUE_ENTRYHI(entry)); write_c0_index(entry); mtc0_tlbw_hazard(); tlb_write_indexed(); @@ -57,12 +60,21 @@ local_irq_restore(flags); } +/* All entries common to a mm share an asid. To effectively flush + these entries, we just bump the asid. */ void local_flush_tlb_mm(struct mm_struct *mm) { - int cpu = smp_processor_id(); + int cpu; + + preempt_disable(); - if (cpu_context(cpu, mm) != 0) - drop_mmu_context(mm,cpu); + cpu = smp_processor_id(); + + if (cpu_context(cpu, mm) != 0) { + drop_mmu_context(mm, cpu); + } + + preempt_enable(); } void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, @@ -75,9 +87,9 @@ unsigned long flags; int size; - local_irq_save(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; + local_irq_save(flags); if (size <= current_cpu_data.tlbsize/2) { int oldpid = read_c0_entryhi(); int newpid = cpu_asid(cpu, mm); @@ -99,8 +111,7 @@ if (idx < 0) continue; /* Make sure all entries differ. */ - write_c0_entryhi(CKSEG0 + - (idx << (PAGE_SHIFT + 1))); + write_c0_entryhi(UNIQUE_ENTRYHI(idx)); mtc0_tlbw_hazard(); tlb_write_indexed(); } @@ -118,9 +129,9 @@ unsigned long flags; int size; - local_irq_save(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; + local_irq_save(flags); if (size <= current_cpu_data.tlbsize / 2) { int pid = read_c0_entryhi(); @@ -142,7 +153,7 @@ if (idx < 0) continue; /* Make sure all entries differ. */ - write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1))); + write_c0_entryhi(UNIQUE_ENTRYHI(idx)); mtc0_tlbw_hazard(); tlb_write_indexed(); } @@ -176,7 +187,7 @@ if (idx < 0) goto finish; /* Make sure all entries differ. */ - write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1))); + write_c0_entryhi(UNIQUE_ENTRYHI(idx)); mtc0_tlbw_hazard(); tlb_write_indexed(); tlbw_use_hazard(); @@ -197,8 +208,8 @@ int oldpid, idx; local_irq_save(flags); - page &= (PAGE_MASK << 1); oldpid = read_c0_entryhi(); + page &= (PAGE_MASK << 1); write_c0_entryhi(page); mtc0_tlbw_hazard(); tlb_probe(); @@ -208,7 +219,7 @@ write_c0_entrylo1(0); if (idx >= 0) { /* Make sure all entries differ. */ - write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1))); + write_c0_entryhi(UNIQUE_ENTRYHI(idx)); mtc0_tlbw_hazard(); tlb_write_indexed(); tlbw_use_hazard(); @@ -227,6 +238,7 @@ { unsigned long flags; pgd_t *pgdp; + pud_t *pudp; pmd_t *pmdp; pte_t *ptep; int idx, pid; @@ -237,35 +249,34 @@ if (current->active_mm != vma->vm_mm) return; - pid = read_c0_entryhi() & ASID_MASK; - local_irq_save(flags); + + pid = read_c0_entryhi() & ASID_MASK; address &= (PAGE_MASK << 1); write_c0_entryhi(address | pid); pgdp = pgd_offset(vma->vm_mm, address); mtc0_tlbw_hazard(); tlb_probe(); BARRIER; - pmdp = pmd_offset(pgdp, address); + pudp = pud_offset(pgdp, address); + pmdp = pmd_offset(pudp, address); idx = read_c0_index(); ptep = pte_offset_map(pmdp, address); - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) - write_c0_entrylo0(ptep->pte_high); - ptep++; - write_c0_entrylo1(ptep->pte_high); +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) + write_c0_entrylo0(ptep->pte_high); + ptep++; + write_c0_entrylo1(ptep->pte_high); #else - write_c0_entrylo0(pte_val(*ptep++) >> 6); - write_c0_entrylo1(pte_val(*ptep) >> 6); + write_c0_entrylo0(pte_val(*ptep++) >> 6); + write_c0_entrylo1(pte_val(*ptep) >> 6); #endif - write_c0_entryhi(address | pid); mtc0_tlbw_hazard(); if (idx < 0) tlb_write_random(); else tlb_write_indexed(); tlbw_use_hazard(); - write_c0_entryhi(pid); local_irq_restore(flags); } @@ -357,7 +368,8 @@ old_pagemask = read_c0_pagemask(); wired = read_c0_wired(); if (--temp_tlb_entry < wired) { - printk(KERN_WARNING "No TLB space left for add_temporary_entry\n"); + printk(KERN_WARNING + "No TLB space left for add_temporary_entry\n"); ret = -ENOSPC; goto out; } @@ -388,7 +400,7 @@ * is not supported, we assume R4k style. Cpu probing already figured * out the number of tlb entries. */ - if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY) + if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY) return; reg = read_c0_config1(); diff -Naur linux-2.6.12.6.orig/arch/mips/mm/tlb-sb1.c linux-2.6.12.6/arch/mips/mm/tlb-sb1.c --- linux-2.6.12.6.orig/arch/mips/mm/tlb-sb1.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/tlb-sb1.c 2005-10-02 23:47:37.000000000 +0000 @@ -17,6 +17,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include #include #include #include @@ -94,7 +95,7 @@ local_irq_save(flags); /* Save old context and create impossible VPN2 value */ - old_ctx = read_c0_entryhi() & ASID_MASK; + old_ctx = read_c0_entryhi(); write_c0_entrylo0(0); write_c0_entrylo1(0); @@ -144,17 +145,17 @@ unsigned long end) { struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - int cpu; + int cpu = smp_processor_id(); - local_irq_save(flags); - cpu = smp_processor_id(); if (cpu_context(cpu, mm) != 0) { + unsigned long flags; int size; + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; + local_irq_save(flags); if (size <= (current_cpu_data.tlbsize/2)) { - int oldpid = read_c0_entryhi() & ASID_MASK; + int oldpid = read_c0_entryhi(); int newpid = cpu_asid(cpu, mm); start &= (PAGE_MASK << 1); @@ -169,17 +170,17 @@ idx = read_c0_index(); write_c0_entrylo0(0); write_c0_entrylo1(0); - write_c0_entryhi(UNIQUE_ENTRYHI(idx)); if (idx < 0) continue; + write_c0_entryhi(UNIQUE_ENTRYHI(idx)); tlb_write_indexed(); } write_c0_entryhi(oldpid); } else { drop_mmu_context(mm, cpu); } + local_irq_restore(flags); } - local_irq_restore(flags); } void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) @@ -189,7 +190,6 @@ size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; - local_irq_save(flags); if (size <= (current_cpu_data.tlbsize/2)) { int pid = read_c0_entryhi(); @@ -207,9 +207,9 @@ idx = read_c0_index(); write_c0_entrylo0(0); write_c0_entrylo1(0); - write_c0_entryhi(UNIQUE_ENTRYHI(idx)); if (idx < 0) continue; + write_c0_entryhi(UNIQUE_ENTRYHI(idx)); tlb_write_indexed(); } write_c0_entryhi(pid); @@ -221,15 +221,16 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) { - unsigned long flags; int cpu = smp_processor_id(); - local_irq_save(flags); if (cpu_context(cpu, vma->vm_mm) != 0) { + unsigned long flags; int oldpid, newpid, idx; + newpid = cpu_asid(cpu, vma->vm_mm); page &= (PAGE_MASK << 1); - oldpid = read_c0_entryhi() & ASID_MASK; + local_irq_save(flags); + oldpid = read_c0_entryhi(); write_c0_entryhi(page | newpid); tlb_probe(); idx = read_c0_index(); @@ -240,10 +241,11 @@ /* Make sure all entries differ. */ write_c0_entryhi(UNIQUE_ENTRYHI(idx)); tlb_write_indexed(); + finish: write_c0_entryhi(oldpid); + local_irq_restore(flags); } - local_irq_restore(flags); } /* @@ -255,18 +257,17 @@ unsigned long flags; int oldpid, idx; - page &= (PAGE_MASK << 1); - oldpid = read_c0_entryhi() & ASID_MASK; - local_irq_save(flags); + oldpid = read_c0_entryhi(); + page &= (PAGE_MASK << 1); write_c0_entryhi(page); tlb_probe(); idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); if (idx >= 0) { /* Make sure all entries differ. */ write_c0_entryhi(UNIQUE_ENTRYHI(idx)); - write_c0_entrylo0(0); - write_c0_entrylo1(0); tlb_write_indexed(); } @@ -297,6 +298,7 @@ { unsigned long flags; pgd_t *pgdp; + pud_t *pudp; pmd_t *pmdp; pte_t *ptep; int idx, pid; @@ -311,19 +313,26 @@ pid = read_c0_entryhi() & ASID_MASK; address &= (PAGE_MASK << 1); - write_c0_entryhi(address | (pid)); + write_c0_entryhi(address | pid); pgdp = pgd_offset(vma->vm_mm, address); tlb_probe(); - pmdp = pmd_offset(pgdp, address); + pudp = pud_offset(pgdp, address); + pmdp = pmd_offset(pudp, address); idx = read_c0_index(); ptep = pte_offset_map(pmdp, address); + +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) + write_c0_entrylo0(ptep->pte_high); + ptep++; + write_c0_entrylo1(ptep->pte_high); +#else write_c0_entrylo0(pte_val(*ptep++) >> 6); write_c0_entrylo1(pte_val(*ptep) >> 6); - if (idx < 0) { +#endif + if (idx < 0) tlb_write_random(); - } else { + else tlb_write_indexed(); - } local_irq_restore(flags); } @@ -336,7 +345,8 @@ unsigned long old_ctx; local_irq_save(flags); - old_ctx = read_c0_entryhi() & 0xff; + /* Save old context and create impossible VPN2 value */ + old_ctx = read_c0_entryhi(); old_pagemask = read_c0_pagemask(); wired = read_c0_wired(); write_c0_wired(wired + 1); diff -Naur linux-2.6.12.6.orig/arch/mips/mm/tlbex.c linux-2.6.12.6/arch/mips/mm/tlbex.c --- linux-2.6.12.6.orig/arch/mips/mm/tlbex.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/mm/tlbex.c 2005-10-02 23:47:37.000000000 +0000 @@ -6,6 +6,7 @@ * Synthesize TLB refill handlers at runtime. * * Copyright (C) 2004,2005 by Thiemo Seufer + * Copyright (C) 2005 Maciej W. Rozycki */ #include @@ -91,7 +92,7 @@ insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, - insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, + insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, @@ -134,7 +135,6 @@ { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, - { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE }, { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, { insn_j, M(j_op,0,0,0,0,0), JIMM }, @@ -366,7 +366,6 @@ I_u2u1u3(_dsll32); I_u2u1u3(_dsra); I_u2u1u3(_dsrl); -I_u2u1u3(_dsrl32); I_u3u1u2(_dsubu); I_0(_eret); I_u1(_j); @@ -412,7 +411,6 @@ label_nopage_tlbm, label_smp_pgtable_change, label_r3000_write_probe_fail, - label_r3000_write_probe_ok }; struct label { @@ -445,7 +443,6 @@ L_LA(_nopage_tlbm) L_LA(_smp_pgtable_change) L_LA(_r3000_write_probe_fail) -L_LA(_r3000_write_probe_ok) /* convenience macros for instructions */ #ifdef CONFIG_MIPS64 @@ -734,7 +731,7 @@ if (p > tlb_handler + 32) panic("TLB refill handler space exceeded"); - printk("Synthesized TLB handler (%u instructions).\n", + printk("Synthesized TLB refill handler (%u instructions).\n", (unsigned int)(p - tlb_handler)); #ifdef DEBUG_TLB { @@ -834,12 +831,19 @@ case CPU_R4700: case CPU_R5000: case CPU_R5000A: + i_nop(p); + tlbw(p); + i_nop(p); + break; + + case CPU_R4300: case CPU_5KC: case CPU_TX49XX: case CPU_AU1000: case CPU_AU1100: case CPU_AU1500: case CPU_AU1550: + case CPU_AU1200: i_nop(p); tlbw(p); break; @@ -942,34 +946,29 @@ /* No i_nop needed here, since the next insn doesn't touch TMP. */ #ifdef CONFIG_SMP +# ifdef CONFIG_BUILD_ELF64 /* - * 64 bit SMP has the lower part of &pgd_current[smp_processor_id()] + * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 * stored in CONTEXT. */ - if (in_compat_space_p(pgdc)) { - i_dmfc0(p, ptr, C0_CONTEXT); - i_dsra(p, ptr, ptr, 23); - i_ld(p, ptr, 0, ptr); - } else { -#ifdef CONFIG_BUILD_ELF64 - i_dmfc0(p, ptr, C0_CONTEXT); - i_dsrl(p, ptr, ptr, 23); - i_dsll(p, ptr, ptr, 3); - i_LA_mostly(p, tmp, pgdc); - i_daddu(p, ptr, ptr, tmp); - i_dmfc0(p, tmp, C0_BADVADDR); - i_ld(p, ptr, rel_lo(pgdc), ptr); -#else - i_dmfc0(p, ptr, C0_CONTEXT); - i_lui(p, tmp, rel_highest(pgdc)); - i_dsll(p, ptr, ptr, 9); - i_daddiu(p, tmp, tmp, rel_higher(pgdc)); - i_dsrl32(p, ptr, ptr, 0); - i_and(p, ptr, ptr, tmp); - i_dmfc0(p, tmp, C0_BADVADDR); - i_ld(p, ptr, 0, ptr); -#endif - } + i_dmfc0(p, ptr, C0_CONTEXT); + i_dsrl(p, ptr, ptr, 23); + i_LA_mostly(p, tmp, pgdc); + i_daddu(p, ptr, ptr, tmp); + i_dmfc0(p, tmp, C0_BADVADDR); + i_ld(p, ptr, rel_lo(pgdc), ptr); +# else + /* + * 64 bit SMP running in compat space has the lower part of + * &pgd_current[smp_processor_id()] stored in CONTEXT. + */ + if (!in_compat_space_p(pgdc)) + panic("Invalid page directory address!"); + + i_dmfc0(p, ptr, C0_CONTEXT); + i_dsra(p, ptr, ptr, 23); + i_ld(p, ptr, 0, ptr); +# endif #else i_LA_mostly(p, ptr, pgdc); i_ld(p, ptr, rel_lo(pgdc), ptr); @@ -1026,7 +1025,6 @@ i_mfc0(p, ptr, C0_CONTEXT); i_LA_mostly(p, tmp, pgdc); i_srl(p, ptr, ptr, 23); - i_sll(p, ptr, ptr, 2); i_addu(p, ptr, tmp, ptr); #else i_LA_mostly(p, ptr, pgdc); @@ -1245,8 +1243,15 @@ { int i; - for (i = 0; i < 64; i++) - printk("%08x\n", final_handler[i]); + f = final_handler; +#ifdef CONFIG_MIPS64 + if (final_len > 32) + final_len = 64; + else + f = final_handler + 32; +#endif /* CONFIG_MIPS64 */ + for (i = 0; i < final_len; i++) + printk("%08x\n", f[i]); } #endif @@ -1256,7 +1261,7 @@ /* * TLB load/store/modify handlers. - * + * * Only the fastpath gets synthesized at runtime, the slowpath for * do_page_fault remains normal asm. */ @@ -1277,37 +1282,41 @@ u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; static void __init -iPTE_LW(u32 **p, struct label **l, unsigned int pte, int offset, - unsigned int ptr) +iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr) { #ifdef CONFIG_SMP # ifdef CONFIG_64BIT_PHYS_ADDR if (cpu_has_64bits) - i_lld(p, pte, offset, ptr); + i_lld(p, pte, 0, ptr); else # endif - i_LL(p, pte, offset, ptr); + i_LL(p, pte, 0, ptr); #else # ifdef CONFIG_64BIT_PHYS_ADDR if (cpu_has_64bits) - i_ld(p, pte, offset, ptr); + i_ld(p, pte, 0, ptr); else # endif - i_LW(p, pte, offset, ptr); + i_LW(p, pte, 0, ptr); #endif } static void __init -iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, int offset, - unsigned int ptr) +iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr, + unsigned int mode) { +#ifdef CONFIG_64BIT_PHYS_ADDR + unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); +#endif + + i_ori(p, pte, pte, mode); #ifdef CONFIG_SMP # ifdef CONFIG_64BIT_PHYS_ADDR if (cpu_has_64bits) - i_scd(p, pte, offset, ptr); + i_scd(p, pte, 0, ptr); else # endif - i_SC(p, pte, offset, ptr); + i_SC(p, pte, 0, ptr); if (r10000_llsc_war()) il_beqzl(p, r, pte, label_smp_pgtable_change); @@ -1318,7 +1327,7 @@ if (!cpu_has_64bits) { /* no i_nop needed */ i_ll(p, pte, sizeof(pte_t) / 2, ptr); - i_ori(p, pte, pte, _PAGE_VALID); + i_ori(p, pte, pte, hwmode); i_sc(p, pte, sizeof(pte_t) / 2, ptr); il_beqz(p, r, pte, label_smp_pgtable_change); /* no i_nop needed */ @@ -1331,15 +1340,15 @@ #else # ifdef CONFIG_64BIT_PHYS_ADDR if (cpu_has_64bits) - i_sd(p, pte, offset, ptr); + i_sd(p, pte, 0, ptr); else # endif - i_SW(p, pte, offset, ptr); + i_SW(p, pte, 0, ptr); # ifdef CONFIG_64BIT_PHYS_ADDR if (!cpu_has_64bits) { i_lw(p, pte, sizeof(pte_t) / 2, ptr); - i_ori(p, pte, pte, _PAGE_VALID); + i_ori(p, pte, pte, hwmode); i_sw(p, pte, sizeof(pte_t) / 2, ptr); i_lw(p, pte, 0, ptr); } @@ -1359,7 +1368,7 @@ i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); il_bnez(p, r, pte, lid); - iPTE_LW(p, l, pte, 0, ptr); + iPTE_LW(p, l, pte, ptr); } /* Make PTE valid, store result in PTR. */ @@ -1367,8 +1376,9 @@ build_make_valid(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr) { - i_ori(p, pte, pte, _PAGE_VALID | _PAGE_ACCESSED); - iPTE_SW(p, r, pte, 0, ptr); + unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; + + iPTE_SW(p, r, pte, ptr, mode); } /* @@ -1382,7 +1392,7 @@ i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); il_bnez(p, r, pte, lid); - iPTE_LW(p, l, pte, 0, ptr); + iPTE_LW(p, l, pte, ptr); } /* Make PTE writable, update software status bits as well, then store @@ -1392,9 +1402,10 @@ build_make_write(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr) { - i_ori(p, pte, pte, - _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); - iPTE_SW(p, r, pte, 0, ptr); + unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID + | _PAGE_DIRTY); + + iPTE_SW(p, r, pte, ptr, mode); } /* @@ -1407,41 +1418,48 @@ { i_andi(p, pte, pte, _PAGE_WRITE); il_beqz(p, r, pte, lid); - iPTE_LW(p, l, pte, 0, ptr); + iPTE_LW(p, l, pte, ptr); } /* * R3000 style TLB load/store/modify handlers. */ -/* This places the pte in the page table at PTR into ENTRYLO0. */ +/* + * This places the pte into ENTRYLO0 and writes it with tlbwi. + * Then it returns. + */ static void __init -build_r3000_pte_reload(u32 **p, unsigned int ptr) +build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) { - i_lw(p, ptr, 0, ptr); - i_nop(p); /* load delay */ - i_mtc0(p, ptr, C0_ENTRYLO0); - i_nop(p); /* cp0 delay */ + i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ + i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ + i_tlbwi(p); + i_jr(p, tmp); + i_rfe(p); /* branch delay */ } /* - * The index register may have the probe fail bit set, - * because we would trap on access kseg2, i.e. without refill. + * This places the pte into ENTRYLO0 and writes it with tlbwi + * or tlbwr as appropriate. This is because the index register + * may have the probe fail bit set as a result of a trap on a + * kseg2 access, i.e. without refill. Then it returns. */ static void __init -build_r3000_tlb_write(u32 **p, struct label **l, struct reloc **r, - unsigned int tmp) +build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r, + unsigned int pte, unsigned int tmp) { i_mfc0(p, tmp, C0_INDEX); - i_nop(p); /* cp0 delay */ - il_bltz(p, r, tmp, label_r3000_write_probe_fail); - i_nop(p); /* branch delay */ - i_tlbwi(p); - il_b(p, r, label_r3000_write_probe_ok); - i_nop(p); /* branch delay */ + i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ + il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ + i_mfc0(p, tmp, C0_EPC); /* branch delay */ + i_tlbwi(p); /* cp0 delay */ + i_jr(p, tmp); + i_rfe(p); /* branch delay */ l_r3000_write_probe_fail(l, *p); - i_tlbwr(p); - l_r3000_write_probe_ok(l, *p); + i_tlbwr(p); /* cp0 delay */ + i_jr(p, tmp); + i_rfe(p); /* branch delay */ } static void __init @@ -1461,17 +1479,7 @@ i_andi(p, pte, pte, 0xffc); /* load delay */ i_addu(p, ptr, ptr, pte); i_lw(p, pte, 0, ptr); - i_nop(p); /* load delay */ - i_tlbp(p); -} - -static void __init -build_r3000_tlbchange_handler_tail(u32 **p, unsigned int tmp) -{ - i_mfc0(p, tmp, C0_EPC); - i_nop(p); /* cp0 delay */ - i_jr(p, tmp); - i_rfe(p); /* branch delay */ + i_tlbp(p); /* load delay */ } static void __init build_r3000_tlb_load_handler(void) @@ -1486,10 +1494,9 @@ build_r3000_tlbchange_handler_head(&p, K0, K1); build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); + i_nop(&p); /* load delay */ build_make_valid(&p, &r, K0, K1); - build_r3000_pte_reload(&p, K1); - build_r3000_tlb_write(&p, &l, &r, K0); - build_r3000_tlbchange_handler_tail(&p, K0); + build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); l_nopage_tlbl(&l, p); i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); @@ -1506,7 +1513,7 @@ { int i; - for (i = 0; i < FASTPATH_SIZE; i++) + for (i = 0; i < (p - handle_tlbl); i++) printk("%08x\n", handle_tlbl[i]); } #endif @@ -1527,10 +1534,9 @@ build_r3000_tlbchange_handler_head(&p, K0, K1); build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); + i_nop(&p); /* load delay */ build_make_write(&p, &r, K0, K1); - build_r3000_pte_reload(&p, K1); - build_r3000_tlb_write(&p, &l, &r, K0); - build_r3000_tlbchange_handler_tail(&p, K0); + build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); l_nopage_tlbs(&l, p); i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); @@ -1547,7 +1553,7 @@ { int i; - for (i = 0; i < FASTPATH_SIZE; i++) + for (i = 0; i < (p - handle_tlbs); i++) printk("%08x\n", handle_tlbs[i]); } #endif @@ -1568,10 +1574,9 @@ build_r3000_tlbchange_handler_head(&p, K0, K1); build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); + i_nop(&p); /* load delay */ build_make_write(&p, &r, K0, K1); - build_r3000_pte_reload(&p, K1); - i_tlbwi(&p); - build_r3000_tlbchange_handler_tail(&p, K0); + build_r3000_pte_reload_tlbwi(&p, K0, K1); l_nopage_tlbm(&l, p); i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); @@ -1588,7 +1593,7 @@ { int i; - for (i = 0; i < FASTPATH_SIZE; i++) + for (i = 0; i < (p - handle_tlbm); i++) printk("%08x\n", handle_tlbm[i]); } #endif @@ -1620,7 +1625,7 @@ #ifdef CONFIG_SMP l_smp_pgtable_change(l, *p); # endif - iPTE_LW(p, l, pte, 0, ptr); /* get even pte */ + iPTE_LW(p, l, pte, ptr); /* get even pte */ build_tlb_probe_entry(p); } @@ -1680,7 +1685,7 @@ { int i; - for (i = 0; i < FASTPATH_SIZE; i++) + for (i = 0; i < (p - handle_tlbl); i++) printk("%08x\n", handle_tlbl[i]); } #endif @@ -1719,7 +1724,7 @@ { int i; - for (i = 0; i < FASTPATH_SIZE; i++) + for (i = 0; i < (p - handle_tlbs); i++) printk("%08x\n", handle_tlbs[i]); } #endif @@ -1759,7 +1764,7 @@ { int i; - for (i = 0; i < FASTPATH_SIZE; i++) + for (i = 0; i < (p - handle_tlbm); i++) printk("%08x\n", handle_tlbm[i]); } #endif diff -Naur linux-2.6.12.6.orig/arch/mips/momentum/Kconfig linux-2.6.12.6/arch/mips/momentum/Kconfig --- linux-2.6.12.6.orig/arch/mips/momentum/Kconfig 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/momentum/Kconfig 2005-10-02 23:47:37.000000000 +0000 @@ -0,0 +1,6 @@ +config JAGUAR_DMALOW + bool "Low DMA Mode" + depends on MOMENCO_JAGUAR_ATX + help + Select to Y if jump JP5 is set on your board, N otherwise. Normally + the jumper is set, so if you feel unsafe, just say Y. diff -Naur linux-2.6.12.6.orig/arch/mips/momentum/jaguar_atx/setup.c linux-2.6.12.6/arch/mips/momentum/jaguar_atx/setup.c --- linux-2.6.12.6.orig/arch/mips/momentum/jaguar_atx/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/momentum/jaguar_atx/setup.c 2005-10-02 23:47:37.000000000 +0000 @@ -351,7 +351,7 @@ arch_initcall(ja_pci_init); -static int __init momenco_jaguar_atx_setup(void) +int __init plat_setup(void) { unsigned int tmpword; @@ -467,8 +467,4 @@ } #endif - - return 0; } - -early_initcall(momenco_jaguar_atx_setup); diff -Naur linux-2.6.12.6.orig/arch/mips/momentum/ocelot_3/setup.c linux-2.6.12.6/arch/mips/momentum/ocelot_3/setup.c --- linux-2.6.12.6.orig/arch/mips/momentum/ocelot_3/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/momentum/ocelot_3/setup.c 2005-10-02 23:47:37.000000000 +0000 @@ -307,7 +307,7 @@ arch_initcall(ja_pci_init); -static int __init momenco_ocelot_3_setup(void) +int __init plat_setup(void) { unsigned int tmpword; @@ -391,8 +391,4 @@ /* Support for 128 MB memory */ add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM); - - return 0; } - -early_initcall(momenco_ocelot_3_setup); diff -Naur linux-2.6.12.6.orig/arch/mips/momentum/ocelot_c/cpci-irq.c linux-2.6.12.6/arch/mips/momentum/ocelot_c/cpci-irq.c --- linux-2.6.12.6.orig/arch/mips/momentum/ocelot_c/cpci-irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/momentum/ocelot_c/cpci-irq.c 2005-10-02 23:47:37.000000000 +0000 @@ -129,14 +129,13 @@ #define shutdown_cpci_irq disable_cpci_irq struct hw_interrupt_type cpci_irq_type = { - "CPCI/FPGA", - startup_cpci_irq, - shutdown_cpci_irq, - enable_cpci_irq, - disable_cpci_irq, - mask_and_ack_cpci_irq, - end_cpci_irq, - NULL + .typename = "CPCI/FPGA", + .startup = startup_cpci_irq, + .shutdown = shutdown_cpci_irq, + .enable = enable_cpci_irq, + .disable = disable_cpci_irq, + .ack = mask_and_ack_cpci_irq, + .end = end_cpci_irq, }; void cpci_irq_init(void) diff -Naur linux-2.6.12.6.orig/arch/mips/momentum/ocelot_c/setup.c linux-2.6.12.6/arch/mips/momentum/ocelot_c/setup.c --- linux-2.6.12.6.orig/arch/mips/momentum/ocelot_c/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/momentum/ocelot_c/setup.c 2005-10-02 23:47:37.000000000 +0000 @@ -222,7 +222,7 @@ rtc_set_time = m48t37y_set_time; } -static void __init momenco_ocelot_c_setup(void) +void __init plat_setup(void) { unsigned int tmpword; @@ -340,8 +340,6 @@ } } -early_initcall(momenco_ocelot_c_setup); - #ifndef CONFIG_MIPS64 /* This needs to be one of the first initcalls, because no I/O port access can work before this */ diff -Naur linux-2.6.12.6.orig/arch/mips/momentum/ocelot_c/uart-irq.c linux-2.6.12.6/arch/mips/momentum/ocelot_c/uart-irq.c --- linux-2.6.12.6.orig/arch/mips/momentum/ocelot_c/uart-irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/momentum/ocelot_c/uart-irq.c 2005-10-02 23:47:37.000000000 +0000 @@ -122,14 +122,13 @@ #define shutdown_uart_irq disable_uart_irq struct hw_interrupt_type uart_irq_type = { - "UART/FPGA", - startup_uart_irq, - shutdown_uart_irq, - enable_uart_irq, - disable_uart_irq, - mask_and_ack_uart_irq, - end_uart_irq, - NULL + .typename = "UART/FPGA", + .startup = startup_uart_irq, + .shutdown = shutdown_uart_irq, + .enable = enable_uart_irq, + .disable = disable_uart_irq, + .ack = mask_and_ack_uart_irq, + .end = end_uart_irq, }; void uart_irq_init(void) diff -Naur linux-2.6.12.6.orig/arch/mips/momentum/ocelot_g/setup.c linux-2.6.12.6/arch/mips/momentum/ocelot_g/setup.c --- linux-2.6.12.6.orig/arch/mips/momentum/ocelot_g/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/momentum/ocelot_g/setup.c 2005-10-02 23:47:37.000000000 +0000 @@ -160,7 +160,7 @@ printk("Done\n"); } -static int __init momenco_ocelot_g_setup(void) +int __init plat_setup(void) { void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache); unsigned int tmpword; @@ -240,12 +240,8 @@ /* FIXME: Fix up the DiskOnChip mapping */ MV_WRITE(0x468, 0xfef73); - - return 0; } -early_initcall(momenco_ocelot_g_setup); - /* This needs to be one of the first initcalls, because no I/O port access can work before this */ diff -Naur linux-2.6.12.6.orig/arch/mips/oprofile/Kconfig linux-2.6.12.6/arch/mips/oprofile/Kconfig --- linux-2.6.12.6.orig/arch/mips/oprofile/Kconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/oprofile/Kconfig 2005-10-02 23:47:37.000000000 +0000 @@ -7,7 +7,7 @@ help Say Y here to enable the extended profiling support mechanisms used by profilers such as OProfile. - + config OPROFILE tristate "OProfile system profiling (EXPERIMENTAL)" diff -Naur linux-2.6.12.6.orig/arch/mips/oprofile/common.c linux-2.6.12.6/arch/mips/oprofile/common.c --- linux-2.6.12.6.orig/arch/mips/oprofile/common.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/oprofile/common.c 2005-10-02 23:47:37.000000000 +0000 @@ -68,9 +68,18 @@ on_each_cpu(model->cpu_stop, NULL, 0, 1); } -void __init oprofile_arch_init(struct oprofile_operations *ops) +static struct oprofile_operations oprof_mips_ops = { + .create_files = op_mips_create_files, + .setup = op_mips_setup, + .start = op_mips_start, + .stop = op_mips_stop, + .cpu_type = NULL +}; + +int __init oprofile_arch_init(struct oprofile_operations **ops) { struct op_mips_model *lmodel = NULL; + int res; switch (current_cpu_data.cputype) { case CPU_24K: @@ -83,21 +92,21 @@ }; if (!lmodel) - return; + return -ENODEV; - if (lmodel->init()) - return; + res = lmodel->init(); + if (res) + return res; model = lmodel; - ops->create_files = op_mips_create_files; - ops->setup = op_mips_setup; - ops->start = op_mips_start; - ops->stop = op_mips_stop; - ops->cpu_type = lmodel->cpu_type; + oprof_mips_ops.cpu_type = lmodel->cpu_type; + *ops = &oprof_mips_ops; printk(KERN_INFO "oprofile: using %s performance monitoring.\n", lmodel->cpu_type); + + return 0; } void oprofile_arch_exit(void) diff -Naur linux-2.6.12.6.orig/arch/mips/oprofile/op_model_rm9000.c linux-2.6.12.6/arch/mips/oprofile/op_model_rm9000.c --- linux-2.6.12.6.orig/arch/mips/oprofile/op_model_rm9000.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/oprofile/op_model_rm9000.c 2005-10-02 23:47:37.000000000 +0000 @@ -5,6 +5,7 @@ * * Copyright (C) 2004 by Ralf Baechle */ +#include #include #include #include @@ -114,7 +115,7 @@ return IRQ_HANDLED; } -static int rm9000_init(void) +static int __init rm9000_init(void) { return request_irq(rm9000_perfcount_irq, rm9000_perfcount_handler, 0, "Perfcounter", NULL); diff -Naur linux-2.6.12.6.orig/arch/mips/pci/fixup-atlas.c linux-2.6.12.6/arch/mips/pci/fixup-atlas.c --- linux-2.6.12.6.orig/arch/mips/pci/fixup-atlas.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pci/fixup-atlas.c 2005-10-02 23:47:37.000000000 +0000 @@ -1,14 +1,37 @@ +/* + * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * Author: Maciej W. Rozycki + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ #include #include #include + #include -#define INTD ATLASINT_INTD -#define INTC ATLASINT_INTC -#define INTB ATLASINT_INTB +#define PCIA ATLASINT_PCIA +#define PCIB ATLASINT_PCIB +#define PCIC ATLASINT_PCIC +#define PCID ATLASINT_PCID #define INTA ATLASINT_INTA -#define SCSI ATLASINT_SCSI +#define INTB ATLASINT_INTB #define ETH ATLASINT_ETH +#define INTC ATLASINT_INTC +#define SCSI ATLASINT_SCSI +#define INTD ATLASINT_INTD static char irq_tab[][5] __initdata = { /* INTA INTB INTC INTD */ @@ -27,13 +50,13 @@ {0, 0, 0, 0, 0 }, /* 12: Unused */ {0, 0, 0, 0, 0 }, /* 13: Unused */ {0, 0, 0, 0, 0 }, /* 14: Unused */ - {0, 0, 0, 0, 0 }, /* 15: Unused */ + {0, PCIA, PCIB, PCIC, PCID }, /* 15: cPCI (behind 21150) */ {0, SCSI, 0, 0, 0 }, /* 16: SYM53C810A SCSI */ {0, 0, 0, 0, 0 }, /* 17: Core */ - {0, INTA, INTB, INTC, INTD }, /* 18: PCI Slot 1 */ - {0, ETH, 0, 0, 0 }, /* 19: SAA9730 Ethernet */ - {0, 0, 0, 0, 0 }, /* 20: PCI Slot 3 */ - {0, 0, 0, 0, 0 } /* 21: PCI Slot 4 */ + {0, INTA, INTB, INTC, INTD }, /* 18: PCI Slot */ + {0, ETH, 0, 0, 0 }, /* 19: SAA9730 Eth. et al. */ + {0, 0, 0, 0, 0 }, /* 20: Unused */ + {0, 0, 0, 0, 0 } /* 21: Unused */ }; int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) diff -Naur linux-2.6.12.6.orig/arch/mips/pci/fixup-au1000.c linux-2.6.12.6/arch/mips/pci/fixup-au1000.c --- linux-2.6.12.6.orig/arch/mips/pci/fixup-au1000.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pci/fixup-au1000.c 2005-10-02 23:47:37.000000000 +0000 @@ -26,7 +26,6 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include #include #include #include @@ -34,82 +33,7 @@ #include -/* - * Shortcut - */ -#ifdef CONFIG_SOC_AU1500 -#define INTA AU1000_PCI_INTA -#define INTB AU1000_PCI_INTB -#define INTC AU1000_PCI_INTC -#define INTD AU1000_PCI_INTD -#endif - -#ifdef CONFIG_SOC_AU1550 -#define INTA AU1550_PCI_INTA -#define INTB AU1550_PCI_INTB -#define INTC AU1550_PCI_INTC -#define INTD AU1550_PCI_INTD -#endif - -#define INTX 0xFF /* not valid */ - -#ifdef CONFIG_MIPS_DB1500 -static char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT371 */ - [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ -}; -#endif - -#ifdef CONFIG_MIPS_BOSPORUS -static char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 11 - miniPCI */ - [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - SN1741 */ - [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ -}; -#endif - -#ifdef CONFIG_MIPS_MIRAGE -static char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, INTD, INTX, INTX, INTX}, /* IDSEL 11 - SMI VGX */ - [12] = { -1, INTX, INTX, INTC, INTX}, /* IDSEL 12 - PNX1300 */ - [13] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 13 - miniPCI */ -}; -#endif - -#ifdef CONFIG_MIPS_DB1550 -static char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, INTC, INTX, INTX, INTX}, /* IDSEL 11 - on-board HPT371 */ - [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */ - [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */ -}; -#endif - -#ifdef CONFIG_MIPS_PB1500 -static char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT370 */ - [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ -}; -#endif - -#ifdef CONFIG_MIPS_PB1550 -static char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */ - [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */ -}; -#endif - -#ifdef CONFIG_MIPS_MTX1 -static char irq_tab_alchemy[][5] __initdata = { - [0] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 00 - AdapterA-Slot0 (top) */ - [1] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 01 - AdapterA-Slot1 (bottom) */ - [2] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 02 - AdapterB-Slot0 (top) */ - [3] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 03 - AdapterB-Slot1 (bottom) */ - [4] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 04 - AdapterC-Slot0 (top) */ - [5] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 05 - AdapterC-Slot1 (bottom) */ - [6] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 06 - AdapterD-Slot0 (top) */ - [7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */ -}; -#endif +extern char irq_tab_alchemy[][5]; int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { diff -Naur linux-2.6.12.6.orig/arch/mips/pci/fixup-cobalt.c linux-2.6.12.6/arch/mips/pci/fixup-cobalt.c --- linux-2.6.12.6.orig/arch/mips/pci/fixup-cobalt.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pci/fixup-cobalt.c 2005-10-02 23:47:37.000000000 +0000 @@ -21,6 +21,20 @@ extern int cobalt_board_id; +static void qube_raq_galileo_early_fixup(struct pci_dev *dev) +{ + if (dev->devfn == PCI_DEVFN(0, 0) && + (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) { + + dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff); + + printk(KERN_INFO "Galileo: fixed bridge class\n"); + } +} + +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, + qube_raq_galileo_early_fixup); + static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) { unsigned short cfgword; @@ -48,6 +62,9 @@ { unsigned short galileo_id; + if (dev->devfn != PCI_DEVFN(0, 0)) + return; + /* Fix PCI latency-timer and cache-line-size values in Galileo * host bridge. */ @@ -55,6 +72,13 @@ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); /* + * The code described by the comment below has been removed + * as it causes bus mastering by the Ethernet controllers + * to break under any kind of network load. We always set + * the retry timeouts to their maximum. + * + * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x-- + * * On all machines prior to Q2, we had the STOP line disconnected * from Galileo to VIA on PCI. The new Galileo does not function * correctly unless we have it connected. @@ -64,21 +88,43 @@ */ pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id); galileo_id &= 0xff; /* mask off class info */ + + printk(KERN_INFO "Galileo: revision %u\n", galileo_id); + +#if 0 if (galileo_id >= 0x10) { /* New Galileo, assumes PCI stop line to VIA is connected. */ GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS); - } else if (galileo_id == 0x1 || galileo_id == 0x2) { + } else if (galileo_id == 0x1 || galileo_id == 0x2) +#endif + { signed int timeo; /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ timeo = GALILEO_INL(GT_PCI0_TOR_OFS); /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ - GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS); + GALILEO_OUTL( + (0xff << 16) | /* retry count */ + (0xff << 8) | /* timeout 1 */ + 0xff, /* timeout 0 */ + GT_PCI0_TOR_OFS); + + /* enable PCI retry exceeded interrupt */ + GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); } } -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, qube_raq_galileo_fixup); +static char irq_tab_qube1[] __initdata = { + [COBALT_PCICONF_CPU] = 0, + [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ, + [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, + [COBALT_PCICONF_VIA] = 0, + [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, + [COBALT_PCICONF_ETH1] = 0 +}; + static char irq_tab_cobalt[] __initdata = { [COBALT_PCICONF_CPU] = 0, [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, @@ -99,6 +145,9 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { + if (cobalt_board_id < COBALT_BRD_ID_QUBE2) + return irq_tab_qube1[slot]; + if (cobalt_board_id == COBALT_BRD_ID_RAQ2) return irq_tab_raq2[slot]; diff -Naur linux-2.6.12.6.orig/arch/mips/pci/fixup-vr4133.c linux-2.6.12.6/arch/mips/pci/fixup-vr4133.c --- linux-2.6.12.6.orig/arch/mips/pci/fixup-vr4133.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pci/fixup-vr4133.c 2005-10-02 23:47:37.000000000 +0000 @@ -11,9 +11,9 @@ * is licensed "as is" without any warranty of any kind, whether express * or implied. * - * Modified for support in 2.6 + * Modified for support in 2.6 * Author: Manish Lachwani (mlachwani@mvista.com) - * + * */ #include #include @@ -29,21 +29,21 @@ /* Do platform specific device initialization at pci_enable_device() time */ int pcibios_plat_dev_init(struct pci_dev *dev) { - /* + /* * We have to reset AMD PCnet adapter on Rockhopper since * PMON leaves it enabled and generating interrupts. This leads * to a lock if some PCI device driver later enables the IRQ line * shared with PCnet and there is no AMD PCnet driver to catch its - * interrupts. + * interrupts. */ #ifdef CONFIG_ROCKHOPPER - if (dev->vendor == PCI_VENDOR_ID_AMD && + if (dev->vendor == PCI_VENDOR_ID_AMD && dev->device == PCI_DEVICE_ID_AMD_LANCE) { inl(pci_resource_start(dev, 0) + 0x18); } #endif - /* + /* * we have to open the bridges' windows down to 0 because otherwise * we cannot access ISA south bridge I/O registers that get mapped from * 0. for example, 8259 PIC would be unaccessible without that @@ -60,8 +60,8 @@ return 0; } -/* - * M1535 IRQ mapping +/* + * M1535 IRQ mapping * Feel free to change this, although it shouldn't be needed */ #define M1535_IRQ_INTA 7 @@ -124,7 +124,7 @@ {1, ROCKHOPPER_PCI2_SLOT, M1535_IRQ_INTC}, /* PCI slot #2 */ {1, ROCKHOPPER_M5237_SLOT, M1535_IRQ_USB}, /* USB host controller */ {1, ROCKHOPPER_M5229_SLOT, IDE_PRIMARY_IRQ}, /* IDE controller */ - {2, ROCKHOPPER_PCNET_SLOT, M1535_IRQ_INTD}, /* AMD Am79c973 on-board + {2, ROCKHOPPER_PCNET_SLOT, M1535_IRQ_INTD}, /* AMD Am79c973 on-board ethernet */ {2, ROCKHOPPER_PCI3_SLOT, M1535_IRQ_INTB}, /* PCI slot #3 */ {2, ROCKHOPPER_PCI4_SLOT, M1535_IRQ_INTC} /* PCI slot #4 */ diff -Naur linux-2.6.12.6.orig/arch/mips/pci/ops-au1000.c linux-2.6.12.6/arch/mips/pci/ops-au1000.c --- linux-2.6.12.6.orig/arch/mips/pci/ops-au1000.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pci/ops-au1000.c 2005-10-02 23:47:37.000000000 +0000 @@ -50,11 +50,6 @@ int (*board_pci_idsel)(unsigned int devsel, int assert); -/* CP0 hazard avoidance. */ -#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ - "nop; nop; nop; nop;\t" \ - ".set reorder\n\t") - void mod_wired_entry(int entry, unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask) @@ -66,16 +61,12 @@ old_ctx = read_c0_entryhi() & 0xff; old_pagemask = read_c0_pagemask(); write_c0_index(entry); - BARRIER; write_c0_pagemask(pagemask); write_c0_entryhi(entryhi); write_c0_entrylo0(entrylo0); write_c0_entrylo1(entrylo1); - BARRIER; tlb_write_indexed(); - BARRIER; write_c0_entryhi(old_ctx); - BARRIER; write_c0_pagemask(old_pagemask); } @@ -128,9 +119,8 @@ last_entryLo0 = last_entryLo1 = 0xffffffff; } - /* Since the Au1xxx doesn't do the idsel timing exactly to spec, - * many board vendors implement their own off-chip idsel, so call - * it now. If it doesn't succeed, may as well bail out at this point. + /* Allow board vendors to implement their own off-chip idsel. + * If it doesn't succeed, may as well bail out at this point. */ if (board_pci_idsel) { if (board_pci_idsel(device, 1) == 0) { diff -Naur linux-2.6.12.6.orig/arch/mips/pci/ops-bonito64.c linux-2.6.12.6/arch/mips/pci/ops-bonito64.c --- linux-2.6.12.6.orig/arch/mips/pci/ops-bonito64.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pci/ops-bonito64.c 2005-10-02 23:47:37.000000000 +0000 @@ -1,6 +1,8 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -17,7 +19,6 @@ * * MIPS boards specific PCI support. */ -#include #include #include #include @@ -57,13 +58,6 @@ return -1; } -#ifdef CONFIG_MIPS_BOARDS_GEN - if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) { - /* MIPS Core boards have Bonito connected as device 17 */ - return -1; - } -#endif - /* Clear cause register bits */ BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR | BONITO_PCICMD_MTABORT_CLR); diff -Naur linux-2.6.12.6.orig/arch/mips/pci/ops-gt64111.c linux-2.6.12.6/arch/mips/pci/ops-gt64111.c --- linux-2.6.12.6.orig/arch/mips/pci/ops-gt64111.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pci/ops-gt64111.c 2005-10-02 23:47:37.000000000 +0000 @@ -18,15 +18,15 @@ #include /* - * Accessing device 31 hangs the GT64120. Not sure if this will also hang - * the GT64111, let's be paranoid for now. + * Device 31 on the GT64111 is used to generate PCI special + * cycles, so we shouldn't expected to find a device there ... */ static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn) { - if (bus->number == 0 && devfn == PCI_DEVFN(31, 0)) - return -1; + if (bus->number == 0 && PCI_SLOT(devfn) < 31) + return 0; - return 0; + return -1; } static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn, diff -Naur linux-2.6.12.6.orig/arch/mips/pci/ops-gt64120.c linux-2.6.12.6/arch/mips/pci/ops-gt64120.c --- linux-2.6.12.6.orig/arch/mips/pci/ops-gt64120.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pci/ops-gt64120.c 2005-10-02 23:47:37.000000000 +0000 @@ -1,6 +1,8 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -43,10 +45,6 @@ unsigned char busnum = bus->number; u32 intr; - if ((busnum == 0) && (PCI_SLOT(devfn) == 0)) - /* Galileo itself is devfn 0, don't move it around */ - return -1; - if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0))) return -1; /* Because of a bug in the galileo (for slot 31). */ diff -Naur linux-2.6.12.6.orig/arch/mips/pci/ops-msc.c linux-2.6.12.6/arch/mips/pci/ops-msc.c --- linux-2.6.12.6.orig/arch/mips/pci/ops-msc.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pci/ops-msc.c 2005-10-02 23:47:37.000000000 +0000 @@ -1,8 +1,8 @@ /* * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) * * This program is free software; you can distribute it and/or modify it @@ -21,7 +21,6 @@ * MIPS boards specific PCI support. * */ -#include #include #include #include @@ -49,34 +48,17 @@ struct pci_bus *bus, unsigned int devfn, int where, u32 * data) { unsigned char busnum = bus->number; - unsigned char type; u32 intr; -#ifdef CONFIG_MIPS_BOARDS_GEN - if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) { - /* MIPS Core boards have SOCit connected as device 17 */ - return -1; - } -#endif - /* Clear status register bits. */ MSC_WRITE(MSC01_PCI_INTSTAT, (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)); - /* Setup address */ - if (busnum == 0) - type = 0; /* Type 0 */ - else - type = 1; /* Type 1 */ - MSC_WRITE(MSC01_PCI_CFGADDR, ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) | - (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) - | (PCI_FUNC(devfn) << - MSC01_PCI_CFGADDR_FNUM_SHF) | ((where / - 4) << - MSC01_PCI_CFGADDR_RNUM_SHF) - | (type))); + (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) | + (PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) | + ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF))); /* Perform access */ if (access_type == PCI_ACCESS_WRITE) @@ -86,15 +68,12 @@ /* Detect Master/Target abort */ MSC_READ(MSC01_PCI_INTSTAT, intr); - if (intr & (MSC01_PCI_INTCFG_MA_BIT | - MSC01_PCI_INTCFG_TA_BIT)) { + if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) { /* Error occurred */ /* Clear bits */ - MSC_READ(MSC01_PCI_INTSTAT, intr); MSC_WRITE(MSC01_PCI_INTSTAT, - (MSC01_PCI_INTCFG_MA_BIT | - MSC01_PCI_INTCFG_TA_BIT)); + (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)); return -1; } diff -Naur linux-2.6.12.6.orig/arch/mips/pci/ops-tx4927.c linux-2.6.12.6/arch/mips/pci/ops-tx4927.c --- linux-2.6.12.6.orig/arch/mips/pci/ops-tx4927.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pci/ops-tx4927.c 2005-10-02 23:47:37.000000000 +0000 @@ -120,7 +120,7 @@ switch (size) { case 1: *val = *(volatile u8 *) ((ulong) & tx4927_pcicptr-> - g2pcfgdata | + g2pcfgdata | #ifdef __LITTLE_ENDIAN (where & 3)); #else @@ -129,7 +129,7 @@ break; case 2: *val = *(volatile u16 *) ((ulong) & tx4927_pcicptr-> - g2pcfgdata | + g2pcfgdata | #ifdef __LITTLE_ENDIAN (where & 3)); #else @@ -169,7 +169,7 @@ switch (size) { case 1: *(volatile u8 *) ((ulong) & tx4927_pcicptr-> - g2pcfgdata | + g2pcfgdata | #ifdef __LITTLE_ENDIAN (where & 3)) = val; #else @@ -179,7 +179,7 @@ case 2: *(volatile u16 *) ((ulong) & tx4927_pcicptr-> - g2pcfgdata | + g2pcfgdata | #ifdef __LITTLE_ENDIAN (where & 3)) = val; #else diff -Naur linux-2.6.12.6.orig/arch/mips/pci/pci-ip32.c linux-2.6.12.6/arch/mips/pci/pci-ip32.c --- linux-2.6.12.6.orig/arch/mips/pci/pci-ip32.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pci/pci-ip32.c 2005-10-02 23:47:37.000000000 +0000 @@ -136,7 +136,9 @@ BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0, "MACE PCI error", NULL)); - ioport_resource.end = mace_pci_io_resource.end; + iomem_resource = mace_pci_mem_resource; + ioport_resource = mace_pci_io_resource; + register_pci_controller(&mace_pci_controller); return 0; diff -Naur linux-2.6.12.6.orig/arch/mips/pci/pci-lasat.c linux-2.6.12.6/arch/mips/pci/pci-lasat.c --- linux-2.6.12.6.orig/arch/mips/pci/pci-lasat.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pci/pci-lasat.c 2005-10-02 23:47:37.000000000 +0000 @@ -7,12 +7,8 @@ */ #include #include -#include #include #include -#include -#include -#include #include extern struct pci_ops nile4_pci_ops; @@ -20,14 +16,14 @@ static struct resource lasat_pci_mem_resource = { .name = "LASAT PCI MEM", .start = 0x18000000, - .end = 0x19FFFFFF, + .end = 0x19ffffff, .flags = IORESOURCE_MEM, }; static struct resource lasat_pci_io_resource = { .name = "LASAT PCI IO", .start = 0x1a000000, - .end = 0x1bFFFFFF, + .end = 0x1bffffff, .flags = IORESOURCE_IO, }; @@ -38,23 +34,25 @@ static int __init lasat_pci_setup(void) { - printk("PCI: starting\n"); + printk("PCI: starting\n"); - switch (mips_machtype) { - case MACH_LASAT_100: + switch (mips_machtype) { + case MACH_LASAT_100: lasat_pci_controller.pci_ops = >64120_pci_ops; break; - case MACH_LASAT_200: + case MACH_LASAT_200: lasat_pci_controller.pci_ops = &nile4_pci_ops; break; - default: + default: panic("pcibios_init: mips_machtype incorrect"); } register_pci_controller(&lasat_pci_controller); - return 0; + + return 0; } -early_initcall(lasat_pci_setup); + +arch_initcall(lasat_pci_setup); #define LASATINT_ETH1 0 #define LASATINT_ETH0 1 @@ -68,24 +66,22 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - switch (slot) { - case 1: - return LASATINT_PCIA; /* Expansion Module 0 */ - case 2: - return LASATINT_PCIB; /* Expansion Module 1 */ - case 3: - return LASATINT_PCIC; /* Expansion Module 2 */ - case 4: - return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */ - case 5: - return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */ - case 6: - return LASATINT_HDC; /* IDE controller */ - default: - return 0xff; /* Illegal */ - } + switch (slot) { + case 1: + case 2: + case 3: + return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4); + case 4: + return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */ + case 5: + return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */ + case 6: + return LASATINT_HDC; /* IDE controller */ + default: + return 0xff; /* Illegal */ + } - return -1; + return -1; } /* Do platform specific device initialization at pci_enable_device() time */ diff -Naur linux-2.6.12.6.orig/arch/mips/pci/pci-vr41xx.c linux-2.6.12.6/arch/mips/pci/pci-vr41xx.c --- linux-2.6.12.6.orig/arch/mips/pci/pci-vr41xx.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pci/pci-vr41xx.c 2005-10-02 23:47:37.000000000 +0000 @@ -123,10 +123,8 @@ return -EBUSY; pciu_base = ioremap(PCIU_BASE, PCIU_SIZE); - if (pciu_base == NULL) { - release_mem_region(PCIU_BASE, PCIU_SIZE); + if (pciu_base == NULL) return -EBUSY; - } /* Disable PCI interrupt */ vr41xx_disable_pciint(); diff -Naur linux-2.6.12.6.orig/arch/mips/pmc-sierra/Kconfig linux-2.6.12.6/arch/mips/pmc-sierra/Kconfig --- linux-2.6.12.6.orig/arch/mips/pmc-sierra/Kconfig 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pmc-sierra/Kconfig 2005-10-02 23:47:37.000000000 +0000 @@ -0,0 +1,3 @@ +config HYPERTRANSPORT + bool "Hypertransport Support for PMC-Sierra Yosemite" + depends on PMC_YOSEMITE diff -Naur linux-2.6.12.6.orig/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h linux-2.6.12.6/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h --- linux-2.6.12.6.orig/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h 2005-10-02 23:47:37.000000000 +0000 @@ -34,7 +34,6 @@ #include #include #include -#include #include #include #include diff -Naur linux-2.6.12.6.orig/arch/mips/pmc-sierra/yosemite/ht-irq.c linux-2.6.12.6/arch/mips/pmc-sierra/yosemite/ht-irq.c --- linux-2.6.12.6.orig/arch/mips/pmc-sierra/yosemite/ht-irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pmc-sierra/yosemite/ht-irq.c 2005-10-02 23:47:37.000000000 +0000 @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff -Naur linux-2.6.12.6.orig/arch/mips/pmc-sierra/yosemite/ht.c linux-2.6.12.6/arch/mips/pmc-sierra/yosemite/ht.c --- linux-2.6.12.6.orig/arch/mips/pmc-sierra/yosemite/ht.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pmc-sierra/yosemite/ht.c 2005-10-02 23:47:37.000000000 +0000 @@ -28,7 +28,6 @@ #include #include #include -#include #include #include diff -Naur linux-2.6.12.6.orig/arch/mips/pmc-sierra/yosemite/setup.c linux-2.6.12.6/arch/mips/pmc-sierra/yosemite/setup.c --- linux-2.6.12.6.orig/arch/mips/pmc-sierra/yosemite/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/pmc-sierra/yosemite/setup.c 2005-10-02 23:47:37.000000000 +0000 @@ -212,7 +212,7 @@ py_rtc_setup(); } -static int __init pmc_yosemite_setup(void) +void __init plat_setup(void) { board_time_init = yosemite_time_init; late_time_init = py_late_time_init; @@ -228,8 +228,4 @@ OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR); OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0); #endif - - return 0; } - -early_initcall(pmc_yosemite_setup); diff -Naur linux-2.6.12.6.orig/arch/mips/sgi-ip22/ip22-eisa.c linux-2.6.12.6/arch/mips/sgi-ip22/ip22-eisa.c --- linux-2.6.12.6.orig/arch/mips/sgi-ip22/ip22-eisa.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sgi-ip22/ip22-eisa.c 2005-10-02 23:47:37.000000000 +0000 @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -37,42 +38,29 @@ #include #include -#define EISA_MAX_SLOTS 4 +/* I2 has four EISA slots. */ +#define IP22_EISA_MAX_SLOTS 4 #define EISA_MAX_IRQ 16 -#define EISA_TO_PHYS(x) (0x00080000 | (x)) -#define EISA_TO_KSEG1(x) ((void *) KSEG1ADDR(EISA_TO_PHYS((x)))) +#define EIU_MODE_REG 0x0001ffc0 +#define EIU_STAT_REG 0x0001ffc4 +#define EIU_PREMPT_REG 0x0001ffc8 +#define EIU_QUIET_REG 0x0001ffcc +#define EIU_INTRPT_ACK 0x00010004 + +static char __init *decode_eisa_sig(unsigned long addr) +{ + static char sig_str[EISA_SIG_LEN]; + u8 sig[4]; + u16 rev; + int i; -#define EIU_MODE_REG 0x0009ffc0 -#define EIU_STAT_REG 0x0009ffc4 -#define EIU_PREMPT_REG 0x0009ffc8 -#define EIU_QUIET_REG 0x0009ffcc -#define EIU_INTRPT_ACK 0x00090004 - -#define EISA_DMA1_STATUS 8 -#define EISA_INT1_CTRL 0x20 -#define EISA_INT1_MASK 0x21 -#define EISA_INT2_CTRL 0xA0 -#define EISA_INT2_MASK 0xA1 -#define EISA_DMA2_STATUS 0xD0 -#define EISA_DMA2_WRITE_SINGLE 0xD4 -#define EISA_EXT_NMI_RESET_CTRL 0x461 -#define EISA_INT1_EDGE_LEVEL 0x4D0 -#define EISA_INT2_EDGE_LEVEL 0x4D1 -#define EISA_VENDOR_ID_OFFSET 0xC80 - -#define EIU_WRITE_32(x,y) { *((u32 *) KSEG1ADDR(x)) = (u32) (y); mb(); } -#define EIU_READ_8(x) *((u8 *) KSEG1ADDR(x)) -#define EISA_WRITE_8(x,y) { *((u8 *) EISA_TO_KSEG1(x)) = (u8) (y); mb(); } -#define EISA_READ_8(x) *((u8 *) EISA_TO_KSEG1(x)) + for (i = 0; i < 4; i++) { + sig[i] = inb (addr + i); -static char *decode_eisa_sig(u8 * sig) -{ - static char sig_str[8]; - u16 rev; - - if (sig[0] & 0x80) - return NULL; + if (!i && (sig[0] & 0x80)) + return NULL; + } sig_str[0] = ((sig[0] >> 2) & 0x1f) + ('A' - 1); sig_str[1] = (((sig[0] & 3) << 3) | (sig[1] >> 5)) + ('A' - 1); @@ -83,23 +71,26 @@ return sig_str; } -static void ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs) +static irqreturn_t ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs) { u8 eisa_irq; u8 dma1, dma2; - eisa_irq = EIU_READ_8(EIU_INTRPT_ACK); - dma1 = EISA_READ_8(EISA_DMA1_STATUS); - dma2 = EISA_READ_8(EISA_DMA2_STATUS); - - if (eisa_irq >= EISA_MAX_IRQ) { - /* Oops, Bad Stuff Happened... */ - printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq); - - EISA_WRITE_8(EISA_INT2_CTRL, 0x20); - EISA_WRITE_8(EISA_INT1_CTRL, 0x20); - } else + eisa_irq = inb(EIU_INTRPT_ACK); + dma1 = inb(EISA_DMA1_STATUS); + dma2 = inb(EISA_DMA2_STATUS); + + if (eisa_irq < EISA_MAX_IRQ) { do_IRQ(eisa_irq, regs); + return IRQ_HANDLED; + } + + /* Oops, Bad Stuff Happened... */ + printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq); + + outb(0x20, EISA_INT2_CTRL); + outb(0x20, EISA_INT1_CTRL); + return IRQ_NONE; } static void enable_eisa1_irq(unsigned int irq) @@ -109,9 +100,9 @@ local_irq_save(flags); - mask = EISA_READ_8(EISA_INT1_MASK); + mask = inb(EISA_INT1_MASK); mask &= ~((u8) (1 << irq)); - EISA_WRITE_8(EISA_INT1_MASK, mask); + outb(mask, EISA_INT1_MASK); local_irq_restore(flags); } @@ -122,9 +113,9 @@ /* Only use edge interrupts for EISA */ - edge = EISA_READ_8(EISA_INT1_EDGE_LEVEL); + edge = inb(EISA_INT1_EDGE_LEVEL); edge &= ~((u8) (1 << irq)); - EISA_WRITE_8(EISA_INT1_EDGE_LEVEL, edge); + outb(edge, EISA_INT1_EDGE_LEVEL); enable_eisa1_irq(irq); return 0; @@ -134,9 +125,9 @@ { u8 mask; - mask = EISA_READ_8(EISA_INT1_MASK); + mask = inb(EISA_INT1_MASK); mask |= ((u8) (1 << irq)); - EISA_WRITE_8(EISA_INT1_MASK, mask); + outb(mask, EISA_INT1_MASK); } #define shutdown_eisa1_irq disable_eisa1_irq @@ -145,7 +136,7 @@ { disable_eisa1_irq(irq); - EISA_WRITE_8(EISA_INT1_CTRL, 0x20); + outb(0x20, EISA_INT1_CTRL); } static void end_eisa1_irq(unsigned int irq) @@ -171,9 +162,9 @@ local_irq_save(flags); - mask = EISA_READ_8(EISA_INT2_MASK); + mask = inb(EISA_INT2_MASK); mask &= ~((u8) (1 << (irq - 8))); - EISA_WRITE_8(EISA_INT2_MASK, mask); + outb(mask, EISA_INT2_MASK); local_irq_restore(flags); } @@ -184,9 +175,9 @@ /* Only use edge interrupts for EISA */ - edge = EISA_READ_8(EISA_INT2_EDGE_LEVEL); + edge = inb(EISA_INT2_EDGE_LEVEL); edge &= ~((u8) (1 << (irq - 8))); - EISA_WRITE_8(EISA_INT2_EDGE_LEVEL, edge); + outb(edge, EISA_INT2_EDGE_LEVEL); enable_eisa2_irq(irq); return 0; @@ -196,9 +187,9 @@ { u8 mask; - mask = EISA_READ_8(EISA_INT2_MASK); + mask = inb(EISA_INT2_MASK); mask |= ((u8) (1 << (irq - 8))); - EISA_WRITE_8(EISA_INT2_MASK, mask); + outb(mask, EISA_INT2_MASK); } #define shutdown_eisa2_irq disable_eisa2_irq @@ -207,8 +198,7 @@ { disable_eisa2_irq(irq); - EISA_WRITE_8(EISA_INT2_CTRL, 0x20); - EISA_WRITE_8(EISA_INT1_CTRL, 0x20); + outb(0x20, EISA_INT2_CTRL); } static void end_eisa2_irq(unsigned int irq) @@ -241,7 +231,6 @@ { int i, c; char *str; - u8 *slot_addr; if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) { printk(KERN_INFO "EISA: bus not present.\n"); @@ -249,11 +238,8 @@ } printk(KERN_INFO "EISA: Probing bus...\n"); - for (c = 0, i = 1; i <= EISA_MAX_SLOTS; i++) { - slot_addr = - (u8 *) EISA_TO_KSEG1((0x1000 * i) + - EISA_VENDOR_ID_OFFSET); - if ((str = decode_eisa_sig(slot_addr))) { + for (c = 0, i = 1; i <= IP22_EISA_MAX_SLOTS; i++) { + if ((str = decode_eisa_sig(0x1000 * i + EISA_VENDOR_ID_OFFSET))) { printk(KERN_INFO "EISA: slot %d : %s detected.\n", i, str); c++; @@ -268,25 +254,25 @@ Please wave your favorite dead chicken over the busses */ /* First say hello to the EIU */ - EIU_WRITE_32(EIU_PREMPT_REG, 0x0000FFFF); - EIU_WRITE_32(EIU_QUIET_REG, 1); - EIU_WRITE_32(EIU_MODE_REG, 0x40f3c07F); + outl(0x0000FFFF, EIU_PREMPT_REG); + outl(1, EIU_QUIET_REG); + outl(0x40f3c07F, EIU_MODE_REG); /* Now be nice to the EISA chipset */ - EISA_WRITE_8(EISA_EXT_NMI_RESET_CTRL, 1); - for (i = 0; i < 10000; i++); /* Wait long enough for the dust to settle */ - EISA_WRITE_8(EISA_EXT_NMI_RESET_CTRL, 0); - EISA_WRITE_8(EISA_INT1_CTRL, 0x11); - EISA_WRITE_8(EISA_INT2_CTRL, 0x11); - EISA_WRITE_8(EISA_INT1_MASK, 0); - EISA_WRITE_8(EISA_INT2_MASK, 8); - EISA_WRITE_8(EISA_INT1_MASK, 4); - EISA_WRITE_8(EISA_INT2_MASK, 2); - EISA_WRITE_8(EISA_INT1_MASK, 1); - EISA_WRITE_8(EISA_INT2_MASK, 1); - EISA_WRITE_8(EISA_INT1_MASK, 0xfb); - EISA_WRITE_8(EISA_INT2_MASK, 0xff); - EISA_WRITE_8(EISA_DMA2_WRITE_SINGLE, 0); + outb(1, EISA_EXT_NMI_RESET_CTRL); + udelay(50); /* Wait long enough for the dust to settle */ + outb(0, EISA_EXT_NMI_RESET_CTRL); + outb(0x11, EISA_INT1_CTRL); + outb(0x11, EISA_INT2_CTRL); + outb(0, EISA_INT1_MASK); + outb(8, EISA_INT2_MASK); + outb(4, EISA_INT1_MASK); + outb(2, EISA_INT2_MASK); + outb(1, EISA_INT1_MASK); + outb(1, EISA_INT2_MASK); + outb(0xfb, EISA_INT1_MASK); + outb(0xff, EISA_INT2_MASK); + outb(0, EISA_DMA2_WRITE_SINGLE); for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) { irq_desc[i].status = IRQ_DISABLED; diff -Naur linux-2.6.12.6.orig/arch/mips/sgi-ip22/ip22-setup.c linux-2.6.12.6/arch/mips/sgi-ip22/ip22-setup.c --- linux-2.6.12.6.orig/arch/mips/sgi-ip22/ip22-setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sgi-ip22/ip22-setup.c 2005-10-02 23:47:37.000000000 +0000 @@ -53,9 +53,10 @@ extern void ip22_be_init(void) __init; extern void ip22_time_init(void) __init; -static int __init ip22_setup(void) +void __init plat_setup(void) { char *ctype; + char *cserial; board_be_init = ip22_be_init; ip22_time_init(); @@ -81,9 +82,14 @@ /* ARCS console environment variable is set to "g?" for * graphics console, it is set to "d" for the first serial * line and "d2" for the second serial line. + * + * Need to check if the case is 'g' but no keyboard: + * (ConsoleIn/Out = serial) */ ctype = ArcGetEnvironmentVariable("console"); - if (ctype && *ctype == 'd') { + cserial = ArcGetEnvironmentVariable("ConsoleOut"); + + if ((ctype && *ctype == 'd') || (cserial && *cserial == 's')) { static char options[8]; char *baud = ArcGetEnvironmentVariable("dbaud"); if (baud) @@ -91,7 +97,7 @@ add_preferred_console("ttyS", *(ctype + 1) == '2' ? 1 : 0, baud ? options : NULL); } else if (!ctype || *ctype != 'g') { - /* Use ARC if we don't want serial ('d') or Newport ('g'). */ + /* Use ARC if we don't want serial ('d') or graphics ('g'). */ prom_flags |= PROM_FLAG_USE_AS_CONSOLE; add_preferred_console("arc", 0, NULL); } @@ -137,8 +143,4 @@ } } #endif - - return 0; } - -early_initcall(ip22_setup); diff -Naur linux-2.6.12.6.orig/arch/mips/sgi-ip27/Kconfig linux-2.6.12.6/arch/mips/sgi-ip27/Kconfig --- linux-2.6.12.6.orig/arch/mips/sgi-ip27/Kconfig 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sgi-ip27/Kconfig 2005-10-02 23:47:37.000000000 +0000 @@ -0,0 +1,54 @@ +#config SGI_SN0_XXL +# bool "IP27 XXL" +# depends on SGI_IP27 +# This options adds support for userspace processes upto 16TB size. +# Normally the limit is just .5TB. + +config SGI_SN0_N_MODE + bool "IP27 N-Mode" + depends on SGI_IP27 + help + The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be + configured in either N-Modes which allows for more nodes or M-Mode + which allows for more memory. Your system is most probably + running in M-Mode, so you should say N here. + +config DISCONTIGMEM + bool + default y if SGI_IP27 + help + Say Y to upport efficient handling of discontiguous physical memory, + for architectures which are either NUMA (Non-Uniform Memory Access) + or have huge holes in the physical address space for other reasons. + See for more. + +config NUMA + bool "NUMA Support" + depends on SGI_IP27 + help + Say Y to compile the kernel to support NUMA (Non-Uniform Memory + Access). This option is for configuring high-end multiprocessor + server machines. If in doubt, say N. + +config MAPPED_KERNEL + bool "Mapped kernel support" + depends on SGI_IP27 + help + Change the way a Linux kernel is loaded into memory on a MIPS64 + machine. This is required in order to support text replication and + NUMA. If you need to understand it, read the source code. + +config REPLICATE_KTEXT + bool "Kernel text replication support" + depends on SGI_IP27 + help + Say Y here to enable replicating the kernel text across multiple + nodes in a NUMA cluster. This trades memory for speed. + +config REPLICATE_EXHANDLERS + bool "Exception handler replication support" + depends on SGI_IP27 + help + Say Y here to enable replicating the kernel exception handlers + across multiple nodes in a NUMA cluster. This trades memory for + speed. diff -Naur linux-2.6.12.6.orig/arch/mips/sgi-ip27/ip27-console.c linux-2.6.12.6/arch/mips/sgi-ip27/ip27-console.c --- linux-2.6.12.6.orig/arch/mips/sgi-ip27/ip27-console.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sgi-ip27/ip27-console.c 2005-10-02 23:47:37.000000000 +0000 @@ -30,8 +30,10 @@ static inline struct ioc3_uartregs *console_uart(void) { struct ioc3 *ioc3; + nasid_t nasid; - ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(get_nasid())->memory_base; + nasid = (master_nasid == INVALID_NASID) ? get_nasid() : master_nasid; + ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(nasid)->memory_base; return &ioc3->sregs.uarta; } diff -Naur linux-2.6.12.6.orig/arch/mips/sgi-ip27/ip27-init.c linux-2.6.12.6/arch/mips/sgi-ip27/ip27-init.c --- linux-2.6.12.6.orig/arch/mips/sgi-ip27/ip27-init.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sgi-ip27/ip27-init.c 2005-10-02 23:47:37.000000000 +0000 @@ -56,12 +56,12 @@ { struct hub_data *hub = hub_data(cnode); nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode); + int i; cpu_set(smp_processor_id(), hub->h_cpus); if (test_and_set_bit(cnode, hub_init_mask)) return; - /* * Set CRB timeout at 5ms, (< PI timeout of 10ms) */ @@ -88,6 +88,24 @@ __flush_cache_all(); } #endif + + /* + * Some interrupts are reserved by hardware or by software convention. + * Mark these as reserved right away so they won't be used accidently + * later. + */ + for (i = 0; i <= BASE_PCI_IRQ; i++) { + __set_bit(i, hub->irq_alloc_mask); + LOCAL_HUB_CLR_INTR(INT_PEND0_BASELVL + i); + } + + __set_bit(IP_PEND0_6_63, hub->irq_alloc_mask); + LOCAL_HUB_S(PI_INT_PEND_MOD, IP_PEND0_6_63); + + for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) { + __set_bit(i, hub->irq_alloc_mask); + LOCAL_HUB_CLR_INTR(INT_PEND1_BASELVL + i); + } } void __init per_cpu_init(void) @@ -104,30 +122,12 @@ clear_c0_status(ST0_IM); + per_hub_init(cnode); + for (i = 0; i < LEVELS_PER_SLICE; i++) si->level_to_irq[i] = -1; /* - * Some interrupts are reserved by hardware or by software convention. - * Mark these as reserved right away so they won't be used accidently - * later. - */ - for (i = 0; i <= BASE_PCI_IRQ; i++) { - __set_bit(i, si->irq_alloc_mask); - LOCAL_HUB_S(PI_INT_PEND_MOD, i); - } - - __set_bit(IP_PEND0_6_63, si->irq_alloc_mask); - LOCAL_HUB_S(PI_INT_PEND_MOD, IP_PEND0_6_63); - - for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) { - __set_bit(i, si->irq_alloc_mask + 1); - LOCAL_HUB_S(PI_INT_PEND_MOD, i); - } - - LOCAL_HUB_L(PI_INT_PEND0); - - /* * We use this so we can find the local hub's data as fast as only * possible. */ @@ -140,8 +140,6 @@ install_cpu_nmi_handler(cputoslice(cpu)); set_c0_status(SRB_DEV0 | SRB_DEV1); - - per_hub_init(cnode); } /* @@ -198,7 +196,7 @@ extern void ip27_time_init(void); extern void ip27_reboot_setup(void); -static int __init ip27_setup(void) +void __init plat_setup(void) { hubreg_t p, e, n_mode; nasid_t nid; @@ -248,5 +246,3 @@ return 0; } - -early_initcall(ip27_setup); diff -Naur linux-2.6.12.6.orig/arch/mips/sgi-ip27/ip27-irq.c linux-2.6.12.6/arch/mips/sgi-ip27/ip27-irq.c --- linux-2.6.12.6.orig/arch/mips/sgi-ip27/ip27-irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sgi-ip27/ip27-irq.c 2005-10-02 23:47:37.000000000 +0000 @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -74,14 +73,15 @@ static inline int alloc_level(int cpu, int irq) { + struct hub_data *hub = hub_data(cpu_to_node(cpu)); struct slice_data *si = cpu_data[cpu].data; - int level; /* pre-allocated entries */ + int level; - level = find_first_zero_bit(si->irq_alloc_mask, LEVELS_PER_SLICE); + level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE); if (level >= LEVELS_PER_SLICE) panic("Cpu %d flooded with devices\n", cpu); - __set_bit(level, si->irq_alloc_mask); + __set_bit(level, hub->irq_alloc_mask); si->level_to_irq[level] = irq; return level; @@ -216,9 +216,11 @@ { nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); struct slice_data *si = cpu_data[cpu].data; + unsigned long flags; - __set_bit(bit, si->irq_enable_mask); + set_bit(bit, si->irq_enable_mask); + local_irq_save(flags); if (!cputoslice(cpu)) { REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); @@ -226,6 +228,7 @@ REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); } + local_irq_restore(flags); return 0; } @@ -235,7 +238,7 @@ nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); struct slice_data *si = cpu_data[cpu].data; - __clear_bit(bit, si->irq_enable_mask); + clear_bit(bit, si->irq_enable_mask); if (!cputoslice(cpu)) { REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); @@ -298,6 +301,7 @@ static void shutdown_bridge_irq(unsigned int irq) { struct bridge_controller *bc = IRQ_TO_BRIDGE(irq); + struct hub_data *hub = hub_data(cpu_to_node(bc->irq_cpu)); bridge_t *bridge = bc->base; struct slice_data *si = cpu_data[bc->irq_cpu].data; int pin, swlevel; @@ -313,7 +317,7 @@ swlevel = find_level(&cpu, irq); intr_disconnect_level(cpu, swlevel); - __clear_bit(swlevel, si->irq_alloc_mask); + __clear_bit(swlevel, hub->irq_alloc_mask); si->level_to_irq[swlevel] = -1; bridge->b_int_enable &= ~(1 << pin); @@ -433,25 +437,24 @@ int slice = LOCAL_HUB_L(PI_CPU_NUM); int cpu = smp_processor_id(); struct slice_data *si = cpu_data[cpu].data; - hubreg_t mask, set; + struct hub_data *hub = hub_data(cpu_to_node(cpu)); + int resched, call; + + resched = CPU_RESCHED_A_IRQ + slice; + __set_bit(resched, hub->irq_alloc_mask); + __set_bit(resched, si->irq_enable_mask); + LOCAL_HUB_CLR_INTR(resched); + + call = CPU_CALL_A_IRQ + slice; + __set_bit(call, hub->irq_alloc_mask); + __set_bit(call, si->irq_enable_mask); + LOCAL_HUB_CLR_INTR(call); if (slice == 0) { - LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ); - LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ); - mask = LOCAL_HUB_L(PI_INT_MASK0_A); /* Slice A */ - set = (1UL << CPU_RESCHED_A_IRQ) | (1UL << CPU_CALL_A_IRQ); - mask |= set; - si->irq_enable_mask[0] |= set; - si->irq_alloc_mask[0] |= set; - LOCAL_HUB_S(PI_INT_MASK0_A, mask); + LOCAL_HUB_S(PI_INT_MASK0_A, si->irq_enable_mask[0]); + LOCAL_HUB_S(PI_INT_MASK1_A, si->irq_enable_mask[1]); } else { - LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ); - LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ); - mask = LOCAL_HUB_L(PI_INT_MASK0_B); /* Slice B */ - set = (1UL << CPU_RESCHED_B_IRQ) | (1UL << CPU_CALL_B_IRQ); - mask |= set; - si->irq_enable_mask[1] |= set; - si->irq_alloc_mask[1] |= set; - LOCAL_HUB_S(PI_INT_MASK0_B, mask); + LOCAL_HUB_S(PI_INT_MASK0_B, si->irq_enable_mask[0]); + LOCAL_HUB_S(PI_INT_MASK1_B, si->irq_enable_mask[1]); } } diff -Naur linux-2.6.12.6.orig/arch/mips/sgi-ip27/ip27-smp.c linux-2.6.12.6/arch/mips/sgi-ip27/ip27-smp.c --- linux-2.6.12.6.orig/arch/mips/sgi-ip27/ip27-smp.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sgi-ip27/ip27-smp.c 2005-10-02 23:47:37.000000000 +0000 @@ -127,37 +127,28 @@ printk("Discovered %d cpus on %d nodes\n", highest + 1, num_online_nodes()); } -static void intr_clear_bits(nasid_t nasid, volatile hubreg_t *pend, - int base_level) +static __init void intr_clear_all(nasid_t nasid) { - volatile hubreg_t bits; int i; - /* Check pending interrupts */ - if ((bits = HUB_L(pend)) != 0) - for (i = 0; i < N_INTPEND_BITS; i++) - if (bits & (1 << i)) - LOCAL_HUB_CLR_INTR(base_level + i); -} - -static void intr_clear_all(nasid_t nasid) -{ REMOTE_HUB_S(nasid, PI_INT_MASK0_A, 0); REMOTE_HUB_S(nasid, PI_INT_MASK0_B, 0); REMOTE_HUB_S(nasid, PI_INT_MASK1_A, 0); REMOTE_HUB_S(nasid, PI_INT_MASK1_B, 0); - intr_clear_bits(nasid, REMOTE_HUB_ADDR(nasid, PI_INT_PEND0), - INT_PEND0_BASELVL); - intr_clear_bits(nasid, REMOTE_HUB_ADDR(nasid, PI_INT_PEND1), - INT_PEND1_BASELVL); + + for (i = 0; i < 128; i++) + REMOTE_HUB_CLR_INTR(nasid, i); } void __init prom_prepare_cpus(unsigned int max_cpus) { cnodeid_t cnode; - for_each_online_node(cnode) + for_each_online_node(cnode) { + if (cnode == 0) + continue; intr_clear_all(COMPACT_TO_NASID_NODEID(cnode)); + } replicate_kernel_text(); diff -Naur linux-2.6.12.6.orig/arch/mips/sgi-ip32/crime.c linux-2.6.12.6/arch/mips/sgi-ip32/crime.c --- linux-2.6.12.6.orig/arch/mips/sgi-ip32/crime.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sgi-ip32/crime.c 2005-10-02 23:47:37.000000000 +0000 @@ -26,7 +26,7 @@ unsigned int id, rev; const int field = 2 * sizeof(unsigned long); - set_io_port_base((unsigned long) ioremap(MACEPCI_LOW_IO, 0x2000000)); + set_io_port_base((unsigned long) ioremap(MACEPCI_LOW_IO, 0x2000000)); crime = ioremap(CRIME_BASE, sizeof(struct sgi_crime)); mace = ioremap(MACE_BASE, sizeof(struct sgi_mace)); diff -Naur linux-2.6.12.6.orig/arch/mips/sgi-ip32/ip32-irq.c linux-2.6.12.6/arch/mips/sgi-ip32/ip32-irq.c --- linux-2.6.12.6.orig/arch/mips/sgi-ip32/ip32-irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sgi-ip32/ip32-irq.c 2005-10-02 23:47:37.000000000 +0000 @@ -163,14 +163,13 @@ #define mask_and_ack_cpu_irq disable_cpu_irq static struct hw_interrupt_type ip32_cpu_interrupt = { - "IP32 CPU", - startup_cpu_irq, - shutdown_cpu_irq, - enable_cpu_irq, - disable_cpu_irq, - mask_and_ack_cpu_irq, - end_cpu_irq, - NULL + .typename = "IP32 CPU", + .startup = startup_cpu_irq, + .shutdown = shutdown_cpu_irq, + .enable = enable_cpu_irq, + .disable = disable_cpu_irq, + .ack = mask_and_ack_cpu_irq, + .end = end_cpu_irq, }; /* @@ -234,14 +233,13 @@ #define shutdown_crime_irq disable_crime_irq static struct hw_interrupt_type ip32_crime_interrupt = { - "IP32 CRIME", - startup_crime_irq, - shutdown_crime_irq, - enable_crime_irq, - disable_crime_irq, - mask_and_ack_crime_irq, - end_crime_irq, - NULL + .typename = "IP32 CRIME", + .startup = startup_crime_irq, + .shutdown = shutdown_crime_irq, + .enable = enable_crime_irq, + .disable = disable_crime_irq, + .ack = mask_and_ack_crime_irq, + .end = end_crime_irq, }; /* @@ -294,14 +292,13 @@ #define mask_and_ack_macepci_irq disable_macepci_irq static struct hw_interrupt_type ip32_macepci_interrupt = { - "IP32 MACE PCI", - startup_macepci_irq, - shutdown_macepci_irq, - enable_macepci_irq, - disable_macepci_irq, - mask_and_ack_macepci_irq, - end_macepci_irq, - NULL + .typename = "IP32 MACE PCI", + .startup = startup_macepci_irq, + .shutdown = shutdown_macepci_irq, + .enable = enable_macepci_irq, + .disable = disable_macepci_irq, + .ack = mask_and_ack_macepci_irq, + .end = end_macepci_irq, }; /* This is used for MACE ISA interrupts. That means bits 4-6 in the @@ -425,14 +422,13 @@ #define shutdown_maceisa_irq disable_maceisa_irq static struct hw_interrupt_type ip32_maceisa_interrupt = { - "IP32 MACE ISA", - startup_maceisa_irq, - shutdown_maceisa_irq, - enable_maceisa_irq, - disable_maceisa_irq, - mask_and_ack_maceisa_irq, - end_maceisa_irq, - NULL + .typename = "IP32 MACE ISA", + .startup = startup_maceisa_irq, + .shutdown = shutdown_maceisa_irq, + .enable = enable_maceisa_irq, + .disable = disable_maceisa_irq, + .ack = mask_and_ack_maceisa_irq, + .end = end_maceisa_irq, }; /* This is used for regular non-ISA, non-PCI MACE interrupts. That means @@ -476,14 +472,13 @@ #define mask_and_ack_mace_irq disable_mace_irq static struct hw_interrupt_type ip32_mace_interrupt = { - "IP32 MACE", - startup_mace_irq, - shutdown_mace_irq, - enable_mace_irq, - disable_mace_irq, - mask_and_ack_mace_irq, - end_mace_irq, - NULL + .typename = "IP32 MACE", + .startup = startup_mace_irq, + .shutdown = shutdown_mace_irq, + .enable = enable_mace_irq, + .disable = disable_mace_irq, + .ack = mask_and_ack_mace_irq, + .end = end_mace_irq, }; static void ip32_unknown_interrupt(struct pt_regs *regs) diff -Naur linux-2.6.12.6.orig/arch/mips/sgi-ip32/ip32-memory.c linux-2.6.12.6/arch/mips/sgi-ip32/ip32-memory.c --- linux-2.6.12.6.orig/arch/mips/sgi-ip32/ip32-memory.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sgi-ip32/ip32-memory.c 2005-10-02 23:47:37.000000000 +0000 @@ -36,8 +36,8 @@ if (base + size > (256 << 20)) base += CRIME_HI_MEM_BASE; - printk("CRIME MC: bank %u base 0x%016lx size %luMB\n", - bank, base, size); + printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n", + bank, base, size >> 20); add_memory_region (base, size, BOOT_MEM_RAM); } } diff -Naur linux-2.6.12.6.orig/arch/mips/sgi-ip32/ip32-setup.c linux-2.6.12.6/arch/mips/sgi-ip32/ip32-setup.c --- linux-2.6.12.6.orig/arch/mips/sgi-ip32/ip32-setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sgi-ip32/ip32-setup.c 2005-10-02 23:47:37.000000000 +0000 @@ -92,7 +92,7 @@ setup_irq(IP32_R4K_TIMER_IRQ, irq); } -static int __init ip32_setup(void) +void __init plat_setup(void) { board_be_init = ip32_be_init; @@ -152,8 +152,4 @@ } } #endif - - return 0; } - -early_initcall(ip32_setup); diff -Naur linux-2.6.12.6.orig/arch/mips/sibyte/Kconfig linux-2.6.12.6/arch/mips/sibyte/Kconfig --- linux-2.6.12.6.orig/arch/mips/sibyte/Kconfig 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sibyte/Kconfig 2005-10-02 23:47:37.000000000 +0000 @@ -0,0 +1,143 @@ +config SIBYTE_SB1250 + bool + select HW_HAS_PCI + select SIBYTE_HAS_LDT + select SIBYTE_SB1xxx_SOC + +config SIBYTE_BCM1120 + bool + select SIBYTE_BCM112X + select SIBYTE_SB1xxx_SOC + +config SIBYTE_BCM1125 + bool + select HW_HAS_PCI + select SIBYTE_BCM112X + select SIBYTE_SB1xxx_SOC + +config SIBYTE_BCM1125H + bool + select HW_HAS_PCI + select SIBYTE_BCM112X + select SIBYTE_HAS_LDT + select SIBYTE_SB1xxx_SOC + +config SIBYTE_BCM112X + bool + select SIBYTE_SB1xxx_SOC + +config SIBYTE_SB1xxx_SOC + bool + depends on EXPERIMENTAL + select DMA_COHERENT + select SIBYTE_CFE + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + +choice + prompt "SiByte SOC Stepping" + depends on SIBYTE_SB1xxx_SOC + +config CPU_SB1_PASS_1 + bool "1250 Pass1" + depends on SIBYTE_SB1250 + select CPU_HAS_PREFETCH + +config CPU_SB1_PASS_2_1250 + bool "1250 An" + depends on SIBYTE_SB1250 + select CPU_SB1_PASS_2 + help + Also called BCM1250 Pass 2 + +config CPU_SB1_PASS_2_2 + bool "1250 Bn" + depends on SIBYTE_SB1250 + select CPU_HAS_PREFETCH + help + Also called BCM1250 Pass 2.2 + +config CPU_SB1_PASS_4 + bool "1250 Cn" + depends on SIBYTE_SB1250 + select CPU_HAS_PREFETCH + help + Also called BCM1250 Pass 3 + +config CPU_SB1_PASS_2_112x + bool "112x Hybrid" + depends on SIBYTE_BCM112X + select CPU_SB1_PASS_2 + +config CPU_SB1_PASS_3 + bool "112x An" + depends on SIBYTE_BCM112X + select CPU_HAS_PREFETCH + +endchoice + +config CPU_SB1_PASS_2 + bool + +config SIBYTE_HAS_LDT + bool + depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H) + default y + +config SIMULATION + bool "Running under simulation" + depends on SIBYTE_SB1xxx_SOC + help + Build a kernel suitable for running under the GDB simulator. + Primarily adjusts the kernel's notion of time. + +config SIBYTE_CFE + bool "Booting from CFE" + depends on SIBYTE_SB1xxx_SOC + help + Make use of the CFE API for enumerating available memory, + controlling secondary CPUs, and possibly console output. + +config SIBYTE_CFE_CONSOLE + bool "Use firmware console" + depends on SIBYTE_CFE + help + Use the CFE API's console write routines during boot. Other console + options (VT console, sb1250 duart console, etc.) should not be + configured. + +config SIBYTE_STANDALONE + bool + depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE + default y + +config SIBYTE_STANDALONE_RAM_SIZE + int "Memory size (in megabytes)" + depends on SIBYTE_STANDALONE + default "32" + +config SIBYTE_BUS_WATCHER + bool "Support for Bus Watcher statistics" + depends on SIBYTE_SB1xxx_SOC + help + Handle and keep statistics on the bus error interrupts (COR_ECC, + BAD_ECC, IO_BUS). + +config SIBYTE_BW_TRACE + bool "Capture bus trace before bus error" + depends on SIBYTE_BUS_WATCHER + help + Run a continuous bus trace, dumping the raw data as soon as + a ZBbus error is detected. Cannot work if ZBbus profiling + is turned on, and also will interfere with JTAG-based trace + buffer activity. Raw buffer data is dumped to console, and + must be processed off-line. + +config SIBYTE_SB1250_PROF + bool "Support for SB1/SOC profiling - SB1/SCD perf counters" + depends on SIBYTE_SB1xxx_SOC + +config SIBYTE_TBPROF + bool "Support for ZBbus profiling" + depends on SIBYTE_SB1xxx_SOC diff -Naur linux-2.6.12.6.orig/arch/mips/sibyte/sb1250/bcm1250_tbprof.c linux-2.6.12.6/arch/mips/sibyte/sb1250/bcm1250_tbprof.c --- linux-2.6.12.6.orig/arch/mips/sibyte/sb1250/bcm1250_tbprof.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sibyte/sb1250/bcm1250_tbprof.c 2005-10-02 23:47:37.000000000 +0000 @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -64,24 +65,25 @@ u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL; /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to trigger start of trace. XXX vary sampling period */ - bus_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); - scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG)); + __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); + scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); /* Unfortunately, in Pass 2 we must clear all counters to knock down a previous interrupt request. This means that bus profiling requires ALL of the SCD perf counters. */ - bus_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | // keep counters 0,2,3 as is - M_SPC_CFG_ENABLE | // enable counting - M_SPC_CFG_CLEAR | // clear all counters - V_SPC_CFG_SRC1(1), // counter 1 counts cycles - IOADDR(A_SCD_PERF_CNT_CFG)); - bus_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); + __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | + // keep counters 0,2,3 as is + M_SPC_CFG_ENABLE | // enable counting + M_SPC_CFG_CLEAR | // clear all counters + V_SPC_CFG_SRC1(1), // counter 1 counts cycles + IOADDR(A_SCD_PERF_CNT_CFG)); + __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); /* Reset the trace buffer */ - bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); + __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT) /* XXXKW may want to expose control to the data-collector */ tb_options |= M_SCD_TRACE_CFG_FORCECNT; #endif - bus_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); + __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); sbp.tb_armed = 1; } @@ -93,23 +95,30 @@ /* XXX should use XKPHYS to make writes bypass L2 */ u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++]; /* Read out trace */ - bus_writeq(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG)); + __raw_writeq(M_SCD_TRACE_CFG_START_READ, + IOADDR(A_SCD_TRACE_CFG)); __asm__ __volatile__ ("sync" : : : "memory"); /* Loop runs backwards because bundles are read out in reverse order */ for (i = 256 * 6; i > 0; i -= 6) { // Subscripts decrease to put bundle in the order // t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi - p[i-1] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 hi - p[i-2] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 lo - p[i-3] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 hi - p[i-4] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 lo - p[i-5] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 hi - p[i-6] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 lo + p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); + // read t2 hi + p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); + // read t2 lo + p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); + // read t1 hi + p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); + // read t1 lo + p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); + // read t0 hi + p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); + // read t0 lo } if (!sbp.tb_enable) { DBG(printk(DEVNAME ": tb_intr shutdown\n")); - bus_writeq(M_SCD_TRACE_CFG_RESET, - IOADDR(A_SCD_TRACE_CFG)); + __raw_writeq(M_SCD_TRACE_CFG_RESET, + IOADDR(A_SCD_TRACE_CFG)); sbp.tb_armed = 0; wake_up(&sbp.tb_sync); } else { @@ -118,7 +127,7 @@ } else { /* No more trace buffer samples */ DBG(printk(DEVNAME ": tb_intr full\n")); - bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); + __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); sbp.tb_armed = 0; if (!sbp.tb_enable) { wake_up(&sbp.tb_sync); @@ -152,13 +161,11 @@ return -EBUSY; } /* Make sure there isn't a perf-cnt interrupt waiting */ - scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG)); + scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); /* Disable and clear counters, override SRC_1 */ - bus_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) | - M_SPC_CFG_ENABLE | - M_SPC_CFG_CLEAR | - V_SPC_CFG_SRC1(1), - IOADDR(A_SCD_PERF_CNT_CFG)); + __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) | + M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1), + IOADDR(A_SCD_PERF_CNT_CFG)); /* We grab this interrupt to prevent others from trying to use it, even though we don't want to service the interrupts @@ -172,55 +179,55 @@ /* I need the core to mask these, but the interrupt mapper to pass them through. I am exploiting my knowledge that cp0_status masks out IP[5]. krw */ - bus_writeq(K_INT_MAP_I3, - IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + - (K_INT_PERF_CNT << 3))); + __raw_writeq(K_INT_MAP_I3, + IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + + (K_INT_PERF_CNT << 3))); /* Initialize address traps */ - bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); - - bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3)); - - bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2)); - bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); + + __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3)); + + __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2)); + __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); /* Initialize Trace Event 0-7 */ // when interrupt - bus_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6)); - bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); + __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); /* Initialize Trace Sequence 0-7 */ // Start on event 0 (interrupt) - bus_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff, - IOADDR(A_SCD_TRACE_SEQUENCE_0)); + __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff, + IOADDR(A_SCD_TRACE_SEQUENCE_0)); // dsamp when d used | asamp when a used - bus_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | - K_SCD_TRSEQ_TRIGGER_ALL, - IOADDR(A_SCD_TRACE_SEQUENCE_1)); - bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2)); - bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3)); - bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4)); - bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); - bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6)); - bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); + __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | + K_SCD_TRSEQ_TRIGGER_ALL, + IOADDR(A_SCD_TRACE_SEQUENCE_1)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6)); + __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */ - bus_writeq((1ULL << K_INT_PERF_CNT), - IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); + __raw_writeq(1ULL << K_INT_PERF_CNT, + IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); arm_tb(); @@ -231,6 +238,7 @@ int sbprof_zbprof_stop(void) { + DEFINE_WAIT(wait); DBG(printk(DEVNAME ": stopping\n")); if (sbp.tb_enable) { @@ -240,7 +248,9 @@ this sleep happens. */ if (sbp.tb_armed) { DBG(printk(DEVNAME ": wait for disarm\n")); - interruptible_sleep_on(&sbp.tb_sync); + prepare_to_wait(&sbp.tb_sync, &wait, TASK_INTERRUPTIBLE); + schedule(); + finish_wait(&sbp.tb_sync, &wait); DBG(printk(DEVNAME ": disarm complete\n")); } free_irq(K_INT_TRACE_FREEZE, &sbp); @@ -348,7 +358,10 @@ error = sbprof_zbprof_stop(); break; case SBPROF_ZBWAITFULL: - interruptible_sleep_on(&sbp.tb_read); + DEFINE_WAIT(wait); + prepare_to_wait(&sbp.tb_read, &wait, TASK_INTERRUPTIBLE); + schedule(); + finish_wait(&sbp.tb_read, &wait); /* XXXKW check if interrupted? */ return put_user(TB_FULL, (int *) arg); default: diff -Naur linux-2.6.12.6.orig/arch/mips/sibyte/sb1250/bus_watcher.c linux-2.6.12.6/arch/mips/sibyte/sb1250/bus_watcher.c --- linux-2.6.12.6.orig/arch/mips/sibyte/sb1250/bus_watcher.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sibyte/sb1250/bus_watcher.c 2005-10-02 23:47:37.000000000 +0000 @@ -189,7 +189,7 @@ for (i=0; i<256*6; i++) printk("%016llx\n", - (unsigned long long)bus_readq(IOADDR(A_SCD_TRACE_READ))); + (long long)__raw_readq(IOADDR(A_SCD_TRACE_READ))); csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); diff -Naur linux-2.6.12.6.orig/arch/mips/sibyte/sb1250/irq.c linux-2.6.12.6/arch/mips/sibyte/sb1250/irq.c --- linux-2.6.12.6.orig/arch/mips/sibyte/sb1250/irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sibyte/sb1250/irq.c 2005-10-02 23:47:38.000000000 +0000 @@ -71,17 +71,15 @@ #endif static struct hw_interrupt_type sb1250_irq_type = { - "SB1250-IMR", - startup_sb1250_irq, - shutdown_sb1250_irq, - enable_sb1250_irq, - disable_sb1250_irq, - ack_sb1250_irq, - end_sb1250_irq, + .typename = "SB1250-IMR", + .startup = startup_sb1250_irq, + .shutdown = shutdown_sb1250_irq, + .enable = enable_sb1250_irq, + .disable = disable_sb1250_irq, + .ack = ack_sb1250_irq, + .end = end_sb1250_irq, #ifdef CONFIG_SMP - sb1250_set_affinity -#else - NULL + .set_affinity = sb1250_set_affinity #endif }; @@ -96,11 +94,11 @@ u64 cur_ints; spin_lock_irqsave(&sb1250_imr_lock, flags); - cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + - R_IMR_INTERRUPT_MASK)); + cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); cur_ints |= (((u64) 1) << irq); - __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + - R_IMR_INTERRUPT_MASK)); + ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); spin_unlock_irqrestore(&sb1250_imr_lock, flags); } @@ -110,11 +108,11 @@ u64 cur_ints; spin_lock_irqsave(&sb1250_imr_lock, flags); - cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + - R_IMR_INTERRUPT_MASK)); + cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); cur_ints &= ~(((u64) 1) << irq); - __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + - R_IMR_INTERRUPT_MASK)); + ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); spin_unlock_irqrestore(&sb1250_imr_lock, flags); } @@ -149,23 +147,23 @@ /* Swizzle each CPU's IMR (but leave the IP selection alone) */ old_cpu = sb1250_irq_owner[irq]; - cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(old_cpu) + - R_IMR_INTERRUPT_MASK)); + cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + + R_IMR_INTERRUPT_MASK)); int_on = !(cur_ints & (((u64) 1) << irq)); if (int_on) { /* If it was on, mask it */ cur_ints |= (((u64) 1) << irq); - __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + - R_IMR_INTERRUPT_MASK)); + ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + + R_IMR_INTERRUPT_MASK)); } sb1250_irq_owner[irq] = cpu; if (int_on) { /* unmask for the new CPU */ - cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + - R_IMR_INTERRUPT_MASK)); + cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); cur_ints &= ~(((u64) 1) << irq); - __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + - R_IMR_INTERRUPT_MASK)); + ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); } spin_unlock(&sb1250_imr_lock); spin_unlock_irqrestore(&desc->lock, flags); @@ -208,8 +206,8 @@ * deliver the interrupts to all CPUs (which makes affinity * changing easier for us) */ - pending = bus_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], - R_IMR_LDT_INTERRUPT))); + pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], + R_IMR_LDT_INTERRUPT))); pending &= ((u64)1 << (irq)); if (pending) { int i; @@ -224,8 +222,8 @@ * Clear for all CPUs so an affinity switch * doesn't find an old status */ - bus_writeq(pending, - IOADDR(A_IMR_REGISTER(cpu, + __raw_writeq(pending, + IOADDR(A_IMR_REGISTER(cpu, R_IMR_LDT_INTERRUPT_CLR))); } @@ -340,12 +338,14 @@ /* Default everything to IP2 */ for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ - bus_writeq(IMR_IP2_VAL, - IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + - (i << 3))); - bus_writeq(IMR_IP2_VAL, - IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + - (i << 3))); + __raw_writeq(IMR_IP2_VAL, + IOADDR(A_IMR_REGISTER(0, + R_IMR_INTERRUPT_MAP_BASE) + + (i << 3))); + __raw_writeq(IMR_IP2_VAL, + IOADDR(A_IMR_REGISTER(1, + R_IMR_INTERRUPT_MAP_BASE) + + (i << 3))); } init_sb1250_irqs(); @@ -355,23 +355,23 @@ * inter-cpu messages */ /* Was I1 */ - bus_writeq(IMR_IP3_VAL, - IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + - (K_INT_MBOX_0 << 3))); - bus_writeq(IMR_IP3_VAL, - IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + - (K_INT_MBOX_0 << 3))); + __raw_writeq(IMR_IP3_VAL, + IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + + (K_INT_MBOX_0 << 3))); + __raw_writeq(IMR_IP3_VAL, + IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + + (K_INT_MBOX_0 << 3))); /* Clear the mailboxes. The firmware may leave them dirty */ - bus_writeq(0xffffffffffffffffULL, - IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); - bus_writeq(0xffffffffffffffffULL, - IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); + __raw_writeq(0xffffffffffffffffULL, + IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); + __raw_writeq(0xffffffffffffffffULL, + IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); /* Mask everything except the mailbox registers for both cpus */ tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); - bus_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); - bus_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); + __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); + __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); sb1250_steal_irq(K_INT_MBOX_0); @@ -396,12 +396,14 @@ sb1250_duart_present[kgdb_port] = 0; #endif /* Setup uart 1 settings, mapper */ - bus_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port))); + __raw_writeq(M_DUART_IMR_BRK, + IOADDR(A_DUART_IMRREG(kgdb_port))); sb1250_steal_irq(kgdb_irq); - bus_writeq(IMR_IP6_VAL, - IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + - (kgdb_irq<<3))); + __raw_writeq(IMR_IP6_VAL, + IOADDR(A_IMR_REGISTER(0, + R_IMR_INTERRUPT_MAP_BASE) + + (kgdb_irq << 3))); sb1250_unmask_irq(0, kgdb_irq); } #endif diff -Naur linux-2.6.12.6.orig/arch/mips/sibyte/sb1250/setup.c linux-2.6.12.6/arch/mips/sibyte/sb1250/setup.c --- linux-2.6.12.6.orig/arch/mips/sibyte/sb1250/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sibyte/sb1250/setup.c 2005-10-02 23:47:38.000000000 +0000 @@ -153,7 +153,7 @@ int bad_config = 0; sb1_pass = read_c0_prid() & 0xff; - sys_rev = bus_readq(IOADDR(A_SCD_SYSTEM_REVISION)); + sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); soc_type = SYS_SOC_TYPE(sys_rev); soc_pass = G_SYS_REVISION(sys_rev); @@ -162,7 +162,7 @@ machine_restart(NULL); } - plldiv = G_SYS_PLL_DIV(bus_readq(IOADDR(A_SCD_SYSTEM_CFG))); + plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25); prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n", diff -Naur linux-2.6.12.6.orig/arch/mips/sibyte/sb1250/smp.c linux-2.6.12.6/arch/mips/sibyte/sb1250/smp.c --- linux-2.6.12.6.orig/arch/mips/sibyte/sb1250/smp.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sibyte/sb1250/smp.c 2005-10-02 23:47:38.000000000 +0000 @@ -29,18 +29,18 @@ #include static void *mailbox_set_regs[] = { - (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU), - (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU) + IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU), + IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU) }; static void *mailbox_clear_regs[] = { - (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU), - (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU) + IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU), + IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU) }; static void *mailbox_regs[] = { - (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU), - (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU) + IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU), + IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU) }; /* @@ -73,7 +73,7 @@ */ void core_send_ipi(int cpu, unsigned int action) { - bus_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); + __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); } void sb1250_mailbox_interrupt(struct pt_regs *regs) @@ -83,10 +83,10 @@ kstat_this_cpu.irqs[K_INT_MBOX_0]++; /* Load the mailbox register to figure out what we're supposed to do */ - action = (__bus_readq(mailbox_regs[cpu]) >> 48) & 0xffff; + action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff; /* Clear the mailbox to clear the interrupt */ - __bus_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]); + ____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]); /* * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the diff -Naur linux-2.6.12.6.orig/arch/mips/sibyte/sb1250/time.c linux-2.6.12.6/arch/mips/sibyte/sb1250/time.c --- linux-2.6.12.6.orig/arch/mips/sibyte/sb1250/time.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sibyte/sb1250/time.c 2005-10-02 23:47:38.000000000 +0000 @@ -67,24 +67,24 @@ sb1250_mask_irq(cpu, irq); /* Map the timer interrupt to ip[4] of this cpu */ - bus_writeq(IMR_IP4_VAL, - IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + - (irq << 3))); + __raw_writeq(IMR_IP4_VAL, + IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + + (irq << 3))); /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ /* Disable the timer and set up the count */ - bus_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); #ifdef CONFIG_SIMULATION - bus_writeq(50000 / HZ, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); + __raw_writeq(50000 / HZ, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #else - bus_writeq(1000000/HZ, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); + __raw_writeq(1000000 / HZ, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #endif /* Set the timer running */ - bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); sb1250_unmask_irq(cpu, irq); sb1250_steal_irq(irq); @@ -105,8 +105,8 @@ int irq = K_INT_TIMER_0 + cpu; /* Reset the timer */ - __bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); /* * CPU 0 handles the global timer interrupt job @@ -130,7 +130,7 @@ unsigned long sb1250_gettimeoffset(void) { unsigned long count = - bus_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); + __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); return 1000000/HZ - count; } diff -Naur linux-2.6.12.6.orig/arch/mips/sibyte/swarm/rtc_m41t81.c linux-2.6.12.6/arch/mips/sibyte/swarm/rtc_m41t81.c --- linux-2.6.12.6.orig/arch/mips/sibyte/swarm/rtc_m41t81.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sibyte/swarm/rtc_m41t81.c 2005-10-02 23:47:38.000000000 +0000 @@ -82,59 +82,60 @@ #define M41T81REG_SQW 0x13 /* square wave register */ #define M41T81_CCR_ADDRESS 0x68 -#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) + +#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) static int m41t81_read(uint8_t addr) { - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); - bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE), - SMB_CSR(R_SMB_START)); + __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); + __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), - SMB_CSR(R_SMB_START)); + __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } - return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); + return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); } static int m41t81_write(uint8_t addr, int b) { - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq((addr & 0xFF), SMB_CSR(R_SMB_CMD)); - bus_writeq((b & 0xff), SMB_CSR(R_SMB_DATA)); - bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, - SMB_CSR(R_SMB_START)); + __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); + __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA)); + __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } /* read the same byte again to make sure it is written */ - bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, - SMB_CSR(R_SMB_START)); + __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; return 0; diff -Naur linux-2.6.12.6.orig/arch/mips/sibyte/swarm/rtc_xicor1241.c linux-2.6.12.6/arch/mips/sibyte/swarm/rtc_xicor1241.c --- linux-2.6.12.6.orig/arch/mips/sibyte/swarm/rtc_xicor1241.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sibyte/swarm/rtc_xicor1241.c 2005-10-02 23:47:38.000000000 +0000 @@ -57,52 +57,52 @@ #define X1241_CCR_ADDRESS 0x6F -#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) +#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) static int xicor_read(uint8_t addr) { - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); - bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); - bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), - SMB_CSR(R_SMB_START)); + __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); + __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA)); + __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), - SMB_CSR(R_SMB_START)); + __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } - return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); + return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); } static int xicor_write(uint8_t addr, int b) { - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq(addr, SMB_CSR(R_SMB_CMD)); - bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); - bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, - SMB_CSR(R_SMB_START)); + __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); + __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); + __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } else { return 0; diff -Naur linux-2.6.12.6.orig/arch/mips/sibyte/swarm/setup.c linux-2.6.12.6/arch/mips/sibyte/swarm/setup.c --- linux-2.6.12.6.orig/arch/mips/sibyte/swarm/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sibyte/swarm/setup.c 2005-10-02 23:47:38.000000000 +0000 @@ -84,7 +84,7 @@ return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); } -static int __init swarm_setup(void) +int __init plat_setup(void) { sb1250_setup(); @@ -133,12 +133,8 @@ }; /* XXXKW for CFE, get lines/cols from environment */ #endif - - return 0; } -early_initcall(swarm_setup); - #ifdef LEDS_PHYS #ifdef CONFIG_SIBYTE_CARMEL diff -Naur linux-2.6.12.6.orig/arch/mips/sibyte/swarm/time.c linux-2.6.12.6/arch/mips/sibyte/swarm/time.c --- linux-2.6.12.6.orig/arch/mips/sibyte/swarm/time.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sibyte/swarm/time.c 2005-10-02 23:47:38.000000000 +0000 @@ -79,48 +79,48 @@ static int xicor_read(uint8_t addr) { - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); - bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); - bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), - SMB_CSR(R_SMB_START)); + __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); + __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA)); + __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), - SMB_CSR(R_SMB_START)); + __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } - return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); + return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); } static int xicor_write(uint8_t addr, int b) { - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - bus_writeq(addr, SMB_CSR(R_SMB_CMD)); - bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); - bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, - SMB_CSR(R_SMB_START)); + __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); + __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); + __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, + SMB_CSR(R_SMB_START)); - while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } else { return 0; @@ -228,8 +228,8 @@ /* Establish communication with the Xicor 1241 RTC */ /* XXXKW how do I share the SMBus with the I2C subsystem? */ - bus_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); - bus_writeq(0, SMB_CSR(R_SMB_CONTROL)); + __raw_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); + __raw_writeq(0, SMB_CSR(R_SMB_CONTROL)); if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) { printk("x1241: couldn't detect on SWARM SMBus 1\n"); diff -Naur linux-2.6.12.6.orig/arch/mips/sni/irq.c linux-2.6.12.6/arch/mips/sni/irq.c --- linux-2.6.12.6.orig/arch/mips/sni/irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sni/irq.c 2005-10-02 23:47:38.000000000 +0000 @@ -58,14 +58,13 @@ } static struct hw_interrupt_type pciasic_irq_type = { - "ASIC-PCI", - startup_pciasic_irq, - shutdown_pciasic_irq, - enable_pciasic_irq, - disable_pciasic_irq, - mask_and_ack_pciasic_irq, - end_pciasic_irq, - NULL + .typename = "ASIC-PCI", + .startup = startup_pciasic_irq, + .shutdown = shutdown_pciasic_irq, + .enable = enable_pciasic_irq, + .disable = disable_pciasic_irq, + .ack = mask_and_ack_pciasic_irq, + .end = end_pciasic_irq, }; /* diff -Naur linux-2.6.12.6.orig/arch/mips/sni/setup.c linux-2.6.12.6/arch/mips/sni/setup.c --- linux-2.6.12.6.orig/arch/mips/sni/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/sni/setup.c 2005-10-02 23:47:38.000000000 +0000 @@ -167,7 +167,7 @@ rtc_set_time = mc146818_set_rtc_mmss; } -static int __init sni_rm200_pci_setup(void) +void __init plat_setup(void) { sni_pcimt_detect(); sni_pcimt_sc_init(); @@ -196,8 +196,4 @@ #ifdef CONFIG_PCI register_pci_controller(&sni_controller); #endif - - return 0; } - -early_initcall(sni_rm200_pci_setup); diff -Naur linux-2.6.12.6.orig/arch/mips/tx4927/Kconfig linux-2.6.12.6/arch/mips/tx4927/Kconfig --- linux-2.6.12.6.orig/arch/mips/tx4927/Kconfig 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/tx4927/Kconfig 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,3 @@ +config TOSHIBA_FPCIB0 + bool "FPCIB0 Backplane Support" + depends on TOSHIBA_RBTX4927 diff -Naur linux-2.6.12.6.orig/arch/mips/tx4927/common/tx4927_setup.c linux-2.6.12.6/arch/mips/tx4927/common/tx4927_setup.c --- linux-2.6.12.6.orig/arch/mips/tx4927/common/tx4927_setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/tx4927/common/tx4927_setup.c 2005-10-02 23:47:38.000000000 +0000 @@ -64,7 +64,7 @@ } -static void __init tx4927_setup(void) +void __init plat_setup(void) { board_time_init = tx4927_time_init; board_timer_setup = tx4927_timer_setup; @@ -76,12 +76,8 @@ toshiba_rbtx4927_setup(); } #endif - - return; } -early_initcall(tx4927_setup); - void __init tx4927_time_init(void) { diff -Naur linux-2.6.12.6.orig/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c linux-2.6.12.6/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c --- linux-2.6.12.6.orig/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c 2005-10-02 23:47:38.000000000 +0000 @@ -77,6 +77,11 @@ #include #include #endif +#ifdef CONFIG_SERIAL_TXX9 +#include +#include +#include +#endif #undef TOSHIBA_RBTX4927_SETUP_DEBUG @@ -920,12 +925,30 @@ #endif /* CONFIG_PCI */ +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + int i; + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (char *)(0xff1ff300 + i * 0x100); + req.mapbase = 0xff1ff300 + i * 0x100; + req.irq = 32 + i; + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = 50000000; + early_serial_txx9_setup(&req); + } + } #ifdef CONFIG_SERIAL_TXX9_CONSOLE argptr = prom_getcmdline(); if (strstr(argptr, "console=") == NULL) { strcat(argptr, " console=ttyS0,38400"); } #endif +#endif #ifdef CONFIG_ROOT_NFS argptr = prom_getcmdline(); diff -Naur linux-2.6.12.6.orig/arch/mips/vr4181/common/Makefile linux-2.6.12.6/arch/mips/vr4181/common/Makefile --- linux-2.6.12.6.orig/arch/mips/vr4181/common/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr4181/common/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,7 +0,0 @@ -# -# Makefile for common code of NEC vr4181 based boards -# - -obj-y := irq.o int_handler.o serial.o time.o - -EXTRA_AFLAGS := $(CFLAGS) diff -Naur linux-2.6.12.6.orig/arch/mips/vr4181/common/int_handler.S linux-2.6.12.6/arch/mips/vr4181/common/int_handler.S --- linux-2.6.12.6.orig/arch/mips/vr4181/common/int_handler.S 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr4181/common/int_handler.S 1970-01-01 00:00:00.000000000 +0000 @@ -1,206 +0,0 @@ -/* - * arch/mips/vr4181/common/int_handler.S - * - * Adapted to the VR4181 and almost entirely rewritten: - * Copyright (C) 1999 Bradley D. LaRonde and Michael Klar - * - * Clean up to conform to the new IRQ - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ - -#include -#include -#include -#include - -#include - -/* - * [jsun] - * See include/asm/vr4181/irq.h for IRQ assignment and strategy. - */ - - .text - .set noreorder - - .align 5 - NESTED(vr4181_handle_irq, PT_SIZE, ra) - - .set noat - SAVE_ALL - CLI - - .set at - .set noreorder - - mfc0 t0, CP0_CAUSE - mfc0 t2, CP0_STATUS - - and t0, t2 - - /* we check IP3 first; it happens most frequently */ - andi t1, t0, STATUSF_IP3 - bnez t1, ll_cpu_ip3 - andi t1, t0, STATUSF_IP2 - bnez t1, ll_cpu_ip2 - andi t1, t0, STATUSF_IP7 /* cpu timer */ - bnez t1, ll_cputimer_irq - andi t1, t0, STATUSF_IP4 - bnez t1, ll_cpu_ip4 - andi t1, t0, STATUSF_IP5 - bnez t1, ll_cpu_ip5 - andi t1, t0, STATUSF_IP6 - bnez t1, ll_cpu_ip6 - andi t1, t0, STATUSF_IP0 /* software int 0 */ - bnez t1, ll_cpu_ip0 - andi t1, t0, STATUSF_IP1 /* software int 1 */ - bnez t1, ll_cpu_ip1 - nop - - .set reorder -do_spurious: - j spurious_interrupt - -/* - * regular CPU irqs - */ -ll_cputimer_irq: - li a0, VR4181_IRQ_TIMER - move a1, sp - jal do_IRQ - j ret_from_irq - - -ll_cpu_ip0: - li a0, VR4181_IRQ_SW1 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip1: - li a0, VR4181_IRQ_SW2 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip3: - li a0, VR4181_IRQ_INT1 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip4: - li a0, VR4181_IRQ_INT2 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip5: - li a0, VR4181_IRQ_INT3 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip6: - li a0, VR4181_IRQ_INT4 - move a1, sp - jal do_IRQ - j ret_from_irq - -/* - * One of the sys irq has happend. - * - * In the interest of speed, we first determine in the following order - * which 16-irq block have pending interrupts: - * sysint1 (16 sources, including cascading intrs from GPIO) - * sysint2 - * gpio (16 intr sources) - * - * Then we do binary search to find the exact interrupt source. - */ -ll_cpu_ip2: - - lui t3,%hi(VR4181_SYSINT1REG) - lhu t0,%lo(VR4181_SYSINT1REG)(t3) - lhu t2,%lo(VR4181_MSYSINT1REG)(t3) - and t0, 0xfffb /* hack - remove RTC Long 1 intr */ - and t0, t2 - beqz t0, check_sysint2 - - /* check for GPIO interrupts */ - andi t1, t0, 0x0100 - bnez t1, check_gpio_int - - /* so we have an interrupt in sysint1 which is not gpio int */ - li a0, VR4181_SYS_IRQ_BASE - 1 - j check_16 - -check_sysint2: - - lhu t0,%lo(VR4181_SYSINT2REG)(t3) - lhu t2,%lo(VR4181_MSYSINT2REG)(t3) - and t0, 0xfffe /* hack - remove RTC Long 2 intr */ - and t0, t2 - li a0, VR4181_SYS_IRQ_BASE + 16 - 1 - j check_16 - -check_gpio_int: - lui t3,%hi(VR4181_GPINTMSK) - lhu t0,%lo(VR4181_GPINTMSK)(t3) - lhu t2,%lo(VR4181_GPINTSTAT)(t3) - xori t0, 0xffff /* why? reverse logic? */ - and t0, t2 - li a0, VR4181_GPIO_IRQ_BASE - 1 - j check_16 - -/* - * When we reach check_16, we have 16-bit status in t0 and base irq number - * in a0. - */ -check_16: - andi t1, t0, 0xff - bnez t1, check_8 - - srl t0, 8 - addi a0, 8 - j check_8 - -/* - * When we reach check_8, we have 8-bit status in t0 and base irq number - * in a0. - */ -check_8: - andi t1, t0, 0xf - bnez t1, check_4 - - srl t0, 4 - addi a0, 4 - j check_4 - -/* - * When we reach check_4, we have 4-bit status in t0 and base irq number - * in a0. - */ -check_4: - andi t0, t0, 0xf - beqz t0, do_spurious - -loop: - andi t2, t0, 0x1 - srl t0, 1 - addi a0, 1 - beqz t2, loop - -found_it: - move a1, sp - jal do_IRQ - - j ret_from_irq - - END(vr4181_handle_irq) diff -Naur linux-2.6.12.6.orig/arch/mips/vr4181/common/irq.c linux-2.6.12.6/arch/mips/vr4181/common/irq.c --- linux-2.6.12.6.orig/arch/mips/vr4181/common/irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr4181/common/irq.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,239 +0,0 @@ -/* - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * linux/arch/mips/vr4181/common/irq.c - * Completely re-written to use the new irq.c - * - * Credits to Bradley D. LaRonde and Michael Klar for writing the original - * irq.c file which was derived from the common irq.c file. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -/* - * Strategy: - * - * We essentially have three irq controllers, CPU, system, and gpio. - * - * CPU irq controller is taken care by arch/mips/kernel/irq_cpu.c and - * CONFIG_IRQ_CPU config option. - * - * We here provide sys_irq and gpio_irq controller code. - */ - -static int sys_irq_base; -static int gpio_irq_base; - -/* ---------------------- sys irq ------------------------ */ -static void -sys_irq_enable(unsigned int irq) -{ - irq -= sys_irq_base; - if (irq < 16) { - *VR4181_MSYSINT1REG |= (u16)(1 << irq); - } else { - irq -= 16; - *VR4181_MSYSINT2REG |= (u16)(1 << irq); - } -} - -static void -sys_irq_disable(unsigned int irq) -{ - irq -= sys_irq_base; - if (irq < 16) { - *VR4181_MSYSINT1REG &= ~((u16)(1 << irq)); - } else { - irq -= 16; - *VR4181_MSYSINT2REG &= ~((u16)(1 << irq)); - } - -} - -static unsigned int -sys_irq_startup(unsigned int irq) -{ - sys_irq_enable(irq); - return 0; -} - -#define sys_irq_shutdown sys_irq_disable -#define sys_irq_ack sys_irq_disable - -static void -sys_irq_end(unsigned int irq) -{ - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - sys_irq_enable(irq); -} - -static hw_irq_controller sys_irq_controller = { - "vr4181_sys_irq", - sys_irq_startup, - sys_irq_shutdown, - sys_irq_enable, - sys_irq_disable, - sys_irq_ack, - sys_irq_end, - NULL /* no affinity stuff for UP */ -}; - -/* ---------------------- gpio irq ------------------------ */ -/* gpio irq lines use reverse logic */ -static void -gpio_irq_enable(unsigned int irq) -{ - irq -= gpio_irq_base; - *VR4181_GPINTMSK &= ~((u16)(1 << irq)); -} - -static void -gpio_irq_disable(unsigned int irq) -{ - irq -= gpio_irq_base; - *VR4181_GPINTMSK |= (u16)(1 << irq); -} - -static unsigned int -gpio_irq_startup(unsigned int irq) -{ - gpio_irq_enable(irq); - - irq -= gpio_irq_base; - *VR4181_GPINTEN |= (u16)(1 << irq ); - - return 0; -} - -static void -gpio_irq_shutdown(unsigned int irq) -{ - gpio_irq_disable(irq); - - irq -= gpio_irq_base; - *VR4181_GPINTEN &= ~((u16)(1 << irq )); -} - -static void -gpio_irq_ack(unsigned int irq) -{ - u16 irqtype; - u16 irqshift; - - gpio_irq_disable(irq); - - /* we clear interrupt if it is edge triggered */ - irq -= gpio_irq_base; - if (irq < 8) { - irqtype = *VR4181_GPINTTYPL; - irqshift = 2 << (irq*2); - } else { - irqtype = *VR4181_GPINTTYPH; - irqshift = 2 << ((irq-8)*2); - } - if ( ! (irqtype & irqshift) ) { - *VR4181_GPINTSTAT = (u16) (1 << irq); - } -} - -static void -gpio_irq_end(unsigned int irq) -{ - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - gpio_irq_enable(irq); -} - -static hw_irq_controller gpio_irq_controller = { - "vr4181_gpio_irq", - gpio_irq_startup, - gpio_irq_shutdown, - gpio_irq_enable, - gpio_irq_disable, - gpio_irq_ack, - gpio_irq_end, - NULL /* no affinity stuff for UP */ -}; - -/* --------------------- IRQ init stuff ---------------------- */ - -extern asmlinkage void vr4181_handle_irq(void); -extern void breakpoint(void); -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); -extern void mips_cpu_irq_init(u32 irq_base); - -static struct irqaction cascade = - { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL }; -static struct irqaction reserved = - { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL }; - -void __init arch_init_irq(void) -{ - int i; - - set_except_vector(0, vr4181_handle_irq); - - /* init CPU irqs */ - mips_cpu_irq_init(VR4181_CPU_IRQ_BASE); - - /* init sys irqs */ - sys_irq_base = VR4181_SYS_IRQ_BASE; - for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].handler = &sys_irq_controller; - } - - /* init gpio irqs */ - gpio_irq_base = VR4181_GPIO_IRQ_BASE; - for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].handler = &gpio_irq_controller; - } - - /* Default all ICU IRQs to off ... */ - *VR4181_MSYSINT1REG = 0; - *VR4181_MSYSINT2REG = 0; - - /* We initialize the level 2 ICU registers to all bits disabled. */ - *VR4181_MPIUINTREG = 0; - *VR4181_MAIUINTREG = 0; - *VR4181_MKIUINTREG = 0; - - /* disable all GPIO intrs */ - *VR4181_GPINTMSK = 0xffff; - - /* vector handler. What these do is register the IRQ as non-sharable */ - setup_irq(VR4181_IRQ_INT0, &cascade); - setup_irq(VR4181_IRQ_GIU, &cascade); - - /* - * RTC interrupts are interesting. They have two destinations. - * One is at sys irq controller, and the other is at CPU IP3 and IP4. - * RTC timer is used as system timer. - * We enable them here, but timer routine will register later - * with CPU IP3/IP4. - */ - setup_irq(VR4181_IRQ_RTCL1, &reserved); - setup_irq(VR4181_IRQ_RTCL2, &reserved); -} diff -Naur linux-2.6.12.6.orig/arch/mips/vr4181/common/serial.c linux-2.6.12.6/arch/mips/vr4181/common/serial.c --- linux-2.6.12.6.orig/arch/mips/vr4181/common/serial.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr4181/common/serial.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,51 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/vr4181/common/serial.c - * initialize serial port on vr4181. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* - * [jsun, 010925] - * You need to make sure rs_table has at least one element in - * drivers/char/serial.c file. There is no good way to do it right - * now. A workaround is to include CONFIG_SERIAL_MANY_PORTS in your - * configure file, which would gives you 64 ports and wastes 11K ram. - */ - -#include -#include -#include -#include - -#include - -void __init vr4181_init_serial(void) -{ - struct serial_struct s; - - /* turn on UART clock */ - *VR4181_CMUCLKMSK |= VR4181_CMUCLKMSK_MSKSIU; - - /* clear memory */ - memset(&s, 0, sizeof(s)); - - s.line = 0; /* we set the first one */ - s.baud_base = 1152000; - s.irq = VR4181_IRQ_SIU; - s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */ - s.iomem_base = (u8*)VR4181_SIURB; - s.iomem_reg_shift = 0; - s.io_type = SERIAL_IO_MEM; - if (early_serial_setup(&s) != 0) { - panic("vr4181_init_serial() failed!"); - } -} - diff -Naur linux-2.6.12.6.orig/arch/mips/vr4181/common/time.c linux-2.6.12.6/arch/mips/vr4181/common/time.c --- linux-2.6.12.6.orig/arch/mips/vr4181/common/time.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr4181/common/time.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,145 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * rtc and time ops for vr4181. Part of code is drived from - * linux-vr, originally written by Bradley D. LaRonde & Michael Klar. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include -#include /* for HZ */ -#include -#include - -#include -#include - -#include - -#define COUNTS_PER_JIFFY ((32768 + HZ/2) / HZ) - -/* - * RTC ops - */ - -DEFINE_SPINLOCK(rtc_lock); - -/* per VR41xx docs, bad data can be read if between 2 counts */ -static inline unsigned short -read_time_reg(volatile unsigned short *reg) -{ - unsigned short value; - do { - value = *reg; - barrier(); - } while (value != *reg); - return value; -} - -static unsigned long -vr4181_rtc_get_time(void) -{ - unsigned short regh, regm, regl; - - // why this crazy order, you ask? to guarantee that neither m - // nor l wrap before all 3 read - do { - regm = read_time_reg(VR4181_ETIMEMREG); - barrier(); - regh = read_time_reg(VR4181_ETIMEHREG); - barrier(); - regl = read_time_reg(VR4181_ETIMELREG); - } while (regm != read_time_reg(VR4181_ETIMEMREG)); - return ((regh << 17) | (regm << 1) | (regl >> 15)); -} - -static int -vr4181_rtc_set_time(unsigned long timeval) -{ - unsigned short intreg; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - intreg = *VR4181_RTCINTREG & 0x05; - barrier(); - *VR4181_ETIMELREG = timeval << 15; - *VR4181_ETIMEMREG = timeval >> 1; - *VR4181_ETIMEHREG = timeval >> 17; - barrier(); - // assume that any ints that just triggered are invalid, since the - // time value is written non-atomically in 3 separate regs - *VR4181_RTCINTREG = 0x05 ^ intreg; - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - - -/* - * timer interrupt routine (wrapper) - * - * we need our own interrupt routine because we need to clear - * RTC1 interrupt. - */ -static void -vr4181_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - /* Clear the interrupt. */ - *VR4181_RTCINTREG = 0x2; - - /* call the generic one */ - timer_interrupt(irq, dev_id, regs); -} - - -/* - * vr4181_time_init: - * - * We pick the following choices: - * . we use elapsed timer as the RTC. We set some reasonable init data since - * it does not persist across reset - * . we use RTC1 as the system timer interrupt source. - * . we use CPU counter for fast_gettimeoffset and we calivrate the cpu - * frequency. In other words, we use calibrate_div64_gettimeoffset(). - * . we use our own timer interrupt routine which clears the interrupt - * and then calls the generic high-level timer interrupt routine. - * - */ - -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); - -static void -vr4181_timer_setup(struct irqaction *irq) -{ - /* over-write the handler to be our own one */ - irq->handler = vr4181_timer_interrupt; - - /* sets up the frequency */ - *VR4181_RTCL1LREG = COUNTS_PER_JIFFY; - *VR4181_RTCL1HREG = 0; - - /* and ack any pending ints */ - *VR4181_RTCINTREG = 0x2; - - /* setup irqaction */ - setup_irq(VR4181_IRQ_INT1, irq); - -} - -void -vr4181_init_time(void) -{ - /* setup hookup functions */ - rtc_get_time = vr4181_rtc_get_time; - rtc_set_time = vr4181_rtc_set_time; - - board_timer_setup = vr4181_timer_setup; -} - diff -Naur linux-2.6.12.6.orig/arch/mips/vr4181/osprey/Makefile linux-2.6.12.6/arch/mips/vr4181/osprey/Makefile --- linux-2.6.12.6.orig/arch/mips/vr4181/osprey/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr4181/osprey/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,7 +0,0 @@ -# -# Makefile for common code of NEC Osprey board -# - -obj-y := setup.o prom.o reset.o - -obj-$(CONFIG_KGDB) += dbg_io.o diff -Naur linux-2.6.12.6.orig/arch/mips/vr4181/osprey/dbg_io.c linux-2.6.12.6/arch/mips/vr4181/osprey/dbg_io.c --- linux-2.6.12.6.orig/arch/mips/vr4181/osprey/dbg_io.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr4181/osprey/dbg_io.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,136 +0,0 @@ -/* - * kgdb io functions for osprey. We use the serial port on debug board. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* ======================= CONFIG ======================== */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE 0xb7fffff0 -#define MAX_BAUD 115200 - -/* distance in bytes between two serial registers */ -#define REG_OFFSET 1 - -/* - * 0 - kgdb does serial init - * 1 - kgdb skip serial init - */ -static int remoteDebugInitialized = 1; - -/* - * the default baud rate *if* kgdb does serial init - */ -#define BAUD_DEFAULT UART16550_BAUD_38400 - -/* ======================= END OF CONFIG ======================== */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up buad rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} diff -Naur linux-2.6.12.6.orig/arch/mips/vr4181/osprey/prom.c linux-2.6.12.6/arch/mips/vr4181/osprey/prom.c --- linux-2.6.12.6.orig/arch/mips/vr4181/osprey/prom.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr4181/osprey/prom.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,49 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * arch/mips/vr4181/osprey/prom.c - * prom code for osprey. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include -#include -#include -#include - -const char *get_system_type(void) -{ - return "NEC_Vr41xx Osprey"; -} - -/* - * [jsun] right now we assume it is the nec debug monitor, which does - * not pass any arguments. - */ -void __init prom_init(void) -{ - // cmdline is now set in default config - // strcpy(arcs_cmdline, "ip=bootp "); - // strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 "); - // strcpy(arcs_cmdline, "ether=0,0x0300,eth0 " - // strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 "); - - mips_machgroup = MACH_GROUP_NEC_VR41XX; - mips_machtype = MACH_NEC_OSPREY; - - /* 16MB fixed */ - add_memory_region(0, 16 << 20, BOOT_MEM_RAM); -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} diff -Naur linux-2.6.12.6.orig/arch/mips/vr4181/osprey/reset.c linux-2.6.12.6/arch/mips/vr4181/osprey/reset.c --- linux-2.6.12.6.orig/arch/mips/vr4181/osprey/reset.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr4181/osprey/reset.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,40 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - */ -#include -#include -#include -#include -#include -#include -#include - -void nec_osprey_restart(char *command) -{ - set_c0_status(ST0_ERL); - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_c0_wired(0); - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -} - -void nec_osprey_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void nec_osprey_power_off(void) -{ - nec_osprey_halt(); -} diff -Naur linux-2.6.12.6.orig/arch/mips/vr4181/osprey/setup.c linux-2.6.12.6/arch/mips/vr4181/osprey/setup.c --- linux-2.6.12.6.orig/arch/mips/vr4181/osprey/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr4181/osprey/setup.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,68 +0,0 @@ -/* - * linux/arch/mips/vr4181/setup.c - * - * VR41xx setup routines - * - * Copyright (C) 1999 Bradley D. LaRonde - * Copyright (C) 1999, 2000 Michael Klar - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ - -#include -#include -#include -#include -#include -#include - - -extern void nec_osprey_restart(char* c); -extern void nec_osprey_halt(void); -extern void nec_osprey_power_off(void); - -extern void vr4181_init_serial(void); -extern void vr4181_init_time(void); - -static void __init nec_osprey_setup(void) -{ - set_io_port_base(VR4181_PORT_BASE); - isa_slot_offset = VR4181_ISAMEM_BASE; - - vr4181_init_serial(); - vr4181_init_time(); - - _machine_restart = nec_osprey_restart; - _machine_halt = nec_osprey_halt; - _machine_power_off = nec_osprey_power_off; - - /* setup resource limit */ - ioport_resource.end = 0xffffffff; - iomem_resource.end = 0xffffffff; - - /* [jsun] hack */ - /* - printk("[jsun] hack to change external ISA control register, %x -> %x\n", - (*VR4181_XISACTL), - (*VR4181_XISACTL) | 0x2); - *VR4181_XISACTL |= 0x2; - */ - - // *VR4181_GPHIBSTH = 0x2000; - // *VR4181_GPMD0REG = 0x00c0; - // *VR4181_GPINTEN = 1<<6; - - /* [jsun] I believe this will get the interrupt type right - * for the ether port. - */ - *VR4181_GPINTTYPL = 0x3000; -} - -early_initcall(nec_osprey_setup); diff -Naur linux-2.6.12.6.orig/arch/mips/vr41xx/Kconfig linux-2.6.12.6/arch/mips/vr41xx/Kconfig --- linux-2.6.12.6.orig/arch/mips/vr41xx/Kconfig 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr41xx/Kconfig 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,107 @@ +config NEC_CMBVR4133 + bool "Support for NEC CMB-VR4133" + depends on MACH_VR41XX + select CPU_VR41XX + select DMA_NONCOHERENT + select IRQ_CPU + select HW_HAS_PCI + select PCI_VR41XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN + +config ROCKHOPPER + bool "Support for Rockhopper baseboard" + depends on NEC_CMBVR4133 + select I8259 + select HAVE_STD_PC_SERIAL_PORT + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + +config CASIO_E55 + bool "Support for CASIO CASSIOPEIA E-10/15/55/65" + depends on MACH_VR41XX + select DMA_NONCOHERENT + select IRQ_CPU + select ISA + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN + +config IBM_WORKPAD + bool "Support for IBM WorkPad z50" + depends on MACH_VR41XX + select DMA_NONCOHERENT + select IRQ_CPU + select ISA + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN + +config TANBAC_TB0226 + bool "Support for TANBAC TB0226 (Mbase)" + depends on MACH_VR41XX + select DMA_NONCOHERENT + select HW_HAS_PCI + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN + help + The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by + TANBAC. Please refer to about Mbase. + +config TANBAC_TB0229 + bool "Support for TANBAC TB0229 (VR4131DIMM)" + depends on MACH_VR41XX + select DMA_NONCOHERENT + select HW_HAS_PCI + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN + help + The TANBAC TB0229 (VR4131DIMM) is a MIPS-based platform manufactured + by TANBAC. Please refer to about + VR4131DIMM. + +config VICTOR_MPC30X + bool "Support for Victor MP-C303/304" + depends on MACH_VR41XX + select DMA_NONCOHERENT + select HW_HAS_PCI + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN + depends on MACH_VR41XX + +config ZAO_CAPCELLA + bool "Support for ZAO Networks Capcella" + depends on MACH_VR41XX + select DMA_NONCOHERENT + select HW_HAS_PCI + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_LITTLE_ENDIAN + +config PCI_VR41XX + bool "Add PCI control unit support of NEC VR4100 series" + depends on MACH_VR41XX && PCI + +config GPIO_VR41XX + tristate "Add General-purpose I/O unit support of NEC VR4100 series" + depends on MACH_VR41XX + +config VRC4171 + tristate "Add NEC VRC4171 companion chip support" + depends on MACH_VR41XX && ISA + help + The NEC VRC4171/4171A is a companion chip for NEC VR4111/VR4121. + +config VRC4173 + tristate "Add NEC VRC4173 companion chip support" + depends on MACH_VR41XX && PCI_VR41XX + help + The NEC VRC4173 is a companion chip for NEC VR4122/VR4131. diff -Naur linux-2.6.12.6.orig/arch/mips/vr41xx/common/Makefile linux-2.6.12.6/arch/mips/vr41xx/common/Makefile --- linux-2.6.12.6.orig/arch/mips/vr41xx/common/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr41xx/common/Makefile 2005-10-02 23:47:38.000000000 +0000 @@ -2,7 +2,8 @@ # Makefile for common code of the NEC VR4100 series. # -obj-y += bcu.o cmu.o giu.o icu.o init.o int-handler.o pmu.o +obj-y += bcu.o cmu.o icu.o init.o int-handler.o irq.o pmu.o +obj-$(CONFIG_GPIO_VR41XX) += giu.o obj-$(CONFIG_VRC4173) += vrc4173.o EXTRA_AFLAGS := $(CFLAGS) diff -Naur linux-2.6.12.6.orig/arch/mips/vr41xx/common/giu.c linux-2.6.12.6/arch/mips/vr41xx/common/giu.c --- linux-2.6.12.6.orig/arch/mips/vr41xx/common/giu.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr41xx/common/giu.c 2005-10-02 23:47:38.000000000 +0000 @@ -3,8 +3,7 @@ * * Copyright (C) 2002 MontaVista Software Inc. * Author: Yoichi Yuasa - * Copyright (C) 2003-2004 Yoichi Yuasa - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2003-2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -63,12 +62,6 @@ static uint32_t giu_base; -static struct irqaction giu_cascade = { - .handler = no_action, - .mask = CPU_MASK_NONE, - .name = "cascade", -}; - #define read_giuint(offset) readw(giu_base + (offset)) #define write_giuint(val, offset) writew((val), giu_base + (offset)) @@ -192,18 +185,20 @@ .end = end_giuint_high_irq, }; -void __init init_vr41xx_giuint_irq(void) +void vr41xx_enable_giuint(unsigned int pin) { - int i; - - for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) { - if (i < (GIU_IRQ_BASE + GIUINT_HIGH_OFFSET)) - irq_desc[i].handler = &giuint_low_irq_type; - else - irq_desc[i].handler = &giuint_high_irq_type; - } + if (pin < GIUINT_HIGH_OFFSET) + enable_giuint_low_irq(GIU_IRQ(pin)); + else + enable_giuint_high_irq(GIU_IRQ(pin)); +} - setup_irq(GIUINT_CASCADE_IRQ, &giu_cascade); +void vr41xx_disable_giuint(unsigned int pin) +{ + if (pin < GIUINT_HIGH_OFFSET) + disable_giuint_low_irq(GIU_IRQ(pin)); + else + disable_giuint_high_irq(GIU_IRQ(pin)); } void vr41xx_set_irq_trigger(int pin, int trigger, int hold) @@ -296,52 +291,7 @@ EXPORT_SYMBOL(vr41xx_set_irq_level); -#define GIUINT_NR_IRQS 32 - -enum { - GIUINT_NO_CASCADE, - GIUINT_CASCADE -}; - -struct vr41xx_giuint_cascade { - unsigned int flag; - int (*get_irq_number)(int irq); -}; - -static struct vr41xx_giuint_cascade giuint_cascade[GIUINT_NR_IRQS]; - -static int no_irq_number(int irq) -{ - return -EINVAL; -} - -int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq)) -{ - unsigned int pin; - int retval; - - if (irq < GIU_IRQ(0) || irq > GIU_IRQ(31)) - return -EINVAL; - - if(!get_irq_number) - return -EINVAL; - - pin = GIU_IRQ_TO_PIN(irq); - giuint_cascade[pin].flag = GIUINT_CASCADE; - giuint_cascade[pin].get_irq_number = get_irq_number; - - retval = setup_irq(irq, &giu_cascade); - if (retval != 0) { - giuint_cascade[pin].flag = GIUINT_NO_CASCADE; - giuint_cascade[pin].get_irq_number = no_irq_number; - } - - return retval; -} - -EXPORT_SYMBOL(vr41xx_cascade_irq); - -static inline int get_irq_pin_number(void) +static int giu_get_irq(unsigned int irq, struct pt_regs *regs) { uint16_t pendl, pendh, maskl, maskh; int i; @@ -357,12 +307,12 @@ if (maskl) { for (i = 0; i < 16; i++) { if (maskl & ((uint16_t)1 << i)) - return i; + return GIU_IRQ(i); } } else if (maskh) { for (i = 0; i < 16; i++) { if (maskh & ((uint16_t)1 << i)) - return i + GIUINT_HIGH_OFFSET; + return GIU_IRQ(i + GIUINT_HIGH_OFFSET); } } @@ -374,54 +324,7 @@ return -1; } -static inline void ack_giuint_irq(int pin) -{ - if (pin < GIUINT_HIGH_OFFSET) { - clear_giuint(GIUINTENL, (uint16_t)1 << pin); - write_giuint((uint16_t)1 << pin, GIUINTSTATL); - } else { - pin -= GIUINT_HIGH_OFFSET; - clear_giuint(GIUINTENH, (uint16_t)1 << pin); - write_giuint((uint16_t)1 << pin, GIUINTSTATH); - } -} - -static inline void end_giuint_irq(int pin) -{ - if (pin < GIUINT_HIGH_OFFSET) - set_giuint(GIUINTENL, (uint16_t)1 << pin); - else - set_giuint(GIUINTENH, (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET)); -} - -void giuint_irq_dispatch(struct pt_regs *regs) -{ - struct vr41xx_giuint_cascade *cascade; - unsigned int giuint_irq; - int pin; - - pin = get_irq_pin_number(); - if (pin < 0) - return; - - disable_irq(GIUINT_CASCADE_IRQ); - - cascade = &giuint_cascade[pin]; - giuint_irq = GIU_IRQ(pin); - if (cascade->flag == GIUINT_CASCADE) { - int irq = cascade->get_irq_number(giuint_irq); - ack_giuint_irq(pin); - if (irq >= 0) - do_IRQ(irq, regs); - end_giuint_irq(pin); - } else { - do_IRQ(giuint_irq, regs); - } - - enable_irq(GIUINT_CASCADE_IRQ); -} - -static int __init vr41xx_giu_init(void) +static int __init vr41xx_giu_init(void) { int i; @@ -437,19 +340,24 @@ break; default: printk(KERN_ERR "GIU: Unexpected CPU of NEC VR4100 series\n"); - return -EINVAL; + return -ENODEV; } - for (i = 0; i < GIUINT_NR_IRQS; i++) { + for (i = 0; i < 32; i++) { if (i < GIUINT_HIGH_OFFSET) clear_giuint(GIUINTENL, (uint16_t)1 << i); else clear_giuint(GIUINTENH, (uint16_t)1 << (i - GIUINT_HIGH_OFFSET)); - giuint_cascade[i].flag = GIUINT_NO_CASCADE; - giuint_cascade[i].get_irq_number = no_irq_number; } - return 0; + for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) { + if (i < (GIU_IRQ_BASE + GIUINT_HIGH_OFFSET)) + irq_desc[i].handler = &giuint_low_irq_type; + else + irq_desc[i].handler = &giuint_high_irq_type; + } + + return cascade_irq(GIUINT_IRQ, giu_get_irq); } -early_initcall(vr41xx_giu_init); +postcore_initcall(vr41xx_giu_init); diff -Naur linux-2.6.12.6.orig/arch/mips/vr41xx/common/icu.c linux-2.6.12.6/arch/mips/vr41xx/common/icu.c --- linux-2.6.12.6.orig/arch/mips/vr41xx/common/icu.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr41xx/common/icu.c 2005-10-02 23:47:38.000000000 +0000 @@ -3,8 +3,7 @@ * * Copyright (C) 2001-2002 MontaVista Software Inc. * Author: Yoichi Yuasa - * Copyright (C) 2003-2004 Yoichi Yuasa - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2003-2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -43,30 +43,22 @@ #include #include -extern asmlinkage void vr41xx_handle_interrupt(void); - -extern void init_vr41xx_giuint_irq(void); -extern void giuint_irq_dispatch(struct pt_regs *regs); - -static uint32_t icu1_base; -static uint32_t icu2_base; - -static struct irqaction icu_cascade = { - .handler = no_action, - .mask = CPU_MASK_NONE, - .name = "cascade", -}; +static void __iomem *icu1_base; +static void __iomem *icu2_base; static unsigned char sysint1_assign[16] = { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; static unsigned char sysint2_assign[16] = { - 2, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -#define SYSINT1REG_TYPE1 KSEG1ADDR(0x0b000080) -#define SYSINT2REG_TYPE1 KSEG1ADDR(0x0b000200) +#define ICU1_TYPE1_BASE 0x0b000080UL +#define ICU2_TYPE1_BASE 0x0b000200UL -#define SYSINT1REG_TYPE2 KSEG1ADDR(0x0f000080) -#define SYSINT2REG_TYPE2 KSEG1ADDR(0x0f0000a0) +#define ICU1_TYPE2_BASE 0x0f000080UL +#define ICU2_TYPE2_BASE 0x0f0000a0UL + +#define ICU1_SIZE 0x20 +#define ICU2_SIZE 0x1c #define SYSINT1REG 0x00 #define PIUINTREG 0x02 @@ -106,61 +98,61 @@ #define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */ #define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */ -#define read_icu1(offset) readw(icu1_base + (offset)) -#define write_icu1(val, offset) writew((val), icu1_base + (offset)) +#define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */ + +#define icu1_read(offset) readw(icu1_base + (offset)) +#define icu1_write(offset, value) writew((value), icu1_base + (offset)) -#define read_icu2(offset) readw(icu2_base + (offset)) -#define write_icu2(val, offset) writew((val), icu2_base + (offset)) +#define icu2_read(offset) readw(icu2_base + (offset)) +#define icu2_write(offset, value) writew((value), icu2_base + (offset)) #define INTASSIGN_MAX 4 #define INTASSIGN_MASK 0x0007 -static inline uint16_t set_icu1(uint8_t offset, uint16_t set) +static inline uint16_t icu1_set(uint8_t offset, uint16_t set) { - uint16_t res; + uint16_t data; - res = read_icu1(offset); - res |= set; - write_icu1(res, offset); + data = icu1_read(offset); + data |= set; + icu1_write(offset, data); - return res; + return data; } -static inline uint16_t clear_icu1(uint8_t offset, uint16_t clear) +static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear) { - uint16_t res; + uint16_t data; - res = read_icu1(offset); - res &= ~clear; - write_icu1(res, offset); + data = icu1_read(offset); + data &= ~clear; + icu1_write(offset, data); - return res; + return data; } -static inline uint16_t set_icu2(uint8_t offset, uint16_t set) +static inline uint16_t icu2_set(uint8_t offset, uint16_t set) { - uint16_t res; + uint16_t data; - res = read_icu2(offset); - res |= set; - write_icu2(res, offset); + data = icu2_read(offset); + data |= set; + icu2_write(offset, data); - return res; + return data; } -static inline uint16_t clear_icu2(uint8_t offset, uint16_t clear) +static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear) { - uint16_t res; + uint16_t data; - res = read_icu2(offset); - res &= ~clear; - write_icu2(res, offset); + data = icu2_read(offset); + data &= ~clear; + icu2_write(offset, data); - return res; + return data; } -/*=======================================================================*/ - void vr41xx_enable_piuint(uint16_t mask) { irq_desc_t *desc = irq_desc + PIU_IRQ; @@ -169,7 +161,7 @@ if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - set_icu1(MPIUINTREG, mask); + icu1_set(MPIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -184,7 +176,7 @@ if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MPIUINTREG, mask); + icu1_clear(MPIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -199,7 +191,7 @@ if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - set_icu1(MAIUINTREG, mask); + icu1_set(MAIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -214,7 +206,7 @@ if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MAIUINTREG, mask); + icu1_clear(MAIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -229,7 +221,7 @@ if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - set_icu1(MKIUINTREG, mask); + icu1_set(MKIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -244,7 +236,7 @@ if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MKIUINTREG, mask); + icu1_clear(MKIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -257,7 +249,7 @@ unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - set_icu1(MDSIUINTREG, mask); + icu1_set(MDSIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -269,7 +261,7 @@ unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MDSIUINTREG, mask); + icu1_clear(MDSIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -281,7 +273,7 @@ unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - set_icu2(MFIRINTREG, mask); + icu2_set(MFIRINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -293,7 +285,7 @@ unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - clear_icu2(MFIRINTREG, mask); + icu2_clear(MFIRINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -308,7 +300,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(PCIINT0, MPCIINTREG); + icu2_write(MPCIINTREG, PCIINT0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -324,7 +316,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(0, MPCIINTREG); + icu2_write(MPCIINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -340,7 +332,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(SCUINT0, MSCUINTREG); + icu2_write(MSCUINTREG, SCUINT0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -356,7 +348,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(0, MSCUINTREG); + icu2_write(MSCUINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -372,7 +364,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - set_icu2(MCSIINTREG, mask); + icu2_set(MCSIINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -388,7 +380,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - clear_icu2(MCSIINTREG, mask); + icu2_clear(MCSIINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -404,7 +396,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(BCUINTR, MBCUINTREG); + icu2_write(MBCUINTREG, BCUINTR); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -420,30 +412,28 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(0, MBCUINTREG); + icu2_write(MBCUINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); } } EXPORT_SYMBOL(vr41xx_disable_bcuint); -/*=======================================================================*/ - static unsigned int startup_sysint1_irq(unsigned int irq) { - set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); return 0; /* never anything pending */ } static void shutdown_sysint1_irq(unsigned int irq) { - clear_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } static void enable_sysint1_irq(unsigned int irq) { - set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } #define disable_sysint1_irq shutdown_sysint1_irq @@ -452,7 +442,7 @@ static void end_sysint1_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } static struct hw_interrupt_type sysint1_irq_type = { @@ -465,23 +455,21 @@ .end = end_sysint1_irq, }; -/*=======================================================================*/ - static unsigned int startup_sysint2_irq(unsigned int irq) { - set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); return 0; /* never anything pending */ } static void shutdown_sysint2_irq(unsigned int irq) { - clear_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } static void enable_sysint2_irq(unsigned int irq) { - set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } #define disable_sysint2_irq shutdown_sysint2_irq @@ -490,7 +478,7 @@ static void end_sysint2_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } static struct hw_interrupt_type sysint2_irq_type = { @@ -503,8 +491,6 @@ .end = end_sysint2_irq, }; -/*=======================================================================*/ - static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) { irq_desc_t *desc = irq_desc + irq; @@ -515,8 +501,8 @@ spin_lock_irq(&desc->lock); - intassign0 = read_icu1(INTASSIGN0); - intassign1 = read_icu1(INTASSIGN1); + intassign0 = icu1_read(INTASSIGN0); + intassign1 = icu1_read(INTASSIGN1); switch (pin) { case 0: @@ -556,8 +542,8 @@ } sysint1_assign[pin] = assign; - write_icu1(intassign0, INTASSIGN0); - write_icu1(intassign1, INTASSIGN1); + icu1_write(INTASSIGN0, intassign0); + icu1_write(INTASSIGN1, intassign1); spin_unlock_irq(&desc->lock); @@ -574,8 +560,8 @@ spin_lock_irq(&desc->lock); - intassign2 = read_icu1(INTASSIGN2); - intassign3 = read_icu1(INTASSIGN3); + intassign2 = icu1_read(INTASSIGN2); + intassign3 = icu1_read(INTASSIGN3); switch (pin) { case 0: @@ -623,8 +609,8 @@ } sysint2_assign[pin] = assign; - write_icu1(intassign2, INTASSIGN2); - write_icu1(intassign3, INTASSIGN3); + icu1_write(INTASSIGN2, intassign2); + icu1_write(INTASSIGN3, intassign3); spin_unlock_irq(&desc->lock); @@ -651,88 +637,92 @@ EXPORT_SYMBOL(vr41xx_set_intassign); -/*=======================================================================*/ - -asmlinkage void irq_dispatch(unsigned char intnum, struct pt_regs *regs) +static int icu_get_irq(unsigned int irq, struct pt_regs *regs) { uint16_t pend1, pend2; uint16_t mask1, mask2; int i; - pend1 = read_icu1(SYSINT1REG); - mask1 = read_icu1(MSYSINT1REG); + pend1 = icu1_read(SYSINT1REG); + mask1 = icu1_read(MSYSINT1REG); - pend2 = read_icu2(SYSINT2REG); - mask2 = read_icu2(MSYSINT2REG); + pend2 = icu2_read(SYSINT2REG); + mask2 = icu2_read(MSYSINT2REG); mask1 &= pend1; mask2 &= pend2; if (mask1) { for (i = 0; i < 16; i++) { - if (intnum == sysint1_assign[i] && - (mask1 & ((uint16_t)1 << i))) { - if (i == 8) - giuint_irq_dispatch(regs); - else - do_IRQ(SYSINT1_IRQ(i), regs); - return; - } + if (irq == INT_TO_IRQ(sysint1_assign[i]) && (mask1 & (1 << i))) + return SYSINT1_IRQ(i); } } if (mask2) { for (i = 0; i < 16; i++) { - if (intnum == sysint2_assign[i] && - (mask2 & ((uint16_t)1 << i))) { - do_IRQ(SYSINT2_IRQ(i), regs); - return; - } + if (irq == INT_TO_IRQ(sysint2_assign[i]) && (mask2 & (1 << i))) + return SYSINT2_IRQ(i); } } printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2); atomic_inc(&irq_err_count); -} -/*=======================================================================*/ + return -1; +} static int __init vr41xx_icu_init(void) { + unsigned long icu1_start, icu2_start; + int i; + switch (current_cpu_data.cputype) { case CPU_VR4111: case CPU_VR4121: - icu1_base = SYSINT1REG_TYPE1; - icu2_base = SYSINT2REG_TYPE1; + icu1_start = ICU1_TYPE1_BASE; + icu2_start = ICU2_TYPE1_BASE; break; case CPU_VR4122: case CPU_VR4131: case CPU_VR4133: - icu1_base = SYSINT1REG_TYPE2; - icu2_base = SYSINT2REG_TYPE2; + icu1_start = ICU1_TYPE2_BASE; + icu2_start = ICU2_TYPE2_BASE; break; default: printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n"); - return -EINVAL; + return -ENODEV; } - write_icu1(0, MSYSINT1REG); - write_icu1(0xffff, MGIUINTLREG); + if (request_mem_region(icu1_start, ICU1_SIZE, "ICU") == NULL) + return -EBUSY; - write_icu2(0, MSYSINT2REG); - write_icu2(0xffff, MGIUINTHREG); + if (request_mem_region(icu2_start, ICU2_SIZE, "ICU") == NULL) { + release_mem_region(icu1_start, ICU1_SIZE); + return -EBUSY; + } - return 0; -} + icu1_base = ioremap(icu1_start, ICU1_SIZE); + if (icu1_base == NULL) { + release_mem_region(icu1_start, ICU1_SIZE); + release_mem_region(icu2_start, ICU2_SIZE); + return -ENOMEM; + } -early_initcall(vr41xx_icu_init); + icu2_base = ioremap(icu2_start, ICU2_SIZE); + if (icu2_base == NULL) { + iounmap(icu1_base); + release_mem_region(icu1_start, ICU1_SIZE); + release_mem_region(icu2_start, ICU2_SIZE); + return -ENOMEM; + } -/*=======================================================================*/ + icu1_write(MSYSINT1REG, 0); + icu1_write(MGIUINTLREG, 0xffff); -static inline void init_vr41xx_icu_irq(void) -{ - int i; + icu2_write(MSYSINT2REG, 0); + icu2_write(MGIUINTHREG, 0xffff); for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) irq_desc[i].handler = &sysint1_irq_type; @@ -740,18 +730,13 @@ for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) irq_desc[i].handler = &sysint2_irq_type; - setup_irq(INT0_CASCADE_IRQ, &icu_cascade); - setup_irq(INT1_CASCADE_IRQ, &icu_cascade); - setup_irq(INT2_CASCADE_IRQ, &icu_cascade); - setup_irq(INT3_CASCADE_IRQ, &icu_cascade); - setup_irq(INT4_CASCADE_IRQ, &icu_cascade); -} + cascade_irq(INT0_IRQ, icu_get_irq); + cascade_irq(INT1_IRQ, icu_get_irq); + cascade_irq(INT2_IRQ, icu_get_irq); + cascade_irq(INT3_IRQ, icu_get_irq); + cascade_irq(INT4_IRQ, icu_get_irq); -void __init arch_init_irq(void) -{ - mips_cpu_irq_init(MIPS_CPU_IRQ_BASE); - init_vr41xx_icu_irq(); - init_vr41xx_giuint_irq(); - - set_except_vector(0, vr41xx_handle_interrupt); + return 0; } + +core_initcall(vr41xx_icu_init); diff -Naur linux-2.6.12.6.orig/arch/mips/vr41xx/common/int-handler.S linux-2.6.12.6/arch/mips/vr41xx/common/int-handler.S --- linux-2.6.12.6.orig/arch/mips/vr41xx/common/int-handler.S 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr41xx/common/int-handler.S 2005-10-02 23:47:38.000000000 +0000 @@ -71,24 +71,24 @@ andi t1, t0, CAUSEF_IP3 # check for Int1 bnez t1, handle_int - li a0, 1 + li a0, 3 andi t1, t0, CAUSEF_IP4 # check for Int2 bnez t1, handle_int - li a0, 2 + li a0, 4 andi t1, t0, CAUSEF_IP5 # check for Int3 bnez t1, handle_int - li a0, 3 + li a0, 5 andi t1, t0, CAUSEF_IP6 # check for Int4 bnez t1, handle_int - li a0, 4 + li a0, 6 1: andi t1, t0, CAUSEF_IP2 # check for Int0 bnez t1, handle_int - li a0, 0 + li a0, 2 andi t1, t0, CAUSEF_IP0 # check for IP0 bnez t1, handle_irq diff -Naur linux-2.6.12.6.orig/arch/mips/vr41xx/common/irq.c linux-2.6.12.6/arch/mips/vr41xx/common/irq.c --- linux-2.6.12.6.orig/arch/mips/vr41xx/common/irq.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr41xx/common/irq.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,86 @@ +/* + * Interrupt handing routines for NEC VR4100 series. + * + * Copyright (C) 2005 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include + +#include +#include +#include + +typedef struct irq_cascade { + int (*get_irq)(unsigned int, struct pt_regs *); +} irq_cascade_t; + +static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned; + +static struct irqaction cascade_irqaction = { + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "cascade", +}; + +int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)) +{ + int retval = 0; + + if (irq >= NR_IRQS) + return -EINVAL; + + if (irq_cascade[irq].get_irq != NULL) + free_irq(irq, NULL); + + irq_cascade[irq].get_irq = get_irq; + + if (get_irq != NULL) { + retval = setup_irq(irq, &cascade_irqaction); + if (retval < 0) + irq_cascade[irq].get_irq = NULL; + } + + return retval; +} + +asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs) +{ + irq_cascade_t *cascade; + + if (irq >= NR_IRQS) { + atomic_inc(&irq_err_count); + return; + } + + cascade = irq_cascade + irq; + if (cascade->get_irq != NULL) { + irq = cascade->get_irq(irq, regs); + if (irq < 0) + atomic_inc(&irq_err_count); + else + irq_dispatch(irq, regs); + } else + do_IRQ(irq, regs); +} + +extern asmlinkage void vr41xx_handle_interrupt(void); + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(MIPS_CPU_IRQ_BASE); + + set_except_vector(0, vr41xx_handle_interrupt); +} diff -Naur linux-2.6.12.6.orig/arch/mips/vr41xx/common/ksyms.c linux-2.6.12.6/arch/mips/vr41xx/common/ksyms.c --- linux-2.6.12.6.orig/arch/mips/vr41xx/common/ksyms.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr41xx/common/ksyms.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,33 @@ +/* + * ksyms.c, Export NEC VR4100 series specific functions needed for loadable modules. + * + * Copyright (C) 2003 Yoichi Yuasa + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include + +#include + +EXPORT_SYMBOL(vr41xx_get_vtclock_frequency); +EXPORT_SYMBOL(vr41xx_get_tclock_frequency); + +EXPORT_SYMBOL(vr41xx_set_rtclong1_cycle); +EXPORT_SYMBOL(vr41xx_read_rtclong1_counter); +EXPORT_SYMBOL(vr41xx_set_rtclong2_cycle); +EXPORT_SYMBOL(vr41xx_read_rtclong2_counter); +EXPORT_SYMBOL(vr41xx_set_tclock_cycle); +EXPORT_SYMBOL(vr41xx_read_tclock_counter); diff -Naur linux-2.6.12.6.orig/arch/mips/vr41xx/common/rtc.c linux-2.6.12.6/arch/mips/vr41xx/common/rtc.c --- linux-2.6.12.6.orig/arch/mips/vr41xx/common/rtc.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr41xx/common/rtc.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,317 @@ +/* + * rtc.c, RTC(has only timer function) routines for NEC VR4100 series. + * + * Copyright (C) 2003-2004 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include + +#include +#include +#include + +static uint32_t rtc1_base; +static uint32_t rtc2_base; + +static uint64_t previous_elapsedtime; +static unsigned int remainder_per_sec; +static unsigned int cycles_per_sec; +static unsigned int cycles_per_jiffy; +static unsigned long epoch_time; + +#define CYCLES_PER_JIFFY (CLOCK_TICK_RATE / HZ) +#define REMAINDER_PER_SEC (CLOCK_TICK_RATE - (CYCLES_PER_JIFFY * HZ)) +#define CYCLES_PER_100USEC ((CLOCK_TICK_RATE + (10000 / 2)) / 10000) + +#define ETIMELREG_TYPE1 KSEG1ADDR(0x0b0000c0) +#define TCLKLREG_TYPE1 KSEG1ADDR(0x0b0001c0) + +#define ETIMELREG_TYPE2 KSEG1ADDR(0x0f000100) +#define TCLKLREG_TYPE2 KSEG1ADDR(0x0f000120) + +/* RTC 1 registers */ +#define ETIMELREG 0x00 +#define ETIMEMREG 0x02 +#define ETIMEHREG 0x04 +/* RFU */ +#define ECMPLREG 0x08 +#define ECMPMREG 0x0a +#define ECMPHREG 0x0c +/* RFU */ +#define RTCL1LREG 0x10 +#define RTCL1HREG 0x12 +#define RTCL1CNTLREG 0x14 +#define RTCL1CNTHREG 0x16 +#define RTCL2LREG 0x18 +#define RTCL2HREG 0x1a +#define RTCL2CNTLREG 0x1c +#define RTCL2CNTHREG 0x1e + +/* RTC 2 registers */ +#define TCLKLREG 0x00 +#define TCLKHREG 0x02 +#define TCLKCNTLREG 0x04 +#define TCLKCNTHREG 0x06 +/* RFU */ +#define RTCINTREG 0x1e + #define TCLOCK_INT 0x08 + #define RTCLONG2_INT 0x04 + #define RTCLONG1_INT 0x02 + #define ELAPSEDTIME_INT 0x01 + +#define read_rtc1(offset) readw(rtc1_base + (offset)) +#define write_rtc1(val, offset) writew((val), rtc1_base + (offset)) + +#define read_rtc2(offset) readw(rtc2_base + (offset)) +#define write_rtc2(val, offset) writew((val), rtc2_base + (offset)) + +static inline uint64_t read_elapsedtime_counter(void) +{ + uint64_t first, second; + uint32_t first_mid, first_low; + uint32_t second_mid, second_low; + + do { + first_low = (uint32_t)read_rtc1(ETIMELREG); + first_mid = (uint32_t)read_rtc1(ETIMEMREG); + first = (uint64_t)read_rtc1(ETIMEHREG); + second_low = (uint32_t)read_rtc1(ETIMELREG); + second_mid = (uint32_t)read_rtc1(ETIMEMREG); + second = (uint64_t)read_rtc1(ETIMEHREG); + } while (first_low != second_low || first_mid != second_mid || + first != second); + + return (first << 32) | (uint64_t)((first_mid << 16) | first_low); +} + +static inline void write_elapsedtime_counter(uint64_t time) +{ + write_rtc1((uint16_t)time, ETIMELREG); + write_rtc1((uint16_t)(time >> 16), ETIMEMREG); + write_rtc1((uint16_t)(time >> 32), ETIMEHREG); +} + +static inline void write_elapsedtime_compare(uint64_t time) +{ + write_rtc1((uint16_t)time, ECMPLREG); + write_rtc1((uint16_t)(time >> 16), ECMPMREG); + write_rtc1((uint16_t)(time >> 32), ECMPHREG); +} + +void vr41xx_set_rtclong1_cycle(uint32_t cycles) +{ + write_rtc1((uint16_t)cycles, RTCL1LREG); + write_rtc1((uint16_t)(cycles >> 16), RTCL1HREG); +} + +uint32_t vr41xx_read_rtclong1_counter(void) +{ + uint32_t first_high, first_low; + uint32_t second_high, second_low; + + do { + first_low = (uint32_t)read_rtc1(RTCL1CNTLREG); + first_high = (uint32_t)read_rtc1(RTCL1CNTHREG); + second_low = (uint32_t)read_rtc1(RTCL1CNTLREG); + second_high = (uint32_t)read_rtc1(RTCL1CNTHREG); + } while (first_low != second_low || first_high != second_high); + + return (first_high << 16) | first_low; +} + +void vr41xx_set_rtclong2_cycle(uint32_t cycles) +{ + write_rtc1((uint16_t)cycles, RTCL2LREG); + write_rtc1((uint16_t)(cycles >> 16), RTCL2HREG); +} + +uint32_t vr41xx_read_rtclong2_counter(void) +{ + uint32_t first_high, first_low; + uint32_t second_high, second_low; + + do { + first_low = (uint32_t)read_rtc1(RTCL2CNTLREG); + first_high = (uint32_t)read_rtc1(RTCL2CNTHREG); + second_low = (uint32_t)read_rtc1(RTCL2CNTLREG); + second_high = (uint32_t)read_rtc1(RTCL2CNTHREG); + } while (first_low != second_low || first_high != second_high); + + return (first_high << 16) | first_low; +} + +void vr41xx_set_tclock_cycle(uint32_t cycles) +{ + write_rtc2((uint16_t)cycles, TCLKLREG); + write_rtc2((uint16_t)(cycles >> 16), TCLKHREG); +} + +uint32_t vr41xx_read_tclock_counter(void) +{ + uint32_t first_high, first_low; + uint32_t second_high, second_low; + + do { + first_low = (uint32_t)read_rtc2(TCLKCNTLREG); + first_high = (uint32_t)read_rtc2(TCLKCNTHREG); + second_low = (uint32_t)read_rtc2(TCLKCNTLREG); + second_high = (uint32_t)read_rtc2(TCLKCNTHREG); + } while (first_low != second_low || first_high != second_high); + + return (first_high << 16) | first_low; +} + +static void vr41xx_timer_ack(void) +{ + uint64_t cur; + + write_rtc2(ELAPSEDTIME_INT, RTCINTREG); + + previous_elapsedtime += (uint64_t)cycles_per_jiffy; + cycles_per_sec += cycles_per_jiffy; + + if (cycles_per_sec >= CLOCK_TICK_RATE) { + cycles_per_sec = 0; + remainder_per_sec = REMAINDER_PER_SEC; + } + + cycles_per_jiffy = 0; + + do { + cycles_per_jiffy += CYCLES_PER_JIFFY; + if (remainder_per_sec > 0) { + cycles_per_jiffy++; + remainder_per_sec--; + } + + cur = read_elapsedtime_counter(); + } while (cur >= previous_elapsedtime + (uint64_t)cycles_per_jiffy); + + write_elapsedtime_compare(previous_elapsedtime + (uint64_t)cycles_per_jiffy); +} + +static void vr41xx_hpt_init(unsigned int count) +{ +} + +static unsigned int vr41xx_hpt_read(void) +{ + uint64_t cur; + + cur = read_elapsedtime_counter(); + + return (unsigned int)cur; +} + +static unsigned long vr41xx_gettimeoffset(void) +{ + uint64_t cur; + unsigned long gap; + + cur = read_elapsedtime_counter(); + gap = (unsigned long)(cur - previous_elapsedtime); + gap = gap / CYCLES_PER_100USEC * 100; /* usec */ + + return gap; +} + +static unsigned long vr41xx_get_time(void) +{ + uint64_t counts; + + counts = read_elapsedtime_counter(); + counts >>= 15; + + return epoch_time + (unsigned long)counts; + +} + +static int vr41xx_set_time(unsigned long sec) +{ + if (sec < epoch_time) + return -EINVAL; + + sec -= epoch_time; + + write_elapsedtime_counter((uint64_t)sec << 15); + + return 0; +} + +void vr41xx_set_epoch_time(unsigned long time) +{ + epoch_time = time; +} + +static void __init vr41xx_time_init(void) +{ + switch (current_cpu_data.cputype) { + case CPU_VR4111: + case CPU_VR4121: + rtc1_base = ETIMELREG_TYPE1; + rtc2_base = TCLKLREG_TYPE1; + break; + case CPU_VR4122: + case CPU_VR4131: + case CPU_VR4133: + rtc1_base = ETIMELREG_TYPE2; + rtc2_base = TCLKLREG_TYPE2; + break; + default: + panic("Unexpected CPU of NEC VR4100 series"); + break; + } + + mips_timer_ack = vr41xx_timer_ack; + + mips_hpt_init = vr41xx_hpt_init; + mips_hpt_read = vr41xx_hpt_read; + mips_hpt_frequency = CLOCK_TICK_RATE; + + if (epoch_time == 0) + epoch_time = mktime(1970, 1, 1, 0, 0, 0); + + rtc_get_time = vr41xx_get_time; + rtc_set_time = vr41xx_set_time; +} + +static void __init vr41xx_timer_setup(struct irqaction *irq) +{ + do_gettimeoffset = vr41xx_gettimeoffset; + + remainder_per_sec = REMAINDER_PER_SEC; + cycles_per_jiffy = CYCLES_PER_JIFFY; + + if (remainder_per_sec > 0) { + cycles_per_jiffy++; + remainder_per_sec--; + } + + previous_elapsedtime = read_elapsedtime_counter(); + write_elapsedtime_compare(previous_elapsedtime + (uint64_t)cycles_per_jiffy); + write_rtc2(ELAPSEDTIME_INT, RTCINTREG); + + setup_irq(ELAPSEDTIME_IRQ, irq); +} + +static void __init vr41xx_rtc_init(void) +{ + board_time_init = vr41xx_time_init; + board_timer_setup = vr41xx_timer_setup; +} diff -Naur linux-2.6.12.6.orig/arch/mips/vr41xx/nec-cmbvr4133/init.c linux-2.6.12.6/arch/mips/vr41xx/nec-cmbvr4133/init.c --- linux-2.6.12.6.orig/arch/mips/vr41xx/nec-cmbvr4133/init.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr41xx/nec-cmbvr4133/init.c 2005-10-02 23:47:38.000000000 +0000 @@ -12,7 +12,7 @@ * is licensed "as is" without any warranty of any kind, whether express * or implied. * - * Support for NEC-CMBVR4133 in 2.6 + * Support for NEC-CMBVR4133 in 2.6 * Manish Lachwani (mlachwani@mvista.com) */ #include @@ -40,7 +40,7 @@ { u32 data; - /* + /* * Workaround for the bug in PMON on VR4133. PMON leaves * AMD PCNet controller (on Rockhopper) initialized and running in * bus master mode. We have do disable it before doing any @@ -69,7 +69,7 @@ (4 & 0xfc) | 1UL, PCICONFAREG); - + data &= ~4; writel(data, PCICONFDREG); diff -Naur linux-2.6.12.6.orig/arch/mips/vr41xx/nec-cmbvr4133/irq.c linux-2.6.12.6/arch/mips/vr41xx/nec-cmbvr4133/irq.c --- linux-2.6.12.6.orig/arch/mips/vr41xx/nec-cmbvr4133/irq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr41xx/nec-cmbvr4133/irq.c 2005-10-02 23:47:38.000000000 +0000 @@ -27,9 +27,9 @@ extern void disable_8259A_irq(unsigned int irq); extern void mask_and_ack_8259A(unsigned int irq); extern void init_8259A(int hoge); - + extern int vr4133_rockhopper; - + static unsigned int startup_i8259_irq(unsigned int irq) { enable_8259A_irq(irq - I8259_IRQ_BASE); diff -Naur linux-2.6.12.6.orig/arch/mips/vr41xx/nec-cmbvr4133/setup.c linux-2.6.12.6/arch/mips/vr41xx/nec-cmbvr4133/setup.c --- linux-2.6.12.6.orig/arch/mips/vr41xx/nec-cmbvr4133/setup.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/arch/mips/vr41xx/nec-cmbvr4133/setup.c 2005-10-02 23:47:38.000000000 +0000 @@ -16,6 +16,7 @@ */ #include #include +#include #include #include @@ -36,13 +37,13 @@ .size = 0x1be0000, .offset = 0, .mask_flags = 0, - }, + }, { .name = "PMON", .size = 0x140000, .offset = MTDPART_OFS_APPEND, .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, + }, { .name = "User FS2", .size = MTDPART_SIZ_FULL, @@ -56,7 +57,7 @@ extern void i8259_init(void); -static int __init nec_cmbvr4133_setup(void) +static void __init nec_cmbvr4133_setup(void) { #ifdef CONFIG_ROCKHOPPER extern void disable_pcnet(void); @@ -90,7 +91,4 @@ #ifdef CONFIG_ROCKHOPPER i8259_init(); #endif - return 0; } - -early_initcall(nec_cmbvr4133_setup); diff -Naur linux-2.6.12.6.orig/arch/um/kernel/checksum.c linux-2.6.12.6/arch/um/kernel/checksum.c --- linux-2.6.12.6.orig/arch/um/kernel/checksum.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/arch/um/kernel/checksum.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,36 @@ +#include "asm/uaccess.h" +#include "linux/errno.h" +#include "linux/module.h" + +unsigned int arch_csum_partial(const unsigned char *buff, int len, int sum); + +unsigned int csum_partial(unsigned char *buff, int len, int sum) +{ + return arch_csum_partial(buff, len, sum); +} + +EXPORT_SYMBOL(csum_partial); + +unsigned int csum_partial_copy_to(const unsigned char *src, + unsigned char __user *dst, int len, int sum, + int *err_ptr) +{ + if(copy_to_user(dst, src, len)){ + *err_ptr = -EFAULT; + return(-1); + } + + return(arch_csum_partial(src, len, sum)); +} + +unsigned int csum_partial_copy_from(const unsigned char __user *src, + unsigned char *dst, int len, int sum, + int *err_ptr) +{ + if(copy_from_user(dst, src, len)){ + *err_ptr = -EFAULT; + return(-1); + } + + return arch_csum_partial(dst, len, sum); +} diff -Naur linux-2.6.12.6.orig/drivers/char/Kconfig linux-2.6.12.6/drivers/char/Kconfig --- linux-2.6.12.6.orig/drivers/char/Kconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/char/Kconfig 2005-10-02 23:47:38.000000000 +0000 @@ -331,23 +331,68 @@ To compile this driver as a module, choose M here: the module will be called istallion. -config AU1000_UART - bool "Enable Au1000 UART Support" - depends on SERIAL_NONSTANDARD && MIPS - help - If you have an Alchemy AU1000 processor (MIPS based) and you want - to use serial ports, say Y. Otherwise, say N. - -config AU1000_SERIAL_CONSOLE - bool "Enable Au1000 serial console" - depends on AU1000_UART +config AU1X00_GPIO + tristate "Alchemy Au1000 GPIO device support" + depends on MIPS && SOC_AU1X00 + +config TS_AU1X00_ADS7846 + tristate "Au1000/ADS7846 touchscreen support" + depends on MIPS && SOC_AU1X00 + +config AU1X00_USB_TTY + tristate "Au1000 USB TTY Device support" + depends on MIPS && MIPS_AU1000 && AU1000_USB_DEVICE=y && AU1000_USB_DEVICE + +config AU1X00_USB_RAW + tristate "Au1000 USB Raw Device support" + depends on MIPS && MIPS_AU1000 && AU1000_USB_DEVICE=y && AU1000_USB_TTY!=y && AU1X00_USB_DEVICE + +config SIBYTE_SB1250_DUART + bool "Support for BCM1xxx onchip DUART" + depends on MIPS && SIBYTE_SB1xxx_SOC=y + +config SIBYTE_SB1250_DUART_CONSOLE + bool "Console on BCM1xxx DUART" + depends on SIBYTE_SB1250_DUART + +config SERIAL_DEC + bool "DECstation serial support" + depends on MACH_DECSTATION + default y + help + This selects whether you want to be asked about drivers for + DECstation serial ports. + + Note that the answer to this question won't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about DECstation serial ports. + + If unsure, say Y. + +config SERIAL_DEC_CONSOLE + bool "Support for console on a DECstation serial port" + depends on SERIAL_DEC + default y help - If you have an Alchemy AU1000 processor (MIPS based) and you want - to use a console on a serial port, say Y. Otherwise, say N. + If you say Y here, it will be possible to use a serial port as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). Note that the firmware uses ttyS0 as the serial console on + the Maxine and ttyS2 on the others. + + If unsure, say Y. + +config ZS + bool "Z85C30 Serial Support" + depends on SERIAL_DEC + default y + help + Documentation on the Zilog 85C350 serial communications controller + is downloadable at . config QTRONIX_KEYBOARD bool "Enable Qtronix 990P Keyboard Support" - depends on IT8712 + depends on MIPS && (MIPS_ITE8172 || MIPS_IVR) help Images of Qtronix keyboards are at . @@ -359,7 +404,7 @@ config IT8172_SCR0 bool "Enable Smart Card Reader 0 Support " - depends on IT8712 + depends on MIPS && (MIPS_ITE8172 || MIPS_IVR) help Say Y here to support smart-card reader 0 (SCR0) on the Integrated Technology Express, Inc. ITE8172 SBC. Vendor page at @@ -368,13 +413,17 @@ config IT8172_SCR1 bool "Enable Smart Card Reader 1 Support " - depends on IT8712 + depends on MIPS && (MIPS_ITE8172 || MIPS_IVR) && MIPS_ITE8172 help Say Y here to support smart-card reader 1 (SCR1) on the Integrated Technology Express, Inc. ITE8172 SBC. Vendor page at ; picture of the board at . +config ITE_GPIO + tristate "ITE GPIO" + depends on MIPS && MIPS_ITE8172 + config A2232 tristate "Commodore A2232 serial support (EXPERIMENTAL)" depends on EXPERIMENTAL && ZORRO && BROKEN_ON_SMP @@ -779,10 +828,6 @@ Samsung S3C2410. This can provide periodic interrupt rates from 1Hz to 64Hz for user programs, and wakeup from Alarm. -config RTC_VR41XX - tristate "NEC VR4100 series Real Time Clock Support" - depends on CPU_VR41XX - config COBALT_LCD bool "Support for Cobalt LCD" depends on MIPS_COBALT diff -Naur linux-2.6.12.6.orig/drivers/char/Makefile linux-2.6.12.6/drivers/char/Makefile --- linux-2.6.12.6.orig/drivers/char/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/char/Makefile 2005-10-02 23:47:38.000000000 +0000 @@ -31,6 +31,7 @@ obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o obj-$(CONFIG_MOXA_SMARTIO) += mxser.o +obj-$(CONFIG_SIBYTE_SB1250_DUART) += sb1250_duart.o obj-$(CONFIG_COMPUTONE) += ip2.o ip2main.o obj-$(CONFIG_RISCOM8) += riscom8.o obj-$(CONFIG_ISI) += isicom.o @@ -48,6 +49,7 @@ obj-$(CONFIG_VIOTAPE) += viotape.o obj-$(CONFIG_HVCS) += hvcs.o obj-$(CONFIG_SGI_MBCS) += mbcs.o +obj-$(CONFIG_SERIAL_DEC) += decserial.o obj-$(CONFIG_PRINTER) += lp.o obj-$(CONFIG_TIPAR) += tipar.o @@ -64,7 +66,6 @@ obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o obj-$(CONFIG_DS1302) += ds1302.o obj-$(CONFIG_S3C2410_RTC) += s3c2410-rtc.o -obj-$(CONFIG_RTC_VR41XX) += vr41xx_rtc.o ifeq ($(CONFIG_GENERIC_NVRAM),y) obj-$(CONFIG_NVRAM) += generic_nvram.o else @@ -76,11 +77,14 @@ obj-$(CONFIG_HW_RANDOM) += hw_random.o obj-$(CONFIG_FTAPE) += ftape/ obj-$(CONFIG_COBALT_LCD) += lcd.o +obj-$(CONFIG_ITE_GPIO) += ite_gpio.o +obj-$(CONFIG_AU1000_GPIO) += au1000_gpio.o +obj-$(CONFIG_AU1000_USB_TTY) += au1000_usbtty.o +obj-$(CONFIG_AU1000_USB_RAW) += au1000_usbraw.o obj-$(CONFIG_PPDEV) += ppdev.o obj-$(CONFIG_NWBUTTON) += nwbutton.o obj-$(CONFIG_NWFLASH) += nwflash.o obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o -obj-$(CONFIG_TANBAC_TB0219) += tb0219.o obj-$(CONFIG_WATCHDOG) += watchdog/ obj-$(CONFIG_MWAVE) += mwave/ @@ -92,7 +96,7 @@ obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o obj-$(CONFIG_TCG_TPM) += tpm/ # Files generated that shall be removed upon make clean -clean-files := consolemap_deftbl.c defkeymap.c qtronixmap.c +clean-files := consolemap_deftbl.c defkeymap.c qtronixmap.c ibm_workpad_keymap.c quiet_cmd_conmk = CONMK $@ cmd_conmk = scripts/conmakehash $< > $@ @@ -104,6 +108,8 @@ $(obj)/qtronixmap.o: $(obj)/qtronixmap.c +$(obj)/ibm_workpad_keymap.o: $(obj)/ibm_workpad_keymap.c + # Uncomment if you're changing the keymap and have an appropriate # loadkeys version for the map. By default, we'll use the shipped # versions. @@ -111,7 +117,8 @@ ifdef GENERATE_KEYMAP -$(obj)/defkeymap.c $(obj)/qtronixmap.c: $(obj)/%.c: $(src)/%.map +$(obj)/defkeymap.c $(obj)/qtronixmap.c $(obj)/ibm_workpad_keymap.c: \ + $(obj)/%.c: $(src)/%.map loadkeys --mktable $< > $@.tmp sed -e 's/^static *//' $@.tmp > $@ rm $@.tmp diff -Naur linux-2.6.12.6.orig/drivers/char/au1000_gpio.c linux-2.6.12.6/drivers/char/au1000_gpio.c --- linux-2.6.12.6.orig/drivers/char/au1000_gpio.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/char/au1000_gpio.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,266 @@ +/* + * FILE NAME au1000_gpio.c + * + * BRIEF MODULE DESCRIPTION + * Driver for Alchemy Au1000 GPIO. + * + * Author: MontaVista Software, Inc. + * Steve Longerbeam + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VERSION "0.01" + +static const struct { + u32 active_hi; + u32 avail_mask; +} pinfunc_to_avail[15] = { + {1, 0x7<<16}, // 0 = SSI0 / GPIO[18:16] + {-1, 0}, // 1 = AC97 / SSI1 + {1, 1<<19}, // 2 = IRDA / GPIO19 + {1, 1<<20}, // 3 = UART0 / GPIO20 + {1, 0x1f<<24}, // 4 = NIC2 / GPIO[28:24] + {1, 0x7<<29}, // 5 = I2S / GPIO[31:29] + {0, 1<<8}, // 6 = I2SDI / GPIO8 + {0, 0x3f<<9}, // 7 = UART3 / GPIO[14:9] + {0, 1<<15}, // 8 = IRFIRSEL / GPIO15 + {0, 1<<2}, // 9 = EXTCLK0 or OSC / GPIO2 + {0, 1<<3}, // 10 = EXTCLK1 / GPIO3 + {0, 1<<6}, // 11 = SMROMCKE / GPIO6 + {1, 1<<21}, // 12 = UART1 / GPIO21 + {1, 1<<22}, // 13 = UART2 / GPIO22 + {1, 1<<23} // 14 = UART3 / GPIO23 +}; + + +u32 get_au1000_avail_gpio_mask(void) +{ + int i; + u32 pinfunc = inl(SYS_PINFUNC); + u32 avail_mask = 0; // start with no gpio available + + // first, check for GPIO's reprogrammed as peripheral pins + for (i=0; i<15; i++) { + if (pinfunc_to_avail[i].active_hi < 0) + continue; + if (!(pinfunc_to_avail[i].active_hi ^ + ((pinfunc & (1< +#include + +#include +#include +#include +#include +#include +#include /* request_region */ +#include /* mark_bh */ +#include /* get_user,copy_to_user */ +#include +#include + +#define TS_NAME "au1000-ts" +#define TS_MAJOR 11 + +#define PFX TS_NAME +#define AU1000_TS_DEBUG 1 + +#ifdef AU1000_TS_DEBUG +#define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg) +#else +#define dbg(format, arg...) do {} while (0) +#endif +#define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg) +#define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg) +#define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg) + + +// SSI Status register bit defines +#define SSISTAT_BF (1<<4) +#define SSISTAT_OF (1<<3) +#define SSISTAT_UF (1<<2) +#define SSISTAT_DONE (1<<1) +#define SSISTAT_BUSY (1<<0) + +// SSI Interrupt Pending and Enable register bit defines +#define SSIINT_OI (1<<3) +#define SSIINT_UI (1<<2) +#define SSIINT_DI (1<<1) + +// SSI Address/Data register bit defines +#define SSIADAT_D (1<<24) +#define SSIADAT_ADDR_BIT 16 +#define SSIADAT_ADDR_MASK (0xff<pressure_eqn == PRESSURE_EQN_2) { + Rt = (ts->x_plate_ohms * ts->x_raw * + (4096 - ts->z1_raw)) / ts->z1_raw; + Rt -= (ts->y_plate_ohms * ts->y_raw); + Rt = (Rt + 2048) >> 12; // round up to nearest ohm + } else { + Rt = (ts->x_plate_ohms * ts->x_raw * + (ts->z2_raw - ts->z1_raw)) / ts->z1_raw; + Rt = (Rt + 2048) >> 12; // round up to nearest ohm + } + + // hysteresis + if (!ts->pendown && Rt > ts->pendown_thresh_ohms) + ts->pendown = 1; + else if (ts->pendown && Rt < ts->penup_thresh_ohms) + ts->pendown = 0; + + if (ts->pendown) { + // Pen is down + // Calculate calibrated X,Y + Xcal = ((ts->cal.xscale * ts->x_raw) >> 8) + ts->cal.xtrans; + Ycal = ((ts->cal.yscale * ts->y_raw) >> 8) + ts->cal.ytrans; + + event.x = (unsigned short)Xcal; + event.y = (unsigned short)Ycal; + event.pressure = (unsigned short)Rt; + + // add this event to the event queue + spin_lock_irqsave(&ts->lock, flags); + ts->event_buf[ts->nextIn++] = event; + if (ts->nextIn == EVENT_BUFSIZE) + ts->nextIn = 0; + if (ts->event_count < EVENT_BUFSIZE) { + ts->event_count++; + } else { + // throw out the oldest event + if (++ts->nextOut == EVENT_BUFSIZE) + ts->nextOut = 0; + } + spin_unlock_irqrestore(&ts->lock, flags); + + // async notify + if (ts->fasync) + kill_fasync(&ts->fasync, SIGIO, POLL_IN); + // wake up any read call + if (waitqueue_active(&ts->wait)) + wake_up_interruptible(&ts->wait); + } +} + + +/* + * Raw X,Y,pressure acquisition timer function. This triggers + * the start of a new acquisition. Its duration between calls + * is the touch screen polling rate. + */ +static void +au1000_acq_timer(unsigned long data) +{ + au1000_ts_t* ts = (au1000_ts_t*)data; + unsigned long flags; + + spin_lock_irqsave(&ts->lock, flags); + + // start acquisition with X coordinate + ts->acq_state = ACQ_X; + // start me up + outl(SSIADAT_D | (MEASURE_12BIT_X << SSIADAT_ADDR_BIT), SSI0_ADATA); + + // schedule next acquire + ts->acq_timer.expires = jiffies + HZ / 100; + add_timer(&ts->acq_timer); + + spin_unlock_irqrestore(&ts->lock, flags); +} + +static void +ssi0_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + au1000_ts_t *ts = (au1000_ts_t*)dev_id; + u32 stat, int_stat, data; + + spin_lock(&ts->lock); + + stat = inl(SSI0_STATUS); + // clear sticky status bits + outl(stat & (SSISTAT_OF|SSISTAT_UF|SSISTAT_DONE), SSI0_STATUS); + + int_stat = inl(SSI0_INT); + // clear sticky intr status bits + outl(int_stat & (SSIINT_OI|SSIINT_UI|SSIINT_DI), SSI0_INT); + + if ((int_stat & (SSIINT_OI|SSIINT_UI|SSIINT_DI)) != SSIINT_DI) { + if (int_stat & SSIINT_OI) + err("overflow"); + if (int_stat & SSIINT_UI) + err("underflow"); + spin_unlock(&ts->lock); + return; + } + + data = inl(SSI0_ADATA) & SSIADAT_DATA_MASK; + + switch (ts->acq_state) { + case IDLE: + break; + case ACQ_X: + ts->x_raw = data; + ts->acq_state = ACQ_Y; + // trigger Y acq + outl(SSIADAT_D | (MEASURE_12BIT_Y << SSIADAT_ADDR_BIT), + SSI0_ADATA); + break; + case ACQ_Y: + ts->y_raw = data; + ts->acq_state = ACQ_Z1; + // trigger Z1 acq + outl(SSIADAT_D | (MEASURE_12BIT_Z1 << SSIADAT_ADDR_BIT), + SSI0_ADATA); + break; + case ACQ_Z1: + ts->z1_raw = data; + if (ts->pressure_eqn == PRESSURE_EQN_2) { + // don't acq Z2, using 2nd eqn for touch pressure + ts->acq_state = IDLE; + // got the raw stuff, now mark BH + queue_task(&ts->chug_tq, &tq_immediate); + mark_bh(IMMEDIATE_BH); + } else { + ts->acq_state = ACQ_Z2; + // trigger Z2 acq + outl(SSIADAT_D | (MEASURE_12BIT_Z2<z2_raw = data; + ts->acq_state = IDLE; + // got the raw stuff, now mark BH + queue_task(&ts->chug_tq, &tq_immediate); + mark_bh(IMMEDIATE_BH); + break; + } + + spin_unlock(&ts->lock); +} + + +/* +++++++++++++ File operations ++++++++++++++*/ + +static int +au1000_fasync(int fd, struct file *filp, int mode) +{ + au1000_ts_t* ts = (au1000_ts_t*)filp->private_data; + return fasync_helper(fd, filp, mode, &ts->fasync); +} + +static int +au1000_ioctl(struct inode * inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + au1000_ts_t* ts = (au1000_ts_t*)filp->private_data; + + switch(cmd) { + case TS_GET_RATE: /* TODO: what is this? */ + break; + case TS_SET_RATE: /* TODO: what is this? */ + break; + case TS_GET_CAL: + copy_to_user((char *)arg, (char *)&ts->cal, sizeof(TS_CAL)); + break; + case TS_SET_CAL: + copy_from_user((char *)&ts->cal, (char *)arg, sizeof(TS_CAL)); + break; + default: + err("unknown cmd %04x", cmd); + return -EINVAL; + } + + return 0; +} + +static unsigned int +au1000_poll(struct file * filp, poll_table * wait) +{ + au1000_ts_t* ts = (au1000_ts_t*)filp->private_data; + poll_wait(filp, &ts->wait, wait); + if (ts->event_count) + return POLLIN | POLLRDNORM; + return 0; +} + +static ssize_t +au1000_read(struct file * filp, char * buf, size_t count, loff_t * l) +{ + au1000_ts_t* ts = (au1000_ts_t*)filp->private_data; + unsigned long flags; + TS_EVENT event; + int i; + + if (ts->event_count == 0) { + if (filp->f_flags & O_NONBLOCK) + return -EAGAIN; + interruptible_sleep_on(&ts->wait); + if (signal_pending(current)) + return -ERESTARTSYS; + } + + for (i = count; + i >= sizeof(TS_EVENT); + i -= sizeof(TS_EVENT), buf += sizeof(TS_EVENT)) { + if (ts->event_count == 0) + break; + spin_lock_irqsave(&ts->lock, flags); + event = ts->event_buf[ts->nextOut++]; + if (ts->nextOut == EVENT_BUFSIZE) + ts->nextOut = 0; + if (ts->event_count) + ts->event_count--; + spin_unlock_irqrestore(&ts->lock, flags); + copy_to_user(buf, &event, sizeof(TS_EVENT)); + } + + return count - i; +} + + +static int +au1000_open(struct inode * inode, struct file * filp) +{ + au1000_ts_t* ts; + unsigned long flags; + + filp->private_data = ts = &au1000_ts; + + spin_lock_irqsave(&ts->lock, flags); + + // setup SSI0 config + outl(DEFAULT_SSI_CONFIG, SSI0_CONFIG); + + // clear out SSI0 status bits + outl(SSISTAT_OF|SSISTAT_UF|SSISTAT_DONE, SSI0_STATUS); + // clear out SSI0 interrupt pending bits + outl(SSIINT_OI|SSIINT_UI|SSIINT_DI, SSI0_INT); + + // enable SSI0 interrupts + outl(SSIINT_OI|SSIINT_UI|SSIINT_DI, SSI0_INT_ENABLE); + + /* + * init bh handler that chugs the raw data (calibrates and + * calculates touch pressure). + */ + ts->chug_tq.routine = chug_raw_data; + ts->chug_tq.data = ts; + ts->pendown = 0; // pen up + + // flush event queue + ts->nextIn = ts->nextOut = ts->event_count = 0; + + // Start acquisition timer function + init_timer(&ts->acq_timer); + ts->acq_timer.function = au1000_acq_timer; + ts->acq_timer.data = (unsigned long)ts; + ts->acq_timer.expires = jiffies + HZ / 100; + add_timer(&ts->acq_timer); + + spin_unlock_irqrestore(&ts->lock, flags); + + return 0; +} + +static int +au1000_release(struct inode * inode, struct file * filp) +{ + au1000_ts_t* ts = (au1000_ts_t*)filp->private_data; + unsigned long flags; + + au1000_fasync(-1, filp, 0); + del_timer_sync(&ts->acq_timer); + + spin_lock_irqsave(&ts->lock, flags); + // disable SSI0 interrupts + outl(0, SSI0_INT_ENABLE); + spin_unlock_irqrestore(&ts->lock, flags); + + return 0; +} + + +static struct file_operations ts_fops = { + .read = au1000_read, + .poll = au1000_poll, + .ioctl = au1000_ioctl, + .fasync = au1000_fasync, + .open = au1000_open, + .release = au1000_release, +}; + +/* +++++++++++++ End File operations ++++++++++++++*/ + + +int __init +au1000ts_init_module(void) +{ + au1000_ts_t* ts = &au1000_ts; + int ret; + + /* register our character device */ + if ((ret = register_chrdev(TS_MAJOR, TS_NAME, &ts_fops)) < 0) { + err("can't get major number"); + return ret; + } + info("registered"); + + memset(ts, 0, sizeof(au1000_ts_t)); + init_waitqueue_head(&ts->wait); + spin_lock_init(&ts->lock); + + if (!request_region(virt_to_phys((void*)SSI0_STATUS), 0x100, TS_NAME)) { + err("SSI0 ports in use"); + return -ENXIO; + } + + if ((ret = request_irq(AU1000_SSI0_INT, ssi0_interrupt, + SA_SHIRQ | SA_INTERRUPT, TS_NAME, ts))) { + err("could not get IRQ"); + return ret; + } + + // initial calibration values + ts->cal.xscale = -93; + ts->cal.xtrans = 346; + ts->cal.yscale = -64; + ts->cal.ytrans = 251; + + // init pen up/down hysteresis points + ts->pendown_thresh_ohms = DEFAULT_PENDOWN_THRESH_OHMS; + ts->penup_thresh_ohms = DEFAULT_PENUP_THRESH_OHMS; + ts->pressure_eqn = PRESSURE_EQN_2; + // init X and Y plate resistances + ts->x_plate_ohms = DEFAULT_X_PLATE_OHMS; + ts->y_plate_ohms = DEFAULT_Y_PLATE_OHMS; + + // set GPIO to SSI0 function + outl(inl(PIN_FUNCTION) & ~1, PIN_FUNCTION); + + // enable SSI0 clock and bring SSI0 out of reset + outl(0, SSI0_CONTROL); + udelay(1000); + outl(SSIEN_E, SSI0_CONTROL); + udelay(100); + + // FIXME: is this a working baudrate? + ts->clkdiv = 0; + ts->baudrate = calc_baudrate(ts->clkdiv); + outl(ts->clkdiv, SSI0_CLKDIV); + + info("baudrate = %d Hz", ts->baudrate); + + return 0; +} + +void +au1000ts_cleanup_module(void) +{ + // disable clocks and hold in reset + outl(SSIEN_CD, SSI0_CONTROL); + free_irq(AU1000_SSI0_INT, &au1000_ts); + release_region(virt_to_phys((void*)SSI0_STATUS), 0x100); + unregister_chrdev(TS_MAJOR, TS_NAME); +} + +/* Module information */ +MODULE_AUTHOR("Steve Longerbeam, stevel@mvista.com, www.mvista.com"); +MODULE_DESCRIPTION("Au1000/ADS7846 Touch Screen Driver"); + +module_init(au1000ts_init_module); +module_exit(au1000ts_cleanup_module); diff -Naur linux-2.6.12.6.orig/drivers/char/au1000_usbraw.c linux-2.6.12.6/drivers/char/au1000_usbraw.c --- linux-2.6.12.6.orig/drivers/char/au1000_usbraw.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/char/au1000_usbraw.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,573 @@ +/* + * BRIEF MODULE DESCRIPTION + * Au1x00 USB Device-Side Raw Block Driver (function layer) + * + * Copyright 2001-2002 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * stevel@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#undef DEBUG +#include + +#include +#include +#include +#include +#include + +#define USBRAW_MAJOR 190 // FIXME: need a legal major +#define USBRAW_NAME "usbraw" + +#define MAX_NUM_PORTS 2 + +#define IN_MAX_PACKET_SIZE 64 +#define OUT_MAX_PACKET_SIZE 64 + +// FIXME: when Au1x00 endpoints 3 and 5 are fixed, make NUM_PORTS=2 +#define NUM_PORTS 1 +#define NUM_EP 2*NUM_PORTS + +#define CONFIG_DESC_LEN \ + USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + NUM_EP*USB_DT_ENDPOINT_SIZE + +/* must be power of two */ +#define READ_BUF_SIZE (1<<12) + +struct usb_raw_port { + unsigned char number; + spinlock_t port_lock; + + struct usb_endpoint_descriptor* out_desc; + struct usb_endpoint_descriptor* in_desc; + + int out_ep_addr; /* endpoint address of OUT endpoint */ + int in_ep_addr; /* endpoint address of IN endpoint */ + + __u8 read_buf[READ_BUF_SIZE]; // FIXME: allocate with get_free_pages + int read_nextin, read_nextout; + int read_count; + + wait_queue_head_t wait; + struct fasync_struct *fasync; // asynch notification + + int active; /* someone has this device open */ + int open_count; /* number of times this port has been opened */ +}; + +static struct usb_serial { + struct usb_device_descriptor* dev_desc; + struct usb_config_descriptor* config_desc; + struct usb_interface_descriptor* if_desc; + struct usb_string_descriptor * str_desc[6]; + void* str_desc_buf; + + usbdev_state_t dev_state; + + struct usb_raw_port port[NUM_PORTS]; +} usbraw; + +static struct usb_device_descriptor dev_desc = { + bLength:USB_DT_DEVICE_SIZE, + bDescriptorType:USB_DT_DEVICE, + bcdUSB:USBDEV_REV, //usb rev + bDeviceClass:USB_CLASS_PER_INTERFACE, //class (none) + bDeviceSubClass:0x00, //subclass (none) + bDeviceProtocol:0x00, //protocol (none) + bMaxPacketSize0:USBDEV_EP0_MAX_PACKET_SIZE, //max packet size for ep0 + idVendor:0x6d04, //vendor id + idProduct:0x0bc0, //product id + bcdDevice:0x0001, //BCD rev 0.1 + iManufacturer:0x01, //manufactuer string index + iProduct:0x02, //product string index + iSerialNumber:0x03, //serial# string index + bNumConfigurations:0x01 //num configurations +}; + +static struct usb_endpoint_descriptor ep_desc[] = { + { + // Bulk IN for Port 0 + bLength:USB_DT_ENDPOINT_SIZE, + bDescriptorType:USB_DT_ENDPOINT, + bEndpointAddress:USB_DIR_IN, + bmAttributes:USB_ENDPOINT_XFER_BULK, + wMaxPacketSize:IN_MAX_PACKET_SIZE, + bInterval:0x00 // ignored for bulk + }, + { + // Bulk OUT for Port 0 + bLength:USB_DT_ENDPOINT_SIZE, + bDescriptorType:USB_DT_ENDPOINT, + bEndpointAddress:USB_DIR_OUT, + bmAttributes:USB_ENDPOINT_XFER_BULK, + wMaxPacketSize:OUT_MAX_PACKET_SIZE, + bInterval:0x00 // ignored for bulk + }, + { + // Bulk IN for Port 1 + bLength:USB_DT_ENDPOINT_SIZE, + bDescriptorType:USB_DT_ENDPOINT, + bEndpointAddress:USB_DIR_IN, + bmAttributes:USB_ENDPOINT_XFER_BULK, + wMaxPacketSize:IN_MAX_PACKET_SIZE, + bInterval:0x00 // ignored for bulk + }, + { + // Bulk OUT for Port 1 + bLength:USB_DT_ENDPOINT_SIZE, + bDescriptorType:USB_DT_ENDPOINT, + bEndpointAddress:USB_DIR_OUT, + bmAttributes:USB_ENDPOINT_XFER_BULK, + wMaxPacketSize:OUT_MAX_PACKET_SIZE, + bInterval:0x00 // ignored for bulk + } +}; + +static struct usb_interface_descriptor if_desc = { + bLength:USB_DT_INTERFACE_SIZE, + bDescriptorType:USB_DT_INTERFACE, + bInterfaceNumber:0x00, + bAlternateSetting:0x00, + bNumEndpoints:NUM_EP, + bInterfaceClass:0xff, + bInterfaceSubClass:0xab, + bInterfaceProtocol:0x00, + iInterface:0x05 +}; + +static struct usb_config_descriptor config_desc = { + bLength:USB_DT_CONFIG_SIZE, + bDescriptorType:USB_DT_CONFIG, + wTotalLength:CONFIG_DESC_LEN, + bNumInterfaces:0x01, + bConfigurationValue:0x01, + iConfiguration:0x04, // configuration string + bmAttributes:0xc0, // self-powered + MaxPower:20 // 40 mA +}; + +// String[0] is a list of Language IDs supported by this device +static struct usb_string_descriptor string_desc0 = { + bLength:4, + bDescriptorType:USB_DT_STRING, + wData:{0x0409} // English, US +}; + +// These strings will be converted to Unicode in string_desc[] +static char *strings[5] = { + "Alchemy Semiconductor", // iManufacturer + "USB Raw Block Device", // iProduct + "0.1", // iSerialNumber + "USB Raw Config", // iConfiguration + "USB Raw Interface" // iInterface +}; + + +static void +receive_callback(struct usb_raw_port *port) +{ + int i, pkt_size; + usbdev_pkt_t* pkt; + + if ((pkt_size = usbdev_receive_packet(port->out_ep_addr, + &pkt)) <= 0) { + dbg(__FUNCTION__ ": usbdev_receive_packet returns %d", + pkt_size); + return; + } + + dbg(__FUNCTION__ ": ep%d, size=%d", port->out_ep_addr, pkt_size); + + spin_lock(&port->port_lock); + for (i=0; i < pkt_size; i++) { + port->read_buf[port->read_nextin++] = pkt->payload[i]; + port->read_nextin &= (READ_BUF_SIZE - 1); + if (++port->read_count == READ_BUF_SIZE) + break; + } + spin_unlock(&port->port_lock); + + /* free the packet */ + kfree(pkt); + + // async notify + if (port->fasync) + kill_fasync(&port->fasync, SIGIO, POLL_IN); + // wake up any read call + if (waitqueue_active(&port->wait)) + wake_up_interruptible(&port->wait); +} + +static void +transmit_callback(struct usb_raw_port *port, usbdev_pkt_t* pkt) +{ + dbg(__FUNCTION__ ": ep%d", port->in_ep_addr); + /* just free the returned packet */ + kfree(pkt); +} + + +static void +usbraw_callback(usbdev_cb_type_t cb_type, unsigned long arg, void* data) +{ + usbdev_pkt_t* pkt; + int i; + + switch (cb_type) { + case CB_NEW_STATE: + usbraw.dev_state = (usbdev_state_t)arg; + break; + case CB_PKT_COMPLETE: + pkt = (usbdev_pkt_t*)arg; + for (i=0; iep_addr == port->in_ep_addr) { + transmit_callback(port, pkt); + break; + } else if (pkt->ep_addr == port->out_ep_addr) { + receive_callback(port); + break; + } + } + break; + } +} + +/***************************************************************************** + * Here begins the driver interface functions + *****************************************************************************/ + +static unsigned int usbraw_poll(struct file * filp, poll_table * wait) +{ + struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data; + unsigned long flags; + int count; + + poll_wait(filp, &port->wait, wait); + + spin_lock_irqsave(&port->port_lock, flags); + count = port->read_count; + spin_unlock_irqrestore(&port->port_lock, flags); + + if (count > 0) { + dbg(__FUNCTION__ ": count=%d", count); + return POLLIN | POLLRDNORM; + } + + return 0; +} + +static int usbraw_fasync(int fd, struct file *filp, int mode) +{ + struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data; + return fasync_helper(fd, filp, mode, &port->fasync); +} + +static int usbraw_open(struct inode * inode, struct file *filp) +{ + int portNumber; + struct usb_raw_port *port; + unsigned long flags; + + /* + * the device-layer must be in the configured state before the + * function layer can operate. + */ + if (usbraw.dev_state != CONFIGURED) + return -ENODEV; + + /* set up our port structure making the tty driver remember + our port object, and us it */ + portNumber = MINOR(inode->i_rdev); + port = &usbraw.port[portNumber]; + filp->private_data = port; + + dbg(__FUNCTION__ ": port %d", port->number); + + spin_lock_irqsave(&port->port_lock, flags); + + ++port->open_count; + + if (!port->active) { + port->active = 1; + } + + /* flush read buffer */ + port->read_nextin = port->read_nextout = port->read_count = 0; + + spin_unlock_irqrestore(&port->port_lock, flags); + + return 0; +} + +static int usbraw_release(struct inode * inode, struct file * filp) +{ + struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data; + unsigned long flags; + + dbg(__FUNCTION__ ": port %d", port->number); + + if (!port->active) { + err(__FUNCTION__ ": port not opened"); + return -ENODEV; + } + + usbraw_fasync(-1, filp, 0); + + spin_lock_irqsave(&port->port_lock, flags); + + --port->open_count; + + if (port->open_count <= 0) { + port->active = 0; + port->open_count = 0; + } + + spin_unlock_irqrestore(&port->port_lock, flags); + + return 0; +} + + +static ssize_t usbraw_read(struct file * filp, char * buf, + size_t count, loff_t * l) +{ + struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data; + unsigned long flags; + int i, cnt; + + /* + * the device-layer must be in the configured state before the + * function layer can operate. + */ + if (usbraw.dev_state != CONFIGURED) + return -ENODEV; + + do { + spin_lock_irqsave(&port->port_lock, flags); + cnt = port->read_count; + spin_unlock_irqrestore(&port->port_lock, flags); + if (cnt == 0) { + if (filp->f_flags & O_NONBLOCK) + return -EAGAIN; + interruptible_sleep_on(&port->wait); + if (signal_pending(current)) + return -ERESTARTSYS; + } + } while (cnt == 0); + + count = (count > cnt) ? cnt : count; + + for (i=0; iread_buf[port->read_nextout++], &buf[i]); + port->read_nextout &= (READ_BUF_SIZE - 1); + spin_lock_irqsave(&port->port_lock, flags); + port->read_count--; + spin_unlock_irqrestore(&port->port_lock, flags); + if (port->read_count == 0) + break; + } + + return i+1; +} + +static ssize_t usbraw_write(struct file * filp, const char * buf, + size_t count, loff_t *ppos) +{ + struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data; + usbdev_pkt_t* pkt; + int ret, max_pkt_sz; + + /* + * the device-layer must be in the configured state before the + * function layer can operate. + */ + if (usbraw.dev_state != CONFIGURED) + return -ENODEV; + + if (!port->active) { + err(__FUNCTION__ ": port not opened"); + return -EINVAL; + } + + if (count == 0) { + dbg(__FUNCTION__ ": write request of 0 bytes"); + return (0); + } + + max_pkt_sz = port->in_desc->wMaxPacketSize; + count = (count > max_pkt_sz) ? max_pkt_sz : count; + + if ((ret = usbdev_alloc_packet(port->in_ep_addr, count, &pkt)) < 0) + return ret; + + copy_from_user(pkt->payload, buf, count); + + return usbdev_send_packet(port->in_ep_addr, pkt); +} + +static int usbraw_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data; + + if (!port->active) { + err(__FUNCTION__ ": port not open"); + return -ENODEV; + } + // FIXME: need any IOCTLs? + + return -ENOIOCTLCMD; +} + + +static struct file_operations usbraw_fops = { + .owner = THIS_MODULE, + .write = usbraw_write, + .read = usbraw_read, + .poll = usbraw_poll, + .ioctl = usbraw_ioctl, + .fasync = usbraw_fasync, + .open = usbraw_open, + .release = usbraw_release, +}; + +void usbfn_raw_exit(void) +{ + /* kill the device layer */ + usbdev_exit(); + + unregister_chrdev(USBRAW_MAJOR, USBRAW_NAME); + + if (usbraw.str_desc_buf) + kfree(usbraw.str_desc_buf); +} + + +int usbfn_raw_init(void) +{ + int ret = 0, i, str_desc_len; + + /* register our character device */ + if ((ret = register_chrdev(USBRAW_MAJOR, USBRAW_NAME, + &usbraw_fops)) < 0) { + err("can't get major number"); + return ret; + } + info("registered"); + + /* + * initialize pointers to descriptors + */ + usbraw.dev_desc = &dev_desc; + usbraw.config_desc = &config_desc; + usbraw.if_desc = &if_desc; + + /* + * initialize the string descriptors + */ + + /* alloc buffer big enough for all string descriptors */ + str_desc_len = string_desc0.bLength; + for (i = 0; i < 5; i++) + str_desc_len += 2 + 2 * strlen(strings[i]); + usbraw.str_desc_buf = (void *) kmalloc(str_desc_len, GFP_KERNEL); + if (!usbraw.str_desc_buf) { + err(__FUNCTION__ ": failed to alloc string descriptors"); + ret = -ENOMEM; + goto out; + } + + usbraw.str_desc[0] = + (struct usb_string_descriptor *)usbraw.str_desc_buf; + memcpy(usbraw.str_desc[0], &string_desc0, string_desc0.bLength); + usbraw.str_desc[1] = (struct usb_string_descriptor *) + (usbraw.str_desc_buf + string_desc0.bLength); + for (i = 1; i < 6; i++) { + struct usb_string_descriptor *desc = usbraw.str_desc[i]; + char *str = strings[i - 1]; + int j, str_len = strlen(str); + + desc->bLength = 2 + 2 * str_len; + desc->bDescriptorType = USB_DT_STRING; + for (j = 0; j < str_len; j++) { + desc->wData[j] = (u16) str[j]; + } + if (i < 5) + usbraw.str_desc[i + 1] = + (struct usb_string_descriptor *) + ((u8 *) desc + desc->bLength); + } + + /* + * start the device layer. The device layer assigns us + * our endpoint addresses + */ + if ((ret = usbdev_init(&dev_desc, &config_desc, &if_desc, ep_desc, + usbraw.str_desc, usbraw_callback, NULL))) { + err(__FUNCTION__ ": device-layer init failed"); + goto out; + } + + /* initialize the devfs nodes for this device and let the user + know what ports we are bound to */ + for (i = 0; i < NUM_PORTS; ++i) { + struct usb_raw_port *port = &usbraw.port[i]; + + port->number = i; + port->in_desc = &ep_desc[NUM_PORTS*i]; + port->out_desc = &ep_desc[NUM_PORTS*i + 1]; + port->in_ep_addr = port->in_desc->bEndpointAddress & 0x0f; + port->out_ep_addr = port->out_desc->bEndpointAddress & 0x0f; + init_waitqueue_head(&port->wait); + spin_lock_init(&port->port_lock); + } + + out: + if (ret) + usbfn_raw_exit(); + return ret; +} + + +/* Module information */ +MODULE_AUTHOR("Steve Longerbeam, stevel@mvista.com, www.mvista.com"); +MODULE_DESCRIPTION("Au1x00 USB Device-Side Raw Block Driver"); +MODULE_LICENSE("GPL"); + +module_init(usbfn_raw_init); +module_exit(usbfn_raw_exit); diff -Naur linux-2.6.12.6.orig/drivers/char/au1000_usbtty.c linux-2.6.12.6/drivers/char/au1000_usbtty.c --- linux-2.6.12.6.orig/drivers/char/au1000_usbtty.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/char/au1000_usbtty.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,761 @@ +/* + * BRIEF MODULE DESCRIPTION + * Au1x00 USB Device-Side Serial TTY Driver (function layer) + * + * Copyright 2001-2002 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * stevel@mvista.com or source@mvista.com + * + * Derived from drivers/usb/serial/usbserial.c: + * + * Copyright (C) 1999 - 2001 Greg Kroah-Hartman (greg@kroah.com) + * Copyright (c) 2000 Peter Berger (pberger@brimson.com) + * Copyright (c) 2000 Al Borchers (borchers@steinerpoint.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#undef DEBUG +#include + +#include +#include +#include +#include +#include + + +/* local function prototypes */ +static int serial_open(struct tty_struct *tty, struct file *filp); +static void serial_close(struct tty_struct *tty, struct file *filp); +static int serial_write(struct tty_struct *tty, int from_user, + const unsigned char *buf, int count); +static int serial_write_room(struct tty_struct *tty); +static int serial_chars_in_buffer(struct tty_struct *tty); +static void serial_throttle(struct tty_struct *tty); +static void serial_unthrottle(struct tty_struct *tty); +static int serial_ioctl(struct tty_struct *tty, struct file *file, + unsigned int cmd, unsigned long arg); +static void serial_set_termios (struct tty_struct *tty, struct termios * old); + +#define SERIAL_TTY_MAJOR 189 // FIXME: need a legal major + +#define MAX_NUM_PORTS 2 + +#define IN_MAX_PACKET_SIZE 32 +#define OUT_MAX_PACKET_SIZE 32 + +// FIXME: when Au1x00 endpoints 3 and 5 are fixed, make NUM_PORTS=2 +#define NUM_PORTS 2 +#define NUM_EP 2*NUM_PORTS + +#define CONFIG_DESC_LEN \ + USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + NUM_EP*USB_DT_ENDPOINT_SIZE + +struct usb_serial_port { + struct tty_struct *tty; /* the coresponding tty for this port */ + unsigned char number; + spinlock_t port_lock; + + struct usb_endpoint_descriptor* out_desc; + struct usb_endpoint_descriptor* in_desc; + + int out_ep_addr; /* endpoint address of OUT endpoint */ + int in_ep_addr; /* endpoint address of IN endpoint */ + + /* task queue for line discipline waking up on send packet complete */ + struct tq_struct send_complete_tq; + /* task queue for line discipline wakeup on receive packet complete */ + struct tq_struct receive_complete_tq; + + int active; /* someone has this device open */ + int writing; /* a packet write is in progress */ + int open_count; /* number of times this port has been opened */ + +}; + +static struct usb_serial { + usbdev_state_t dev_state; // current state of device layer + struct usb_device_descriptor* dev_desc; + struct usb_config_descriptor* config_desc; + struct usb_interface_descriptor* if_desc; + struct usb_string_descriptor * str_desc[6]; + void* str_desc_buf; + + struct usb_serial_port port[NUM_PORTS]; +} usbtty; + +static int serial_refcount; +static struct tty_driver serial_tty_driver; +static struct tty_struct * serial_tty[NUM_PORTS]; +static struct termios * serial_termios[NUM_PORTS]; +static struct termios * serial_termios_locked[NUM_PORTS]; + +static struct usb_device_descriptor dev_desc = { + bLength:USB_DT_DEVICE_SIZE, + bDescriptorType:USB_DT_DEVICE, + bcdUSB:USBDEV_REV, //usb rev + bDeviceClass:USB_CLASS_PER_INTERFACE, //class (none) + bDeviceSubClass:0x00, //subclass (none) + bDeviceProtocol:0x00, //protocol (none) + bMaxPacketSize0:USBDEV_EP0_MAX_PACKET_SIZE, //max packet size for ep0 + idVendor:0x6d04, //vendor id + idProduct:0x0bc0, //product id + bcdDevice:0x0001, //BCD rev 0.1 + iManufacturer:0x01, //manufactuer string index + iProduct:0x02, //product string index + iSerialNumber:0x03, //serial# string index + bNumConfigurations:0x01 //num configurations +}; + +static struct usb_endpoint_descriptor ep_desc[] = { + { + // Bulk IN for Port 0 + bLength:USB_DT_ENDPOINT_SIZE, + bDescriptorType:USB_DT_ENDPOINT, + bEndpointAddress:USB_DIR_IN, + bmAttributes:USB_ENDPOINT_XFER_BULK, + wMaxPacketSize:IN_MAX_PACKET_SIZE, + bInterval:0x00 // ignored for bulk + }, + { + // Bulk OUT for Port 0 + bLength:USB_DT_ENDPOINT_SIZE, + bDescriptorType:USB_DT_ENDPOINT, + bEndpointAddress:USB_DIR_OUT, + bmAttributes:USB_ENDPOINT_XFER_BULK, + wMaxPacketSize:OUT_MAX_PACKET_SIZE, + bInterval:0x00 // ignored for bulk + }, + { + // Bulk IN for Port 1 + bLength:USB_DT_ENDPOINT_SIZE, + bDescriptorType:USB_DT_ENDPOINT, + bEndpointAddress:USB_DIR_IN, + bmAttributes:USB_ENDPOINT_XFER_BULK, + wMaxPacketSize:IN_MAX_PACKET_SIZE, + bInterval:0x00 // ignored for bulk + }, + { + // Bulk OUT for Port 1 + bLength:USB_DT_ENDPOINT_SIZE, + bDescriptorType:USB_DT_ENDPOINT, + bEndpointAddress:USB_DIR_OUT, + bmAttributes:USB_ENDPOINT_XFER_BULK, + wMaxPacketSize:OUT_MAX_PACKET_SIZE, + bInterval:0x00 // ignored for bulk + } +}; + +static struct usb_interface_descriptor if_desc = { + bLength:USB_DT_INTERFACE_SIZE, + bDescriptorType:USB_DT_INTERFACE, + bInterfaceNumber:0x00, + bAlternateSetting:0x00, + bNumEndpoints:NUM_EP, + bInterfaceClass:0xff, + bInterfaceSubClass:0xab, + bInterfaceProtocol:0x00, + iInterface:0x05 +}; + +static struct usb_config_descriptor config_desc = { + bLength:USB_DT_CONFIG_SIZE, + bDescriptorType:USB_DT_CONFIG, + wTotalLength:CONFIG_DESC_LEN, + bNumInterfaces:0x01, + bConfigurationValue:0x01, + iConfiguration:0x04, // configuration string + bmAttributes:0xc0, // self-powered + MaxPower:20 // 40 mA +}; + +// String[0] is a list of Language IDs supported by this device +static struct usb_string_descriptor string_desc0 = { + bLength:4, + bDescriptorType:USB_DT_STRING, + wData:{0x0409} // English, US +}; + +// These strings will be converted to Unicode in string_desc[] +static char *strings[5] = { + "Alchemy Semiconductor", // iManufacturer + "WutzAMattaU", // iProduct + "1.0.doh!", // iSerialNumber + "Au1000 TTY Config", // iConfiguration + "Au1000 TTY Interface" // iInterface +}; + +static inline int +port_paranoia_check(struct usb_serial_port *port, const char *function) +{ + if (!port) { + err("%s: port is NULL", function); + return -1; + } + if (!port->tty) { + err("%s: port->tty is NULL", function); + return -1; + } + + return 0; +} + + +static void +port_rx_callback(struct usb_serial_port *port) +{ + dbg(__FUNCTION__ ": ep%d", port->out_ep_addr); + // mark a bh to push this data up to the tty + queue_task(&port->receive_complete_tq, &tq_immediate); + mark_bh(IMMEDIATE_BH); +} + +static void +port_tx_callback(struct usb_serial_port *port, usbdev_pkt_t* pkt) +{ + dbg(__FUNCTION__ ": ep%d", port->in_ep_addr); + // mark a bh to wakeup any tty write system call on the port. + queue_task(&port->send_complete_tq, &tq_immediate); + mark_bh(IMMEDIATE_BH); + + /* free the returned packet */ + kfree(pkt); +} + +static void +usbtty_callback(usbdev_cb_type_t cb_type, unsigned long arg, void* data) +{ + usbdev_pkt_t* pkt; + int i; + + switch (cb_type) { + case CB_NEW_STATE: + dbg(__FUNCTION__ ": new dev_state=%d", (int)arg); + usbtty.dev_state = (usbdev_state_t)arg; + break; + case CB_PKT_COMPLETE: + pkt = (usbdev_pkt_t*)arg; + for (i=0; iep_addr == port->in_ep_addr) { + port_tx_callback(port, pkt); + break; + } else if (pkt->ep_addr == port->out_ep_addr) { + port_rx_callback(port); + break; + } + } + break; + } +} + + +/***************************************************************************** + * Here begins the tty driver interface functions + *****************************************************************************/ + +static int serial_open(struct tty_struct *tty, struct file *filp) +{ + int portNumber; + struct usb_serial_port *port; + unsigned long flags; + + /* initialize the pointer incase something fails */ + tty->driver_data = NULL; + + /* set up our port structure making the tty driver remember + our port object, and us it */ + portNumber = MINOR(tty->device); + port = &usbtty.port[portNumber]; + tty->driver_data = port; + port->tty = tty; + + if (usbtty.dev_state != CONFIGURED || + port_paranoia_check(port, __FUNCTION__)) { + /* + * the device-layer must be in the configured state before + * the function layer can operate. + */ + return -ENODEV; + } + + dbg(__FUNCTION__ ": port %d", port->number); + + spin_lock_irqsave(&port->port_lock, flags); + + ++port->open_count; + + if (!port->active) { + port->active = 1; + + /* + * force low_latency on so that our tty_push actually forces + * the data through, otherwise it is scheduled, and with high + * data rates (like with OHCI) data can get lost. + */ + port->tty->low_latency = 1; + + } + + spin_unlock_irqrestore(&port->port_lock, flags); + + return 0; +} + + +static void serial_close(struct tty_struct *tty, struct file *filp) +{ + struct usb_serial_port *port = + (struct usb_serial_port *) tty->driver_data; + unsigned long flags; + + dbg(__FUNCTION__ ": port %d", port->number); + + if (!port->active) { + err(__FUNCTION__ ": port not opened"); + return; + } + + spin_lock_irqsave(&port->port_lock, flags); + + --port->open_count; + + if (port->open_count <= 0) { + port->active = 0; + port->open_count = 0; + } + + spin_unlock_irqrestore(&port->port_lock, flags); + MOD_DEC_USE_COUNT; +} + + +static int serial_write(struct tty_struct *tty, int from_user, + const unsigned char *buf, int count) +{ + struct usb_serial_port *port = + (struct usb_serial_port *) tty->driver_data; + usbdev_pkt_t* pkt; + int max_pkt_sz, ret; + unsigned long flags; + + /* + * the device-layer must be in the configured state before the + * function layer can operate. + */ + if (usbtty.dev_state != CONFIGURED) + return -ENODEV; + + if (!port->active) { + err(__FUNCTION__ ": port not open"); + return -EINVAL; + } + + if (count == 0) { + dbg(__FUNCTION__ ": request of 0 bytes"); + return (0); + } + +#if 0 + if (port->writing) { + dbg(__FUNCTION__ ": already writing"); + return 0; + } +#endif + + max_pkt_sz = port->in_desc->wMaxPacketSize; + count = (count > max_pkt_sz) ? max_pkt_sz : count; + + if ((ret = usbdev_alloc_packet(port->in_ep_addr, count, &pkt))) + return ret; + + if (from_user) + copy_from_user(pkt->payload, buf, count); + else + memcpy(pkt->payload, buf, count); + + ret = usbdev_send_packet(port->in_ep_addr, pkt); + + spin_lock_irqsave(&port->port_lock, flags); + port->writing = 1; + spin_unlock_irqrestore(&port->port_lock, flags); + + return ret; +} + + +static int serial_write_room(struct tty_struct *tty) +{ + struct usb_serial_port *port = + (struct usb_serial_port *) tty->driver_data; + int room = 0; + + /* + * the device-layer must be in the configured state before the + * function layer can operate. + */ + if (usbtty.dev_state != CONFIGURED) + return -ENODEV; + + if (!port->active) { + err(__FUNCTION__ ": port not open"); + return -EINVAL; + } + + //room = port->writing ? 0 : port->in_desc->wMaxPacketSize; + room = port->in_desc->wMaxPacketSize; + + dbg(__FUNCTION__ ": %d", room); + return room; +} + + +static int serial_chars_in_buffer(struct tty_struct *tty) +{ + struct usb_serial_port *port = + (struct usb_serial_port *) tty->driver_data; + int chars = 0; + + /* + * the device-layer must be in the configured state before the + * function layer can operate. + */ + if (usbtty.dev_state != CONFIGURED) + return -ENODEV; + + if (!port->active) { + err(__FUNCTION__ ": port not open"); + return -EINVAL; + } + + //chars = port->writing ? usbdev_get_byte_count(port->in_ep_addr) : 0; + chars = usbdev_get_byte_count(port->in_ep_addr); + + dbg(__FUNCTION__ ": %d", chars); + return chars; +} + + +static void serial_throttle(struct tty_struct *tty) +{ + struct usb_serial_port *port = + (struct usb_serial_port *) tty->driver_data; + + if (!port->active || usbtty.dev_state != CONFIGURED) { + err(__FUNCTION__ ": port not open"); + return; + } + + // FIXME: anything to do? + dbg(__FUNCTION__); +} + + +static void serial_unthrottle(struct tty_struct *tty) +{ + struct usb_serial_port *port = + (struct usb_serial_port *) tty->driver_data; + + if (!port->active || usbtty.dev_state != CONFIGURED) { + err(__FUNCTION__ ": port not open"); + return; + } + + // FIXME: anything to do? + dbg(__FUNCTION__); +} + + +static int serial_ioctl(struct tty_struct *tty, struct file *file, + unsigned int cmd, unsigned long arg) +{ + struct usb_serial_port *port = + (struct usb_serial_port *) tty->driver_data; + + if (!port->active) { + err(__FUNCTION__ ": port not open"); + return -ENODEV; + } + // FIXME: need any IOCTLs? + dbg(__FUNCTION__); + + return -ENOIOCTLCMD; +} + + +static void serial_set_termios(struct tty_struct *tty, struct termios *old) +{ + struct usb_serial_port *port = + (struct usb_serial_port *) tty->driver_data; + + if (!port->active || usbtty.dev_state != CONFIGURED) { + err(__FUNCTION__ ": port not open"); + return; + } + + dbg(__FUNCTION__); + // FIXME: anything to do? +} + + +static void serial_break(struct tty_struct *tty, int break_state) +{ + struct usb_serial_port *port = + (struct usb_serial_port *) tty->driver_data; + + if (!port->active || usbtty.dev_state != CONFIGURED) { + err(__FUNCTION__ ": port not open"); + return; + } + + dbg(__FUNCTION__); + // FIXME: anything to do? +} + + +static void port_send_complete(void *private) +{ + struct usb_serial_port *port = (struct usb_serial_port *) private; + struct tty_struct *tty; + unsigned long flags; + + dbg(__FUNCTION__ ": port %d, ep%d", port->number, port->in_ep_addr); + + tty = port->tty; + if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && + tty->ldisc.write_wakeup) { + dbg(__FUNCTION__ ": write wakeup call."); + (tty->ldisc.write_wakeup) (tty); + } + + wake_up_interruptible(&tty->write_wait); + + spin_lock_irqsave(&port->port_lock, flags); + port->writing = usbdev_get_byte_count(port->in_ep_addr) <= 0 ? 0 : 1; + spin_unlock_irqrestore(&port->port_lock, flags); +} + + +static void port_receive_complete(void *private) +{ + struct usb_serial_port *port = (struct usb_serial_port *) private; + struct tty_struct *tty = port->tty; + usbdev_pkt_t* pkt = NULL; + int i, count; + + /* while there is a packet available */ + while ((count = usbdev_receive_packet(port->out_ep_addr, + &pkt)) != -ENODATA) { + if (count < 0) { + if (pkt) + kfree(pkt); + break; /* exit if error other than ENODATA */ + } + + dbg(__FUNCTION__ ": port %d, ep%d, size=%d", + port->number, port->out_ep_addr, count); + + for (i = 0; i < count; i++) { + /* if we insert more than TTY_FLIPBUF_SIZE characters, + we drop them. */ + if (tty->flip.count >= TTY_FLIPBUF_SIZE) { + tty_flip_buffer_push(tty); + } + /* this doesn't actually push the data through + unless tty->low_latency is set */ + tty_insert_flip_char(tty, pkt->payload[i], 0); + } + tty_flip_buffer_push(tty); + + kfree(pkt); /* make sure we free the packet */ + } + +} + + +static struct tty_driver serial_tty_driver = { + .magic= TTY_DRIVER_MAGIC, + .driver_name= "usbfn-tty", + .name= "usb/ttsdev/%d", + .major= SERIAL_TTY_MAJOR, + .minor_start= 0, + .num= NUM_PORTS, + .type= TTY_DRIVER_TYPE_SERIAL, + .subtype= SERIAL_TYPE_NORMAL, + .flags= TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS, + .refcount= &serial_refcount, + .table= serial_tty, + .termios= serial_termios, + .termios_locked= serial_termios_locked, + + .open= serial_open, + .close= serial_close, + .write= serial_write, + .write_room= serial_write_room, + .ioctl= serial_ioctl, + .set_termios= serial_set_termios, + .throttle= serial_throttle, + .unthrottle= serial_unthrottle, + .break_ctl= serial_break, + .chars_in_buffer= serial_chars_in_buffer, +}; + + +void usbfn_tty_exit(void) +{ + int i; + + /* kill the device layer */ + usbdev_exit(); + + for (i=0; i < NUM_PORTS; i++) { + tty_unregister_devfs(&serial_tty_driver, i); + info("usb serial converter now disconnected from ttyUSBdev%d", + i); + } + + tty_unregister_driver(&serial_tty_driver); + + if (usbtty.str_desc_buf) + kfree(usbtty.str_desc_buf); +} + + +int usbfn_tty_init(void) +{ + int ret = 0, i, str_desc_len; + + /* register the tty driver */ + serial_tty_driver.init_termios = tty_std_termios; + serial_tty_driver.init_termios.c_cflag = + B9600 | CS8 | CREAD | HUPCL | CLOCAL; + + if (tty_register_driver(&serial_tty_driver)) { + err(__FUNCTION__ ": failed to register tty driver"); + ret = -ENXIO; + goto out; + } + + /* + * initialize pointers to descriptors + */ + usbtty.dev_desc = &dev_desc; + usbtty.config_desc = &config_desc; + usbtty.if_desc = &if_desc; + + /* + * initialize the string descriptors + */ + + /* alloc buffer big enough for all string descriptors */ + str_desc_len = string_desc0.bLength; + for (i = 0; i < 5; i++) + str_desc_len += 2 + 2 * strlen(strings[i]); + usbtty.str_desc_buf = (void *) kmalloc(str_desc_len, GFP_KERNEL); + if (!usbtty.str_desc_buf) { + err(__FUNCTION__ ": failed to alloc string descriptors"); + ret = -ENOMEM; + goto out; + } + + usbtty.str_desc[0] = + (struct usb_string_descriptor *)usbtty.str_desc_buf; + memcpy(usbtty.str_desc[0], &string_desc0, string_desc0.bLength); + usbtty.str_desc[1] = (struct usb_string_descriptor *) + (usbtty.str_desc_buf + string_desc0.bLength); + for (i = 1; i < 6; i++) { + struct usb_string_descriptor *desc = usbtty.str_desc[i]; + char *str = strings[i - 1]; + int j, str_len = strlen(str); + + desc->bLength = 2 + 2 * str_len; + desc->bDescriptorType = USB_DT_STRING; + for (j = 0; j < str_len; j++) { + desc->wData[j] = (u16) str[j]; + } + if (i < 5) + usbtty.str_desc[i + 1] = + (struct usb_string_descriptor *) + ((u8 *) desc + desc->bLength); + } + + /* + * start the device layer. The device layer assigns us + * our endpoint addresses + */ + if ((ret = usbdev_init(&dev_desc, &config_desc, &if_desc, ep_desc, + usbtty.str_desc, usbtty_callback, NULL))) { + err(__FUNCTION__ ": device-layer init failed"); + goto out; + } + + /* initialize the devfs nodes for this device and let the user + know what ports we are bound to */ + for (i = 0; i < NUM_PORTS; ++i) { + struct usb_serial_port *port; + tty_register_devfs(&serial_tty_driver, 0, i); + info("usbdev serial attached to ttyUSBdev%d " + "(or devfs usb/ttsdev/%d)", i, i); + port = &usbtty.port[i]; + port->number = i; + port->in_desc = &ep_desc[NUM_PORTS*i]; + port->out_desc = &ep_desc[NUM_PORTS*i + 1]; + port->in_ep_addr = port->in_desc->bEndpointAddress & 0x0f; + port->out_ep_addr = port->out_desc->bEndpointAddress & 0x0f; + port->send_complete_tq.routine = port_send_complete; + port->send_complete_tq.data = port; + port->receive_complete_tq.routine = port_receive_complete; + port->receive_complete_tq.data = port; + spin_lock_init(&port->port_lock); + } + + out: + if (ret) + usbfn_tty_exit(); + return ret; +} + + +/* Module information */ +MODULE_AUTHOR("Steve Longerbeam, stevel@mvista.com, www.mvista.com"); +MODULE_DESCRIPTION("Au1x00 USB Device-Side Serial TTY Driver"); +MODULE_LICENSE("GPL"); + +module_init(usbfn_tty_init); +module_exit(usbfn_tty_exit); diff -Naur linux-2.6.12.6.orig/drivers/char/decserial.c linux-2.6.12.6/drivers/char/decserial.c --- linux-2.6.12.6.orig/drivers/char/decserial.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/char/decserial.c 2005-10-02 23:47:38.000000000 +0000 @@ -14,87 +14,85 @@ * device. Added support for PROM console in drivers/char/tty_io.c * instead. Although it may work to enable more than one * console device I strongly recommend to use only one. + * + * Copyright (C) 2004 Maciej W. Rozycki */ #include +#include #include -#include - -#ifdef CONFIG_ZS -extern int zs_init(void); -#endif -#ifdef CONFIG_DZ -extern int dz_init(void); -#endif +#include +#include -#ifdef CONFIG_SERIAL_CONSOLE +extern int register_zs_hook(unsigned int channel, + struct dec_serial_hook *hook); +extern int unregister_zs_hook(unsigned int channel); +int register_dec_serial_hook(unsigned int channel, + struct dec_serial_hook *hook) +{ #ifdef CONFIG_ZS -extern void zs_serial_console_init(void); -#endif - -#ifdef CONFIG_DZ -extern void dz_serial_console_init(void); + if (IOASIC) + return register_zs_hook(channel, hook); #endif + return 0; +} +int unregister_dec_serial_hook(unsigned int channel) +{ +#ifdef CONFIG_ZS + if (IOASIC) + return unregister_zs_hook(channel); #endif + return 0; +} -/* rs_init - starts up the serial interface - - handle normal case of starting up the serial interface */ -#ifdef CONFIG_SERIAL +extern int zs_init(void); +extern int dz_init(void); +/* + * rs_init - starts up the serial interface - + * handle normal case of starting up the serial interface + */ int __init rs_init(void) { - -#if defined(CONFIG_ZS) && defined(CONFIG_DZ) - if (IOASIC) - return zs_init(); - else - return dz_init(); -#else - #ifdef CONFIG_ZS - return zs_init(); + if (IOASIC) + return zs_init(); #endif - #ifdef CONFIG_DZ - return dz_init(); -#endif - + if (!IOASIC) + return dz_init(); #endif + return -ENXIO; } __initcall(rs_init); -#endif -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_SERIAL_DEC_CONSOLE + +extern void zs_serial_console_init(void); +extern void dz_serial_console_init(void); -/* serial_console_init handles the special case of starting - * up the console on the serial port +/* + * dec_serial_console_init handles the special case of starting + * up the console on the serial port */ -static int __init decserial_console_init(void) +static int __init dec_serial_console_init(void) { -#if defined(CONFIG_ZS) && defined(CONFIG_DZ) - if (IOASIC) - zs_serial_console_init(); - else - dz_serial_console_init(); -#else - #ifdef CONFIG_ZS - zs_serial_console_init(); + if (IOASIC) + zs_serial_console_init(); #endif - #ifdef CONFIG_DZ - dz_serial_console_init(); -#endif - + if (!IOASIC) + dz_serial_console_init(); #endif return 0; } -console_initcall(decserial_console_init); +console_initcall(dec_serial_console_init); #endif diff -Naur linux-2.6.12.6.orig/drivers/char/generic_serial.c linux-2.6.12.6/drivers/char/generic_serial.c --- linux-2.6.12.6.orig/drivers/char/generic_serial.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/char/generic_serial.c 2005-10-02 23:47:38.000000000 +0000 @@ -21,6 +21,7 @@ #include #include +#include #include #include #include diff -Naur linux-2.6.12.6.orig/drivers/char/ibm_workpad_keymap.map linux-2.6.12.6/drivers/char/ibm_workpad_keymap.map --- linux-2.6.12.6.orig/drivers/char/ibm_workpad_keymap.map 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/char/ibm_workpad_keymap.map 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,343 @@ +# Keymap for IBM Workpad z50 +# US Mapping +# +# by Michael Klar +# +# This is a great big mess on account of how the Caps Lock key is handled as +# LeftShift-RightShift. Right shift key had to be broken out, so don't use +# use this map file as a basis for other keyboards that don't do the same +# thing with Caps Lock. +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. + +keymaps 0-2,4-5,8,12,32-33,36-37 +strings as usual + +keycode 0 = F1 F11 Console_13 + shiftr keycode 0 = F11 + shift shiftr keycode 0 = F11 + control keycode 0 = F1 + alt keycode 0 = Console_1 + control alt keycode 0 = Console_1 +keycode 1 = F3 F13 Console_15 + shiftr keycode 1 = F13 + shift shiftr keycode 1 = F13 + control keycode 1 = F3 + alt keycode 1 = Console_3 + control alt keycode 1 = Console_3 +keycode 2 = F5 F15 Console_17 + shiftr keycode 2 = F15 + shift shiftr keycode 2 = F15 + control keycode 2 = F5 + alt keycode 2 = Console_5 + control alt keycode 2 = Console_5 +keycode 3 = F7 F17 Console_19 + shiftr keycode 3 = F17 + shift shiftr keycode 3 = F17 + control keycode 3 = F7 + alt keycode 3 = Console_7 + control alt keycode 3 = Console_7 +keycode 4 = F9 F19 Console_21 + shiftr keycode 4 = F19 + shift shiftr keycode 4 = F19 + control keycode 4 = F9 + alt keycode 4 = Console_9 + control alt keycode 4 = Console_9 +#keycode 5 is contrast down +#keycode 6 is contrast up +keycode 7 = F11 F11 Console_23 + shiftr keycode 7 = F11 + shift shiftr keycode 7 = F11 + control keycode 7 = F11 + alt keycode 7 = Console_11 + control alt keycode 7 = Console_11 +keycode 8 = F2 F12 Console_14 + shiftr keycode 8 = F12 + shift shiftr keycode 8 = F12 + control keycode 8 = F2 + alt keycode 8 = Console_2 + control alt keycode 8 = Console_2 +keycode 9 = F4 F14 Console_16 + shiftr keycode 9 = F14 + shift shiftr keycode 9 = F14 + control keycode 9 = F4 + alt keycode 9 = Console_4 + control alt keycode 9 = Console_4 +keycode 10 = F6 F16 Console_18 + shiftr keycode 10 = F16 + shift shiftr keycode 10 = F16 + control keycode 10 = F6 + alt keycode 10 = Console_6 + control alt keycode 10 = Console_6 +keycode 11 = F8 F18 Console_20 + shiftr keycode 11 = F18 + shift shiftr keycode 11 = F18 + control keycode 11 = F8 + alt keycode 11 = Console_8 + control alt keycode 11 = Console_8 +keycode 12 = F10 F20 Console_22 + shiftr keycode 12 = F20 + shift shiftr keycode 12 = F20 + control keycode 12 = F10 + alt keycode 12 = Console_10 + control alt keycode 12 = Console_10 +#keycode 13 is brightness down +#keycode 14 is brightness up +keycode 15 = F12 F12 Console_24 + shiftr keycode 15 = F12 + shift shiftr keycode 15 = F12 + control keycode 15 = F12 + alt keycode 15 = Console_12 + control alt keycode 15 = Console_12 +keycode 16 = apostrophe quotedbl + shiftr keycode 16 = quotedbl + shift shiftr keycode 16 = quotedbl + control keycode 16 = Control_g + alt keycode 16 = Meta_apostrophe +keycode 17 = bracketleft braceleft + shiftr keycode 17 = braceleft + shift shiftr keycode 17 = braceleft + control keycode 17 = Escape + alt keycode 17 = Meta_bracketleft +keycode 18 = minus underscore backslash + shiftr keycode 18 = underscore + shift shiftr keycode 18 = underscore + control keycode 18 = Control_underscore + shift control keycode 18 = Control_underscore + shiftr control keycode 18 = Control_underscore + shift shiftr control keycode 18 = Control_underscore + alt keycode 18 = Meta_minus +keycode 19 = zero parenright braceright + shiftr keycode 19 = parenright + shift shiftr keycode 19 = parenright + alt keycode 19 = Meta_zero +keycode 20 = p + shiftr keycode 20 = +P + shift shiftr keycode 20 = +p +keycode 21 = semicolon colon + shiftr keycode 21 = colon + shift shiftr keycode 21 = colon + alt keycode 21 = Meta_semicolon +keycode 22 = Up Scroll_Backward + shiftr keycode 22 = Scroll_Backward + shift shiftr keycode 22 = Scroll_Backward + alt keycode 22 = Prior +keycode 23 = slash question + shiftr keycode 23 = question + shift shiftr keycode 23 = question + control keycode 23 = Delete + alt keycode 23 = Meta_slash + +keycode 27 = nine parenleft bracketright + shiftr keycode 27 = parenleft + shift shiftr keycode 27 = parenleft + alt keycode 27 = Meta_nine +keycode 28 = o + shiftr keycode 28 = +O + shift shiftr keycode 28 = +o +keycode 29 = l + shiftr keycode 29 = +L + shift shiftr keycode 29 = +l +keycode 30 = period greater + shiftr keycode 30 = greater + shift shiftr keycode 30 = greater + control keycode 30 = Compose + alt keycode 30 = Meta_period + +keycode 32 = Left Decr_Console + shiftr keycode 32 = Decr_Console + shift shiftr keycode 32 = Decr_Console + alt keycode 32 = Home +keycode 33 = bracketright braceright asciitilde + shiftr keycode 33 = braceright + shift shiftr keycode 33 = braceright + control keycode 33 = Control_bracketright + alt keycode 33 = Meta_bracketright +keycode 34 = equal plus + shiftr keycode 34 = plus + shift shiftr keycode 34 = plus + alt keycode 34 = Meta_equal +keycode 35 = eight asterisk bracketleft + shiftr keycode 35 = asterisk + shift shiftr keycode 35 = asterisk + control keycode 35 = Delete + alt keycode 35 = Meta_eight +keycode 36 = i + shiftr keycode 36 = +I + shift shiftr keycode 36 = +i +keycode 37 = k + shiftr keycode 37 = +K + shift shiftr keycode 37 = +k +keycode 38 = comma less + shiftr keycode 38 = less + shift shiftr keycode 38 = less + alt keycode 38 = Meta_comma + +keycode 40 = h + shiftr keycode 40 = +H + shift shiftr keycode 40 = +h +keycode 41 = y + shiftr keycode 41 = +Y + shift shiftr keycode 41 = +y +keycode 42 = six asciicircum + shiftr keycode 42 = asciicircum + shift shiftr keycode 42 = asciicircum + control keycode 42 = Control_asciicircum + alt keycode 42 = Meta_six +keycode 43 = seven ampersand braceleft + shiftr keycode 43 = ampersand + shift shiftr keycode 43 = ampersand + control keycode 43 = Control_underscore + alt keycode 43 = Meta_seven +keycode 44 = u + shiftr keycode 44 = +U + shift shiftr keycode 44 = +u +keycode 45 = j + shiftr keycode 45 = +J + shift shiftr keycode 45 = +j +keycode 46 = m + shiftr keycode 46 = +M + shift shiftr keycode 46 = +m +keycode 47 = n + shiftr keycode 47 = +N + shift shiftr keycode 47 = +n + +# This is the "Backspace" key: +keycode 49 = Delete Delete + shiftr keycode 49 = Delete + shift shiftr keycode 49 = Delete + control keycode 49 = BackSpace + alt keycode 49 = Meta_Delete +keycode 50 = Num_Lock + shift keycode 50 = Bare_Num_Lock + shiftr keycode 50 = Bare_Num_Lock + shift shiftr keycode 50 = Bare_Num_Lock +# This is the "Delete" key: +keycode 51 = Remove + control alt keycode 51 = Boot + +keycode 53 = backslash bar + shiftr keycode 53 = bar + shift shiftr keycode 53 = bar + control keycode 53 = Control_backslash + alt keycode 53 = Meta_backslash +keycode 54 = Return + alt keycode 54 = Meta_Control_m +keycode 55 = space space + shiftr keycode 55 = space + shift shiftr keycode 55 = space + control keycode 55 = nul + alt keycode 55 = Meta_space +keycode 56 = g + shiftr keycode 56 = +G + shift shiftr keycode 56 = +g +keycode 57 = t + shiftr keycode 57 = +T + shift shiftr keycode 57 = +t +keycode 58 = five percent + shiftr keycode 58 = percent + shift shiftr keycode 58 = percent + control keycode 58 = Control_bracketright + alt keycode 58 = Meta_five +keycode 59 = four dollar dollar + shiftr keycode 59 = dollar + shift shiftr keycode 59 = dollar + control keycode 59 = Control_backslash + alt keycode 59 = Meta_four +keycode 60 = r + shiftr keycode 60 = +R + shift shiftr keycode 60 = +r +keycode 61 = f + shiftr keycode 61 = +F + shift shiftr keycode 61 = +f + altgr keycode 61 = Hex_F +keycode 62 = v + shiftr keycode 62 = +V + shift shiftr keycode 62 = +v +keycode 63 = b + shiftr keycode 63 = +B + shift shiftr keycode 63 = +b + altgr keycode 63 = Hex_B + +keycode 67 = three numbersign + shiftr keycode 67 = numbersign + shift shiftr keycode 67 = numbersign + control keycode 67 = Escape + alt keycode 67 = Meta_three +keycode 68 = e + shiftr keycode 68 = +E + shift shiftr keycode 68 = +e + altgr keycode 68 = Hex_E +keycode 69 = d + shiftr keycode 69 = +D + shift shiftr keycode 69 = +d + altgr keycode 69 = Hex_D +keycode 70 = c + shiftr keycode 70 = +C + shift shiftr keycode 70 = +c + altgr keycode 70 = Hex_C +keycode 71 = Right Incr_Console + shiftr keycode 71 = Incr_Console + shift shiftr keycode 71 = Incr_Console + alt keycode 71 = End + +keycode 75 = two at at + shiftr keycode 75 = at + shift shiftr keycode 75 = at + control keycode 75 = nul + shift control keycode 75 = nul + shiftr control keycode 75 = nul + shift shiftr control keycode 75 = nul + alt keycode 75 = Meta_two +keycode 76 = w + shiftr keycode 76 = +W + shift shiftr keycode 76 = +w +keycode 77 = s + shiftr keycode 77 = +S + shift shiftr keycode 77 = +s +keycode 78 = x + shiftr keycode 78 = +X + shift shiftr keycode 78 = +x +keycode 79 = Down Scroll_Forward + shiftr keycode 79 = Scroll_Forward + shift shiftr keycode 79 = Scroll_Forward + alt keycode 79 = Next +keycode 80 = Escape Escape + shiftr keycode 80 = Escape + shift shiftr keycode 80 = Escape + alt keycode 80 = Meta_Escape +keycode 81 = Tab Tab + shiftr keycode 81 = Tab + shift shiftr keycode 81 = Tab + alt keycode 81 = Meta_Tab +keycode 82 = grave asciitilde + shiftr keycode 82 = asciitilde + shift shiftr keycode 82 = asciitilde + control keycode 82 = nul + alt keycode 82 = Meta_grave +keycode 83 = one exclam + shiftr keycode 83 = exclam + shift shiftr keycode 83 = exclam + alt keycode 83 = Meta_one +keycode 84 = q + shiftr keycode 84 = +Q + shift shiftr keycode 84 = +q +keycode 85 = a + shiftr keycode 85 = +A + shift shiftr keycode 85 = +a + altgr keycode 85 = Hex_A +keycode 86 = z + shiftr keycode 86 = +Z + shift shiftr keycode 86 = +z + +# This is the windows key: +keycode 88 = Decr_Console +keycode 89 = Shift +keycode 90 = Control +keycode 91 = Control +keycode 92 = Alt +keycode 93 = AltGr +keycode 94 = ShiftR + shift keycode 94 = Caps_Lock diff -Naur linux-2.6.12.6.orig/drivers/char/lcd.c linux-2.6.12.6/drivers/char/lcd.c --- linux-2.6.12.6.orig/drivers/char/lcd.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/char/lcd.c 2005-10-02 23:47:38.000000000 +0000 @@ -575,8 +575,8 @@ static int lcd_waiters = 0; -static long lcd_read(struct inode *inode, struct file *file, char *buf, - unsigned long count) +static ssize_t lcd_read(struct file *file, char *buf, + size_t count, loff_t *ofs) { long buttons_now; diff -Naur linux-2.6.12.6.orig/drivers/char/lcd.h linux-2.6.12.6/drivers/char/lcd.h --- linux-2.6.12.6.orig/drivers/char/lcd.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/char/lcd.h 2005-10-02 23:47:38.000000000 +0000 @@ -22,7 +22,7 @@ #define MAX_IDLE_TIME 120 struct lcd_display { - unsigned long buttons; + unsigned buttons; int size1; int size2; unsigned char line1[LCD_CHARS_PER_LINE]; diff -Naur linux-2.6.12.6.orig/drivers/char/qtronix.c linux-2.6.12.6/drivers/char/qtronix.c --- linux-2.6.12.6.orig/drivers/char/qtronix.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/char/qtronix.c 2005-10-02 23:47:38.000000000 +0000 @@ -535,8 +535,7 @@ i--; } if (count-i) { - struct inode *inode = file->f_dentry->d_inode; - inode->i_atime = current_fs_time(inode->i_sb); + file->f_dentry->d_inode->i_atime = get_seconds(); return count-i; } if (signal_pending(current)) @@ -591,6 +590,11 @@ return retval; queue = (struct aux_queue *) kmalloc(sizeof(*queue), GFP_KERNEL); + if (!queue) { + misc_deregister(&psaux_mouse); + return -ENOMEM; + } + memset(queue, 0, sizeof(*queue)); queue->head = queue->tail = 0; init_waitqueue_head(&queue->proc_list); diff -Naur linux-2.6.12.6.orig/drivers/char/rtc.c linux-2.6.12.6/drivers/char/rtc.c --- linux-2.6.12.6.orig/drivers/char/rtc.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/char/rtc.c 2005-10-02 23:47:38.000000000 +0000 @@ -35,23 +35,21 @@ * 1.09a Pete Zaitcev: Sun SPARC * 1.09b Jeff Garzik: Modularize, init cleanup * 1.09c Jeff Garzik: SMP cleanup - * 1.10 Paul Barton-Davis: add support for async I/O + * 1.10 Paul Barton-Davis: add support for async I/O * 1.10a Andrea Arcangeli: Alpha updates * 1.10b Andrew Morton: SMP lock fix * 1.10c Cesar Barros: SMP locking fixes and cleanup * 1.10d Paul Gortmaker: delete paranoia check in rtc_exit * 1.10e Maciej W. Rozycki: Handle DECstation's year weirdness. - * 1.11 Takashi Iwai: Kernel access functions + * 1.11 Takashi Iwai: Kernel access functions * rtc_register/rtc_unregister/rtc_control * 1.11a Daniele Bellucci: Audit create_proc_read_entry in rtc_init - * 1.12 Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer + * 1.12 Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer * CONFIG_HPET_EMULATE_RTC - * + * 1.12a Maciej W. Rozycki: Handle memory-mapped chips properly. */ -#define RTC_VERSION "1.12" - -#define RTC_IO_EXTENT 0x8 +#define RTC_VERSION "1.12a" /* * Note that *all* calls to CMOS_READ and CMOS_WRITE are done with @@ -323,7 +321,15 @@ if (rtc_has_irq == 0) return -EIO; - if (count < sizeof(unsigned)) + /* + * Historically this function used to assume that sizeof(unsigned long) + * is the same in userspace and kernelspace. This lead to problems + * for configurations with multiple ABIs such a the MIPS o32 and 64 + * ABIs supported on the same kernel. So now we support read of both + * 4 and 8 bytes and assume that's the sizeof(unsigned long) in the + * userspace ABI. + */ + if (count != sizeof(unsigned int) && count != sizeof(unsigned long)) return -EINVAL; add_wait_queue(&rtc_wait, &wait); @@ -354,10 +360,12 @@ schedule(); } while (1); - if (count < sizeof(unsigned long)) - retval = put_user(data, (unsigned int __user *)buf) ?: sizeof(int); + if (count == sizeof(unsigned int)) + retval = put_user(data, (unsigned int __user *)buf) ?: sizeof(int); else retval = put_user(data, (unsigned long __user *)buf) ?: sizeof(long); + if (!retval) + retval = count; out: current->state = TASK_RUNNING; remove_wait_queue(&rtc_wait, &wait); @@ -905,6 +913,9 @@ struct sparc_isa_device *isa_dev; #endif #endif +#ifndef __sparc__ + void *r; +#endif #ifdef __sparc__ for_each_ebus(ebus) { @@ -951,8 +962,13 @@ } no_irq: #else - if (!request_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc")) { - printk(KERN_ERR "rtc: I/O port %d is not free.\n", RTC_PORT (0)); + if (RTC_IOMAPPED) + r = request_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc"); + else + r = request_mem_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc"); + if (!r) { + printk(KERN_ERR "rtc: I/O resource %lx is not free.\n", + (long)(RTC_PORT(0))); return -EIO; } @@ -966,7 +982,10 @@ if(request_irq(RTC_IRQ, rtc_int_handler_ptr, SA_INTERRUPT, "rtc", NULL)) { /* Yeah right, seeing as irq 8 doesn't even hit the bus. */ printk(KERN_ERR "rtc: IRQ %d is not free.\n", RTC_IRQ); - release_region(RTC_PORT(0), RTC_IO_EXTENT); + if (RTC_IOMAPPED) + release_region(RTC_PORT(0), RTC_IO_EXTENT); + else + release_mem_region(RTC_PORT(0), RTC_IO_EXTENT); return -EIO; } hpet_rtc_timer_init(); @@ -1070,7 +1089,10 @@ if (rtc_has_irq) free_irq (rtc_irq, &rtc_port); #else - release_region (RTC_PORT (0), RTC_IO_EXTENT); + if (RTC_IOMAPPED) + release_region(RTC_PORT(0), RTC_IO_EXTENT); + else + release_mem_region(RTC_PORT(0), RTC_IO_EXTENT); #ifdef RTC_IRQ if (rtc_has_irq) free_irq (RTC_IRQ, NULL); diff -Naur linux-2.6.12.6.orig/drivers/char/sb1250_duart.c linux-2.6.12.6/drivers/char/sb1250_duart.c --- linux-2.6.12.6.orig/drivers/char/sb1250_duart.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/char/sb1250_duart.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,899 @@ +/* + * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * Driver support for the on-chip sb1250 dual-channel serial port, + * running in asynchronous mode. Also, support for doing a serial console + * on one of those ports + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Toggle spewing of debugging output */ +#undef DUART_SPEW + +#define DEFAULT_CFLAGS (CS8 | B115200) + +#define TX_INTEN 1 +#define DUART_INITIALIZED 2 + +#ifndef MIN +#define MIN(a,b) ((a) < (b) ? (a) : (b)) +#endif + +#define DUART_MAX_LINE 2 +char sb1250_duart_present[DUART_MAX_LINE] = {1,1}; +EXPORT_SYMBOL(sb1250_duart_present); + +/* + * Still not sure what the termios structures set up here are for, + * but we have to supply pointers to them to register the tty driver + */ +static struct tty_driver *sb1250_duart_driver; //, sb1250_duart_callout_driver; + +/* + * This lock protects both the open flags for all the uart states as + * well as the reference count for the module + */ +static DEFINE_SPINLOCK(open_lock); + +typedef struct { + unsigned char outp_buf[SERIAL_XMIT_SIZE]; + unsigned int outp_head; + unsigned int outp_tail; + unsigned int outp_count; + spinlock_t outp_lock; + unsigned int open; + unsigned int line; + unsigned int last_cflags; + unsigned long flags; + struct tty_struct *tty; + /* CSR addresses */ + u32 *status; + u32 *imr; + u32 *tx_hold; + u32 *rx_hold; + u32 *mode_1; + u32 *mode_2; + u32 *clk_sel; + u32 *cmd; +} uart_state_t; + +static uart_state_t uart_states[DUART_MAX_LINE]; + +/* + * Inline functions local to this module + */ + +/* + * In bug 1956, we get glitches that can mess up uart registers. This + * "write-mode-1 after any register access" is the accepted + * workaround. + */ +#if SIBYTE_1956_WAR +static unsigned int last_mode1[DUART_MAX_LINE]; +#endif + +static inline u32 READ_SERCSR(u32 *addr, int line) +{ + u32 val = csr_in32(addr); +#if SIBYTE_1956_WAR + csr_out32(last_mode1[line], uart_states[line].mode_1); +#endif + return val; +} + +static inline void WRITE_SERCSR(u32 val, u32 *addr, int line) +{ + csr_out32(val, addr); +#if SIBYTE_1956_WAR + csr_out32(last_mode1[line], uart_states[line].mode_1); +#endif +} + +static void init_duart_port(uart_state_t *port, int line) +{ + if (!(port->flags & DUART_INITIALIZED)) { + port->line = line; + port->status = IOADDR(A_DUART_CHANREG(line, R_DUART_STATUS)); + port->imr = IOADDR(A_DUART_IMRREG(line)); + port->tx_hold = IOADDR(A_DUART_CHANREG(line, R_DUART_TX_HOLD)); + port->rx_hold = IOADDR(A_DUART_CHANREG(line, R_DUART_RX_HOLD)); + port->mode_1 = IOADDR(A_DUART_CHANREG(line, + R_DUART_MODE_REG_1)); + port->mode_2 = IOADDR(A_DUART_CHANREG(line, + R_DUART_MODE_REG_2)); + port->clk_sel = IOADDR(A_DUART_CHANREG(line, R_DUART_CLK_SEL)); + port->cmd = IOADDR(A_DUART_CHANREG(line, R_DUART_CMD)); + port->flags |= DUART_INITIALIZED; + } +} + +/* + * Mask out the passed interrupt lines at the duart level. This should be + * called while holding the associated outp_lock. + */ +static inline void duart_mask_ints(unsigned int line, unsigned int mask) +{ + uart_state_t *port = uart_states + line; + u64 tmp = READ_SERCSR(port->imr, line); + WRITE_SERCSR(tmp & ~mask, port->imr, line); +} + + +/* Unmask the passed interrupt lines at the duart level */ +static inline void duart_unmask_ints(unsigned int line, unsigned int mask) +{ + uart_state_t *port = uart_states + line; + u64 tmp = READ_SERCSR(port->imr, line); + WRITE_SERCSR(tmp | mask, port->imr, line); +} + +static inline void transmit_char_pio(uart_state_t *us) +{ + struct tty_struct *tty = us->tty; + int blocked = 0; + + if (spin_trylock(&us->outp_lock)) { + for (;;) { + if (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_RDY)) + break; + if (us->outp_count <= 0 || tty->stopped || tty->hw_stopped) { + break; + } else { + WRITE_SERCSR(us->outp_buf[us->outp_head], + us->tx_hold, us->line); + us->outp_head = (us->outp_head + 1) & (SERIAL_XMIT_SIZE-1); + if (--us->outp_count <= 0) + break; + } + udelay(10); + } + spin_unlock(&us->outp_lock); + } else { + blocked = 1; + } + + if (!us->outp_count || tty->stopped || + tty->hw_stopped || blocked) { + us->flags &= ~TX_INTEN; + duart_mask_ints(us->line, M_DUART_IMR_TX); + } + + if (us->open && + (us->outp_count < (SERIAL_XMIT_SIZE/2))) { + /* + * We told the discipline at one point that we had no + * space, so it went to sleep. Wake it up when we hit + * half empty + */ + if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && + tty->ldisc.write_wakeup) + tty->ldisc.write_wakeup(tty); + wake_up_interruptible(&tty->write_wait); + } +} + +/* + * Generic interrupt handler for both channels. dev_id is a pointer + * to the proper uart_states structure, so from that we can derive + * which port interrupted + */ + +static irqreturn_t duart_int(int irq, void *dev_id, struct pt_regs *regs) +{ + uart_state_t *us = (uart_state_t *)dev_id; + struct tty_struct *tty = us->tty; + unsigned int status = READ_SERCSR(us->status, us->line); + +#ifdef DUART_SPEW + printk("DUART INT\n"); +#endif + + if (status & M_DUART_RX_RDY) { + int counter = 2048; + unsigned int ch; + + if (status & M_DUART_OVRUN_ERR) + tty_insert_flip_char(tty, 0, TTY_OVERRUN); + if (status & M_DUART_PARITY_ERR) { + printk("Parity error!\n"); + } else if (status & M_DUART_FRM_ERR) { + printk("Frame error!\n"); + } + + while (counter > 0) { + if (!(READ_SERCSR(us->status, us->line) & M_DUART_RX_RDY)) + break; + ch = READ_SERCSR(us->rx_hold, us->line); + if (tty->flip.count < TTY_FLIPBUF_SIZE) { + *tty->flip.char_buf_ptr++ = ch; + *tty->flip.flag_buf_ptr++ = 0; + tty->flip.count++; + } + udelay(1); + counter--; + } + tty_flip_buffer_push(tty); + } + + if (status & M_DUART_TX_RDY) { + transmit_char_pio(us); + } + + return IRQ_HANDLED; +} + +/* + * Actual driver functions + */ + +/* Return the number of characters we can accomodate in a write at this instant */ +static int duart_write_room(struct tty_struct *tty) +{ + uart_state_t *us = (uart_state_t *) tty->driver_data; + int retval; + + retval = SERIAL_XMIT_SIZE - us->outp_count; + +#ifdef DUART_SPEW + printk("duart_write_room called, returning %i\n", retval); +#endif + + return retval; +} + +/* memcpy the data from src to destination, but take extra care if the + data is coming from user space */ +static inline int copy_buf(char *dest, const char *src, int size, int from_user) +{ + if (from_user) { + (void) copy_from_user(dest, src, size); + } else { + memcpy(dest, src, size); + } + return size; +} + +/* + * Buffer up to count characters from buf to be written. If we don't have + * other characters buffered, enable the tx interrupt to start sending + */ +static int duart_write(struct tty_struct *tty, const unsigned char *buf, + int count) +{ + uart_state_t *us; + int c, t, total = 0; + unsigned long flags; + + if (!tty) return 0; + + us = tty->driver_data; + if (!us) return 0; + +#ifdef DUART_SPEW + printk("duart_write called for %i chars by %i (%s)\n", count, current->pid, current->comm); +#endif + + spin_lock_irqsave(&us->outp_lock, flags); + + for (;;) { + c = count; + + t = SERIAL_XMIT_SIZE - us->outp_tail; + if (t < c) c = t; + + t = SERIAL_XMIT_SIZE - 1 - us->outp_count; + if (t < c) c = t; + + if (c <= 0) break; + + memcpy(us->outp_buf + us->outp_tail, buf, c); + + us->outp_count += c; + us->outp_tail = (us->outp_tail + c) & (SERIAL_XMIT_SIZE - 1); + buf += c; + count -= c; + total += c; + } + + spin_unlock_irqrestore(&us->outp_lock, flags); + + if (us->outp_count && !tty->stopped && + !tty->hw_stopped && !(us->flags & TX_INTEN)) { + us->flags |= TX_INTEN; + duart_unmask_ints(us->line, M_DUART_IMR_TX); + } + + return total; +} + + +/* Buffer one character to be written. If there's not room for it, just drop + it on the floor. This is used for echo, among other things */ +static void duart_put_char(struct tty_struct *tty, u_char ch) +{ + uart_state_t *us = (uart_state_t *) tty->driver_data; + unsigned long flags; + +#ifdef DUART_SPEW + printk("duart_put_char called. Char is %x (%c)\n", (int)ch, ch); +#endif + + spin_lock_irqsave(&us->outp_lock, flags); + + if (us->outp_count == SERIAL_XMIT_SIZE) { + spin_unlock_irqrestore(&us->outp_lock, flags); + return; + } + + us->outp_buf[us->outp_tail] = ch; + us->outp_tail = (us->outp_tail + 1) &(SERIAL_XMIT_SIZE-1); + us->outp_count++; + + spin_unlock_irqrestore(&us->outp_lock, flags); +} + +static void duart_flush_chars(struct tty_struct * tty) +{ + uart_state_t *port; + + if (!tty) return; + + port = tty->driver_data; + + if (!port) return; + + if (port->outp_count <= 0 || tty->stopped || tty->hw_stopped) { + return; + } + + port->flags |= TX_INTEN; + duart_unmask_ints(port->line, M_DUART_IMR_TX); +} + +/* Return the number of characters in the output buffer that have yet to be + written */ +static int duart_chars_in_buffer(struct tty_struct *tty) +{ + uart_state_t *us = (uart_state_t *) tty->driver_data; + int retval; + + retval = us->outp_count; + +#ifdef DUART_SPEW + printk("duart_chars_in_buffer returning %i\n", retval); +#endif + return retval; +} + +/* Kill everything we haven't yet shoved into the FIFO. Turn off the + transmit interrupt since we've nothing more to transmit */ +static void duart_flush_buffer(struct tty_struct *tty) +{ + uart_state_t *us = (uart_state_t *) tty->driver_data; + unsigned long flags; + +#ifdef DUART_SPEW + printk("duart_flush_buffer called\n"); +#endif + spin_lock_irqsave(&us->outp_lock, flags); + us->outp_head = us->outp_tail = us->outp_count = 0; + spin_unlock_irqrestore(&us->outp_lock, flags); + + wake_up_interruptible(&us->tty->write_wait); + if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && + tty->ldisc.write_wakeup) + tty->ldisc.write_wakeup(tty); +} + + +/* See sb1250 user manual for details on these registers */ +static inline void duart_set_cflag(unsigned int line, unsigned int cflag) +{ + unsigned int mode_reg1 = 0, mode_reg2 = 0; + unsigned int clk_divisor; + uart_state_t *port = uart_states + line; + + switch (cflag & CSIZE) { + case CS7: + mode_reg1 |= V_DUART_BITS_PER_CHAR_7; + + default: + /* We don't handle CS5 or CS6...is there a way we're supposed to flag this? + right now we just force them to CS8 */ + mode_reg1 |= 0x0; + break; + } + if (cflag & CSTOPB) { + mode_reg2 |= M_DUART_STOP_BIT_LEN_2; + } + if (!(cflag & PARENB)) { + mode_reg1 |= V_DUART_PARITY_MODE_NONE; + } + if (cflag & PARODD) { + mode_reg1 |= M_DUART_PARITY_TYPE_ODD; + } + + /* Formula for this is (5000000/baud)-1, but we saturate + at 12 bits, which means we can't actually do anything less + that 1200 baud */ + switch (cflag & CBAUD) { + case B200: + case B300: + case B1200: clk_divisor = 4095; break; + case B1800: clk_divisor = 2776; break; + case B2400: clk_divisor = 2082; break; + case B4800: clk_divisor = 1040; break; + default: + case B9600: clk_divisor = 519; break; + case B19200: clk_divisor = 259; break; + case B38400: clk_divisor = 129; break; + case B57600: clk_divisor = 85; break; + case B115200: clk_divisor = 42; break; + } + WRITE_SERCSR(mode_reg1, port->mode_1, port->line); + WRITE_SERCSR(mode_reg2, port->mode_2, port->line); + WRITE_SERCSR(clk_divisor, port->clk_sel, port->line); + port->last_cflags = cflag; +} + + +/* Handle notification of a termios change. */ +static void duart_set_termios(struct tty_struct *tty, struct termios *old) +{ + uart_state_t *us = (uart_state_t *) tty->driver_data; + +#ifdef DUART_SPEW + printk("duart_set_termios called by %i (%s)\n", current->pid, current->comm); +#endif + if (old && tty->termios->c_cflag == old->c_cflag) + return; + duart_set_cflag(us->line, tty->termios->c_cflag); +} + +static int get_serial_info(uart_state_t *us, struct serial_struct * retinfo) { + + struct serial_struct tmp; + + memset(&tmp, 0, sizeof(tmp)); + + tmp.type=PORT_SB1250; + tmp.line=us->line; + tmp.port=A_DUART_CHANREG(tmp.line,0); + tmp.irq=K_INT_UART_0 + tmp.line; + tmp.xmit_fifo_size=16; /* fixed by hw */ + tmp.baud_base=5000000; + tmp.io_type=SERIAL_IO_MEM; + + if (copy_to_user(retinfo,&tmp,sizeof(*retinfo))) + return -EFAULT; + + return 0; +} + +static int duart_ioctl(struct tty_struct *tty, struct file * file, + unsigned int cmd, unsigned long arg) +{ + uart_state_t *us = (uart_state_t *) tty->driver_data; + +/* if (serial_paranoia_check(info, tty->device, "rs_ioctl")) + return -ENODEV;*/ + switch (cmd) { + case TIOCMGET: + printk("Ignoring TIOCMGET\n"); + break; + case TIOCMBIS: + printk("Ignoring TIOCMBIS\n"); + break; + case TIOCMBIC: + printk("Ignoring TIOCMBIC\n"); + break; + case TIOCMSET: + printk("Ignoring TIOCMSET\n"); + break; + case TIOCGSERIAL: + return get_serial_info(us,(struct serial_struct *) arg); + case TIOCSSERIAL: + printk("Ignoring TIOCSSERIAL\n"); + break; + case TIOCSERCONFIG: + printk("Ignoring TIOCSERCONFIG\n"); + break; + case TIOCSERGETLSR: /* Get line status register */ + printk("Ignoring TIOCSERGETLSR\n"); + break; + case TIOCSERGSTRUCT: + printk("Ignoring TIOCSERGSTRUCT\n"); + break; + case TIOCMIWAIT: + printk("Ignoring TIOCMIWAIT\n"); + break; + case TIOCGICOUNT: + printk("Ignoring TIOCGICOUNT\n"); + break; + case TIOCSERGWILD: + printk("Ignoring TIOCSERGWILD\n"); + break; + case TIOCSERSWILD: + printk("Ignoring TIOCSERSWILD\n"); + break; + default: + break; + } +// printk("Ignoring IOCTL %x from pid %i (%s)\n", cmd, current->pid, current->comm); + return -ENOIOCTLCMD; +} + +/* XXXKW locking? */ +static void duart_start(struct tty_struct *tty) +{ + uart_state_t *us = (uart_state_t *) tty->driver_data; + +#ifdef DUART_SPEW + printk("duart_start called\n"); +#endif + + if (us->outp_count && !(us->flags & TX_INTEN)) { + us->flags |= TX_INTEN; + duart_unmask_ints(us->line, M_DUART_IMR_TX); + } +} + +/* XXXKW locking? */ +static void duart_stop(struct tty_struct *tty) +{ + uart_state_t *us = (uart_state_t *) tty->driver_data; + +#ifdef DUART_SPEW + printk("duart_stop called\n"); +#endif + + if (us->outp_count && (us->flags & TX_INTEN)) { + us->flags &= ~TX_INTEN; + duart_mask_ints(us->line, M_DUART_IMR_TX); + } +} + +/* Not sure on the semantics of this; are we supposed to wait until the stuff + already in the hardware FIFO drains, or are we supposed to wait until + we've drained the output buffer, too? I'm assuming the former, 'cause thats + what the other drivers seem to assume +*/ + +static void duart_wait_until_sent(struct tty_struct *tty, int timeout) +{ + uart_state_t *us = (uart_state_t *) tty->driver_data; + unsigned long orig_jiffies; + + orig_jiffies = jiffies; +#ifdef DUART_SPEW + printk("duart_wait_until_sent(%d)+\n", timeout); +#endif + while (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_EMT)) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); + if (signal_pending(current)) + break; + if (timeout && time_after(jiffies, orig_jiffies + timeout)) + break; + } +#ifdef DUART_SPEW + printk("duart_wait_until_sent()-\n"); +#endif +} + +/* + * duart_hangup() --- called by tty_hangup() when a hangup is signaled. + */ +static void duart_hangup(struct tty_struct *tty) +{ + uart_state_t *us = (uart_state_t *) tty->driver_data; + + duart_flush_buffer(tty); + us->open = 0; + us->tty = 0; +} + +/* + * Open a tty line. Note that this can be called multiple times, so ->open can + * be >1. Only set up the tty struct if this is a "new" open, e.g. ->open was + * zero + */ +static int duart_open(struct tty_struct *tty, struct file *filp) +{ + uart_state_t *us; + unsigned int line = tty->index; + unsigned long flags; + + if ((line >= tty->driver->num) || !sb1250_duart_present[line]) + return -ENODEV; + +#ifdef DUART_SPEW + printk("duart_open called by %i (%s), tty is %p, rw is %p, ww is %p\n", + current->pid, current->comm, tty, tty->read_wait, + tty->write_wait); +#endif + + us = uart_states + line; + tty->driver_data = us; + + spin_lock_irqsave(&open_lock, flags); + if (!us->open) { + us->tty = tty; + us->tty->termios->c_cflag = us->last_cflags; + } + us->open++; + us->flags &= ~TX_INTEN; + duart_unmask_ints(line, M_DUART_IMR_RX); + spin_unlock_irqrestore(&open_lock, flags); + + return 0; +} + + +/* + * Close a reference count out. If reference count hits zero, null the + * tty, kill the interrupts. The tty_io driver is responsible for making + * sure we've cleared out our internal buffers before calling close() + */ +static void duart_close(struct tty_struct *tty, struct file *filp) +{ + uart_state_t *us = (uart_state_t *) tty->driver_data; + unsigned long flags; + +#ifdef DUART_SPEW + printk("duart_close called by %i (%s)\n", current->pid, current->comm); +#endif + + if (!us || !us->open) + return; + + spin_lock_irqsave(&open_lock, flags); + if (tty_hung_up_p(filp)) { + spin_unlock_irqrestore(&open_lock, flags); + return; + } + + if (--us->open < 0) { + us->open = 0; + printk(KERN_ERR "duart: bad open count: %d\n", us->open); + } + if (us->open) { + spin_unlock_irqrestore(&open_lock, flags); + return; + } + + spin_unlock_irqrestore(&open_lock, flags); + + tty->closing = 1; + + /* Stop accepting input */ + duart_mask_ints(us->line, M_DUART_IMR_RX); + /* Wait for FIFO to drain */ + while (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_EMT)) + ; + + if (tty->driver->flush_buffer) + tty->driver->flush_buffer(tty); + if (tty->ldisc.flush_buffer) + tty->ldisc.flush_buffer(tty); + tty->closing = 0; +} + + +static struct tty_operations duart_ops = { + .open = duart_open, + .close = duart_close, + .write = duart_write, + .put_char = duart_put_char, + .flush_chars = duart_flush_chars, + .write_room = duart_write_room, + .chars_in_buffer = duart_chars_in_buffer, + .flush_buffer = duart_flush_buffer, + .ioctl = duart_ioctl, +// .throttle = duart_throttle, +// .unthrottle = duart_unthrottle, + .set_termios = duart_set_termios, + .stop = duart_stop, + .start = duart_start, + .hangup = duart_hangup, + .wait_until_sent = duart_wait_until_sent, +}; + +/* Set up the driver and register it, register the 2 1250 UART interrupts. This + is called from tty_init, or as a part of the module init */ +static int __init sb1250_duart_init(void) +{ + int i; + + sb1250_duart_driver = alloc_tty_driver(DUART_MAX_LINE); + if (!sb1250_duart_driver) + return -ENOMEM; + + sb1250_duart_driver->owner = THIS_MODULE; + sb1250_duart_driver->name = "duart"; + sb1250_duart_driver->devfs_name = "duart/"; + sb1250_duart_driver->major = TTY_MAJOR; + sb1250_duart_driver->minor_start = SB1250_DUART_MINOR_BASE; + sb1250_duart_driver->type = TTY_DRIVER_TYPE_SERIAL; + sb1250_duart_driver->subtype = SERIAL_TYPE_NORMAL; + sb1250_duart_driver->init_termios = tty_std_termios; + sb1250_duart_driver->flags = TTY_DRIVER_REAL_RAW; + tty_set_operations(sb1250_duart_driver, &duart_ops); + + for (i=0; ioutp_lock); + duart_mask_ints(i, M_DUART_IMR_ALL); + if (request_irq(K_INT_UART_0+i, duart_int, 0, "uart", port)) { + panic("Couldn't get uart0 interrupt line"); + } + __raw_writeq(M_DUART_RX_EN|M_DUART_TX_EN, + IOADDR(A_DUART_CHANREG(i, R_DUART_CMD))); + duart_set_cflag(i, DEFAULT_CFLAGS); + } + + /* Interrupts are now active, our ISR can be called. */ + + if (tty_register_driver(sb1250_duart_driver)) { + printk(KERN_ERR "Couldn't register sb1250 duart serial driver\n"); + put_tty_driver(sb1250_duart_driver); + return 1; + } + return 0; +} + +/* Unload the driver. Unregister stuff, get ready to go away */ +static void __exit sb1250_duart_fini(void) +{ + unsigned long flags; + int i; + + local_irq_save(flags); + tty_unregister_driver(sb1250_duart_driver); + put_tty_driver(sb1250_duart_driver); + + for (i=0; istatus, line) & M_DUART_TX_RDY)) ; + WRITE_SERCSR(c, port->tx_hold, line); + while (!(READ_SERCSR(port->status, port->line) & M_DUART_TX_EMT)) ; +} + +static void ser_console_write(struct console *cons, const char *s, + unsigned int count) +{ + int line = cons->index; + uart_state_t *port = uart_states + line; + u32 imr; + + imr = READ_SERCSR(port->imr, line); + WRITE_SERCSR(0, port->imr, line); + while (count--) { + if (*s == '\n') + serial_outc('\r', line); + serial_outc(*s++, line); + } + WRITE_SERCSR(imr, port->imr, line); +} + +static struct tty_driver *ser_console_device(struct console *c, int *index) +{ + *index = c->index; + return sb1250_duart_driver; +} + +static int ser_console_setup(struct console *cons, char *str) +{ + int i; + + for (i=0; imode_1, i); + WRITE_SERCSR(M_DUART_STOP_BIT_LEN_1, + port->mode_2, i); + WRITE_SERCSR(V_DUART_BAUD_RATE(115200), + port->clk_sel, i); + WRITE_SERCSR(M_DUART_RX_EN|M_DUART_TX_EN, + port->cmd, i); + } + return 0; +} + +static struct console sb1250_ser_cons = { + .name = "duart", + .write = ser_console_write, + .device = ser_console_device, + .setup = ser_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, +}; + +static int __init sb1250_serial_console_init(void) +{ + register_console(&sb1250_ser_cons); + return 0; +} + +console_initcall(sb1250_serial_console_init); + +#endif /* CONFIG_SIBYTE_SB1250_DUART_CONSOLE */ diff -Naur linux-2.6.12.6.orig/drivers/char/tb0219.c linux-2.6.12.6/drivers/char/tb0219.c --- linux-2.6.12.6.orig/drivers/char/tb0219.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/char/tb0219.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,347 +0,0 @@ -/* - * Driver for TANBAC TB0219 base board. - * - * Copyright (C) 2005 Yoichi Yuasa - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include -#include -#include -#include - -#include -#include - -MODULE_AUTHOR("Yoichi Yuasa "); -MODULE_DESCRIPTION("TANBAC TB0219 base board driver"); -MODULE_LICENSE("GPL"); - -static int major; /* default is dynamic major device number */ -module_param(major, int, 0); -MODULE_PARM_DESC(major, "Major device number"); - -static void (*old_machine_restart)(char *command); -static void __iomem *tb0219_base; -static spinlock_t tb0219_lock; - -#define tb0219_read(offset) readw(tb0219_base + (offset)) -#define tb0219_write(offset, value) writew((value), tb0219_base + (offset)) - -#define TB0219_START 0x0a000000UL -#define TB0219_SIZE 0x20UL - -#define TB0219_LED 0x00 -#define TB0219_GPIO_INPUT 0x02 -#define TB0219_GPIO_OUTPUT 0x04 -#define TB0219_DIP_SWITCH 0x06 -#define TB0219_MISC 0x08 -#define TB0219_RESET 0x0e -#define TB0219_PCI_SLOT1_IRQ_STATUS 0x10 -#define TB0219_PCI_SLOT2_IRQ_STATUS 0x12 -#define TB0219_PCI_SLOT3_IRQ_STATUS 0x14 - -typedef enum { - TYPE_LED, - TYPE_GPIO_OUTPUT, -} tb0219_type_t; - -/* - * Minor device number - * 0 = 7 segment LED - * - * 16 = GPIO IN 0 - * 17 = GPIO IN 1 - * 18 = GPIO IN 2 - * 19 = GPIO IN 3 - * 20 = GPIO IN 4 - * 21 = GPIO IN 5 - * 22 = GPIO IN 6 - * 23 = GPIO IN 7 - * - * 32 = GPIO OUT 0 - * 33 = GPIO OUT 1 - * 34 = GPIO OUT 2 - * 35 = GPIO OUT 3 - * 36 = GPIO OUT 4 - * 37 = GPIO OUT 5 - * 38 = GPIO OUT 6 - * 39 = GPIO OUT 7 - * - * 48 = DIP switch 1 - * 49 = DIP switch 2 - * 50 = DIP switch 3 - * 51 = DIP switch 4 - * 52 = DIP switch 5 - * 53 = DIP switch 6 - * 54 = DIP switch 7 - * 55 = DIP switch 8 - */ - -static inline char get_led(void) -{ - return (char)tb0219_read(TB0219_LED); -} - -static inline char get_gpio_input_pin(unsigned int pin) -{ - uint16_t values; - - values = tb0219_read(TB0219_GPIO_INPUT); - if (values & (1 << pin)) - return '1'; - - return '0'; -} - -static inline char get_gpio_output_pin(unsigned int pin) -{ - uint16_t values; - - values = tb0219_read(TB0219_GPIO_OUTPUT); - if (values & (1 << pin)) - return '1'; - - return '0'; -} - -static inline char get_dip_switch(unsigned int pin) -{ - uint16_t values; - - values = tb0219_read(TB0219_DIP_SWITCH); - if (values & (1 << pin)) - return '1'; - - return '0'; -} - -static inline int set_led(char command) -{ - tb0219_write(TB0219_LED, command); - - return 0; -} - -static inline int set_gpio_output_pin(unsigned int pin, char command) -{ - unsigned long flags; - uint16_t value; - - if (command != '0' && command != '1') - return -EINVAL; - - spin_lock_irqsave(&tb0219_lock, flags); - value = tb0219_read(TB0219_GPIO_OUTPUT); - if (command == '0') - value &= ~(1 << pin); - else - value |= 1 << pin; - tb0219_write(TB0219_GPIO_OUTPUT, value); - spin_unlock_irqrestore(&tb0219_lock, flags); - - return 0; - -} - -static ssize_t tanbac_tb0219_read(struct file *file, char __user *buf, size_t len, - loff_t *ppos) -{ - unsigned int minor; - char value; - - minor = iminor(file->f_dentry->d_inode); - switch (minor) { - case 0: - value = get_led(); - break; - case 16 ... 23: - value = get_gpio_input_pin(minor - 16); - break; - case 32 ... 39: - value = get_gpio_output_pin(minor - 32); - break; - case 48 ... 55: - value = get_dip_switch(minor - 48); - break; - default: - return -EBADF; - } - - if (len <= 0) - return -EFAULT; - - if (put_user(value, buf)) - return -EFAULT; - - return 1; -} - -static ssize_t tanbac_tb0219_write(struct file *file, const char __user *data, - size_t len, loff_t *ppos) -{ - unsigned int minor; - tb0219_type_t type; - size_t i; - int retval = 0; - char c; - - minor = iminor(file->f_dentry->d_inode); - switch (minor) { - case 0: - type = TYPE_LED; - break; - case 32 ... 39: - type = TYPE_GPIO_OUTPUT; - break; - default: - return -EBADF; - } - - for (i = 0; i < len; i++) { - if (get_user(c, data + i)) - return -EFAULT; - - switch (type) { - case TYPE_LED: - retval = set_led(c); - break; - case TYPE_GPIO_OUTPUT: - retval = set_gpio_output_pin(minor - 32, c); - break; - } - - if (retval < 0) - break; - } - - return i; -} - -static int tanbac_tb0219_open(struct inode *inode, struct file *file) -{ - unsigned int minor; - - minor = iminor(inode); - switch (minor) { - case 0: - case 16 ... 23: - case 32 ... 39: - case 48 ... 55: - return nonseekable_open(inode, file); - default: - break; - } - - return -EBADF; -} - -static int tanbac_tb0219_release(struct inode *inode, struct file *file) -{ - return 0; -} - -static struct file_operations tb0219_fops = { - .owner = THIS_MODULE, - .read = tanbac_tb0219_read, - .write = tanbac_tb0219_write, - .open = tanbac_tb0219_open, - .release = tanbac_tb0219_release, -}; - -static void tb0219_restart(char *command) -{ - tb0219_write(TB0219_RESET, 0); -} - -static int tb0219_probe(struct device *dev) -{ - int retval; - - if (request_mem_region(TB0219_START, TB0219_SIZE, "TB0219") == NULL) - return -EBUSY; - - tb0219_base = ioremap(TB0219_START, TB0219_SIZE); - if (tb0219_base == NULL) { - release_mem_region(TB0219_START, TB0219_SIZE); - return -ENOMEM; - } - - retval = register_chrdev(major, "TB0219", &tb0219_fops); - if (retval < 0) { - iounmap(tb0219_base); - tb0219_base = NULL; - release_mem_region(TB0219_START, TB0219_SIZE); - return retval; - } - - spin_lock_init(&tb0219_lock); - - old_machine_restart = _machine_restart; - _machine_restart = tb0219_restart; - - if (major == 0) { - major = retval; - printk(KERN_INFO "TB0219: major number %d\n", major); - } - - return 0; -} - -static int tb0219_remove(struct device *dev) -{ - _machine_restart = old_machine_restart; - - iounmap(tb0219_base); - tb0219_base = NULL; - - release_mem_region(TB0219_START, TB0219_SIZE); - - return 0; -} - -static struct platform_device *tb0219_platform_device; - -static struct device_driver tb0219_device_driver = { - .name = "TB0219", - .bus = &platform_bus_type, - .probe = tb0219_probe, - .remove = tb0219_remove, -}; - -static int __devinit tanbac_tb0219_init(void) -{ - int retval; - - tb0219_platform_device = platform_device_register_simple("TB0219", -1, NULL, 0); - if (IS_ERR(tb0219_platform_device)) - return PTR_ERR(tb0219_platform_device); - - retval = driver_register(&tb0219_device_driver); - if (retval < 0) - platform_device_unregister(tb0219_platform_device); - - return retval; -} - -static void __devexit tanbac_tb0219_exit(void) -{ - driver_unregister(&tb0219_device_driver); - - platform_device_unregister(tb0219_platform_device); -} - -module_init(tanbac_tb0219_init); -module_exit(tanbac_tb0219_exit); diff -Naur linux-2.6.12.6.orig/drivers/char/vr41xx_rtc.c linux-2.6.12.6/drivers/char/vr41xx_rtc.c --- linux-2.6.12.6.orig/drivers/char/vr41xx_rtc.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/char/vr41xx_rtc.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,709 +0,0 @@ -/* - * Driver for NEC VR4100 series Real Time Clock unit. - * - * Copyright (C) 2003-2005 Yoichi Yuasa - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -MODULE_AUTHOR("Yoichi Yuasa "); -MODULE_DESCRIPTION("NEC VR4100 series RTC driver"); -MODULE_LICENSE("GPL"); - -#define RTC1_TYPE1_START 0x0b0000c0UL -#define RTC1_TYPE1_END 0x0b0000dfUL -#define RTC2_TYPE1_START 0x0b0001c0UL -#define RTC2_TYPE1_END 0x0b0001dfUL - -#define RTC1_TYPE2_START 0x0f000100UL -#define RTC1_TYPE2_END 0x0f00011fUL -#define RTC2_TYPE2_START 0x0f000120UL -#define RTC2_TYPE2_END 0x0f00013fUL - -#define RTC1_SIZE 0x20 -#define RTC2_SIZE 0x20 - -/* RTC 1 registers */ -#define ETIMELREG 0x00 -#define ETIMEMREG 0x02 -#define ETIMEHREG 0x04 -/* RFU */ -#define ECMPLREG 0x08 -#define ECMPMREG 0x0a -#define ECMPHREG 0x0c -/* RFU */ -#define RTCL1LREG 0x10 -#define RTCL1HREG 0x12 -#define RTCL1CNTLREG 0x14 -#define RTCL1CNTHREG 0x16 -#define RTCL2LREG 0x18 -#define RTCL2HREG 0x1a -#define RTCL2CNTLREG 0x1c -#define RTCL2CNTHREG 0x1e - -/* RTC 2 registers */ -#define TCLKLREG 0x00 -#define TCLKHREG 0x02 -#define TCLKCNTLREG 0x04 -#define TCLKCNTHREG 0x06 -/* RFU */ -#define RTCINTREG 0x1e - #define TCLOCK_INT 0x08 - #define RTCLONG2_INT 0x04 - #define RTCLONG1_INT 0x02 - #define ELAPSEDTIME_INT 0x01 - -#define RTC_FREQUENCY 32768 -#define MAX_PERIODIC_RATE 6553 -#define MAX_USER_PERIODIC_RATE 64 - -static void __iomem *rtc1_base; -static void __iomem *rtc2_base; - -#define rtc1_read(offset) readw(rtc1_base + (offset)) -#define rtc1_write(offset, value) writew((value), rtc1_base + (offset)) - -#define rtc2_read(offset) readw(rtc2_base + (offset)) -#define rtc2_write(offset, value) writew((value), rtc2_base + (offset)) - -static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */ - -static spinlock_t rtc_task_lock; -static wait_queue_head_t rtc_wait; -static unsigned long rtc_irq_data; -static struct fasync_struct *rtc_async_queue; -static rtc_task_t *rtc_callback; -static char rtc_name[] = "RTC"; -static unsigned long periodic_frequency; -static unsigned long periodic_count; - -typedef enum { - RTC_RELEASE, - RTC_OPEN, -} rtc_status_t; - -static rtc_status_t rtc_status; - -typedef enum { - FUNCTION_RTC_IOCTL, - FUNCTION_RTC_CONTROL, -} rtc_callfrom_t; - -struct resource rtc_resource[2] = { - { .name = rtc_name, - .flags = IORESOURCE_MEM, }, - { .name = rtc_name, - .flags = IORESOURCE_MEM, }, -}; - -#define RTC_NUM_RESOURCES sizeof(rtc_resource) / sizeof(struct resource) - -static inline unsigned long read_elapsed_second(void) -{ - unsigned long first_low, first_mid, first_high; - unsigned long second_low, second_mid, second_high; - - do { - first_low = rtc1_read(ETIMELREG); - first_mid = rtc1_read(ETIMEMREG); - first_high = rtc1_read(ETIMEHREG); - second_low = rtc1_read(ETIMELREG); - second_mid = rtc1_read(ETIMEMREG); - second_high = rtc1_read(ETIMEHREG); - } while (first_low != second_low || first_mid != second_mid || - first_high != second_high); - - return (first_high << 17) | (first_mid << 1) | (first_low >> 15); -} - -static inline void write_elapsed_second(unsigned long sec) -{ - spin_lock_irq(&rtc_lock); - - rtc1_write(ETIMELREG, (uint16_t)(sec << 15)); - rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1)); - rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17)); - - spin_unlock_irq(&rtc_lock); -} - -static void set_alarm(struct rtc_time *time) -{ - unsigned long alarm_sec; - - alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday, - time->tm_hour, time->tm_min, time->tm_sec); - - spin_lock_irq(&rtc_lock); - - rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15)); - rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1)); - rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17)); - - spin_unlock_irq(&rtc_lock); -} - -static void read_alarm(struct rtc_time *time) -{ - unsigned long low, mid, high; - - spin_lock_irq(&rtc_lock); - - low = rtc1_read(ECMPLREG); - mid = rtc1_read(ECMPMREG); - high = rtc1_read(ECMPHREG); - - spin_unlock_irq(&rtc_lock); - - to_tm((high << 17) | (mid << 1) | (low >> 15), time); - time->tm_year -= 1900; -} - -static void read_time(struct rtc_time *time) -{ - unsigned long epoch_sec, elapsed_sec; - - epoch_sec = mktime(epoch, 1, 1, 0, 0, 0); - elapsed_sec = read_elapsed_second(); - - to_tm(epoch_sec + elapsed_sec, time); - time->tm_year -= 1900; -} - -static void set_time(struct rtc_time *time) -{ - unsigned long epoch_sec, current_sec; - - epoch_sec = mktime(epoch, 1, 1, 0, 0, 0); - current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday, - time->tm_hour, time->tm_min, time->tm_sec); - - write_elapsed_second(current_sec - epoch_sec); -} - -static ssize_t rtc_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) -{ - DECLARE_WAITQUEUE(wait, current); - unsigned long irq_data; - int retval = 0; - - if (count != sizeof(unsigned int) && count != sizeof(unsigned long)) - return -EINVAL; - - add_wait_queue(&rtc_wait, &wait); - - do { - __set_current_state(TASK_INTERRUPTIBLE); - - spin_lock_irq(&rtc_lock); - irq_data = rtc_irq_data; - rtc_irq_data = 0; - spin_unlock_irq(&rtc_lock); - - if (irq_data != 0) - break; - - if (file->f_flags & O_NONBLOCK) { - retval = -EAGAIN; - break; - } - - if (signal_pending(current)) { - retval = -ERESTARTSYS; - break; - } - } while (1); - - if (retval == 0) { - if (count == sizeof(unsigned int)) { - retval = put_user(irq_data, (unsigned int __user *)buf); - if (retval == 0) - retval = sizeof(unsigned int); - } else { - retval = put_user(irq_data, (unsigned long __user *)buf); - if (retval == 0) - retval = sizeof(unsigned long); - } - - } - - __set_current_state(TASK_RUNNING); - remove_wait_queue(&rtc_wait, &wait); - - return retval; -} - -static unsigned int rtc_poll(struct file *file, struct poll_table_struct *table) -{ - poll_wait(file, &rtc_wait, table); - - if (rtc_irq_data != 0) - return POLLIN | POLLRDNORM; - - return 0; -} - -static int rtc_do_ioctl(unsigned int cmd, unsigned long arg, rtc_callfrom_t from) -{ - struct rtc_time time; - unsigned long count; - - switch (cmd) { - case RTC_AIE_ON: - enable_irq(ELAPSEDTIME_IRQ); - break; - case RTC_AIE_OFF: - disable_irq(ELAPSEDTIME_IRQ); - break; - case RTC_PIE_ON: - enable_irq(RTCLONG1_IRQ); - break; - case RTC_PIE_OFF: - disable_irq(RTCLONG1_IRQ); - break; - case RTC_ALM_SET: - if (copy_from_user(&time, (struct rtc_time __user *)arg, - sizeof(struct rtc_time))) - return -EFAULT; - - set_alarm(&time); - break; - case RTC_ALM_READ: - memset(&time, 0, sizeof(struct rtc_time)); - read_alarm(&time); - break; - case RTC_RD_TIME: - memset(&time, 0, sizeof(struct rtc_time)); - read_time(&time); - if (copy_to_user((void __user *)arg, &time, sizeof(struct rtc_time))) - return -EFAULT; - break; - case RTC_SET_TIME: - if (capable(CAP_SYS_TIME) == 0) - return -EACCES; - - if (copy_from_user(&time, (struct rtc_time __user *)arg, - sizeof(struct rtc_time))) - return -EFAULT; - - set_time(&time); - break; - case RTC_IRQP_READ: - return put_user(periodic_frequency, (unsigned long __user *)arg); - break; - case RTC_IRQP_SET: - if (arg > MAX_PERIODIC_RATE) - return -EINVAL; - - if (from == FUNCTION_RTC_IOCTL && arg > MAX_USER_PERIODIC_RATE && - capable(CAP_SYS_RESOURCE) == 0) - return -EACCES; - - periodic_frequency = arg; - - count = RTC_FREQUENCY; - do_div(count, arg); - - periodic_count = count; - - spin_lock_irq(&rtc_lock); - - rtc1_write(RTCL1LREG, count); - rtc1_write(RTCL1HREG, count >> 16); - - spin_unlock_irq(&rtc_lock); - break; - case RTC_EPOCH_READ: - return put_user(epoch, (unsigned long __user *)arg); - case RTC_EPOCH_SET: - /* Doesn't support before 1900 */ - if (arg < 1900) - return -EINVAL; - - if (capable(CAP_SYS_TIME) == 0) - return -EACCES; - - epoch = arg; - break; - default: - return -EINVAL; - } - - return 0; -} - -static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) -{ - return rtc_do_ioctl(cmd, arg, FUNCTION_RTC_IOCTL); -} - -static int rtc_open(struct inode *inode, struct file *file) -{ - spin_lock_irq(&rtc_lock); - - if (rtc_status == RTC_OPEN) { - spin_unlock_irq(&rtc_lock); - return -EBUSY; - } - - rtc_status = RTC_OPEN; - rtc_irq_data = 0; - - spin_unlock_irq(&rtc_lock); - - return 0; -} - -static int rtc_release(struct inode *inode, struct file *file) -{ - if (file->f_flags & FASYNC) - (void)fasync_helper(-1, file, 0, &rtc_async_queue); - - spin_lock_irq(&rtc_lock); - - rtc1_write(ECMPLREG, 0); - rtc1_write(ECMPMREG, 0); - rtc1_write(ECMPHREG, 0); - rtc1_write(RTCL1LREG, 0); - rtc1_write(RTCL1HREG, 0); - - rtc_status = RTC_RELEASE; - - spin_unlock_irq(&rtc_lock); - - disable_irq(ELAPSEDTIME_IRQ); - disable_irq(RTCLONG1_IRQ); - - return 0; -} - -static int rtc_fasync(int fd, struct file *file, int on) -{ - return fasync_helper(fd, file, on, &rtc_async_queue); -} - -static struct file_operations rtc_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .read = rtc_read, - .poll = rtc_poll, - .ioctl = rtc_ioctl, - .open = rtc_open, - .release = rtc_release, - .fasync = rtc_fasync, -}; - -static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - spin_lock(&rtc_lock); - rtc2_write(RTCINTREG, ELAPSEDTIME_INT); - - rtc_irq_data += 0x100; - rtc_irq_data &= ~0xff; - rtc_irq_data |= RTC_AF; - spin_unlock(&rtc_lock); - - spin_lock(&rtc_lock); - if (rtc_callback) - rtc_callback->func(rtc_callback->private_data); - spin_unlock(&rtc_lock); - - wake_up_interruptible(&rtc_wait); - - kill_fasync(&rtc_async_queue, SIGIO, POLL_IN); - - return IRQ_HANDLED; -} - -static irqreturn_t rtclong1_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - unsigned long count = periodic_count; - - spin_lock(&rtc_lock); - rtc2_write(RTCINTREG, RTCLONG1_INT); - - rtc1_write(RTCL1LREG, count); - rtc1_write(RTCL1HREG, count >> 16); - - rtc_irq_data += 0x100; - rtc_irq_data &= ~0xff; - rtc_irq_data |= RTC_PF; - spin_unlock(&rtc_lock); - - spin_lock(&rtc_task_lock); - if (rtc_callback) - rtc_callback->func(rtc_callback->private_data); - spin_unlock(&rtc_task_lock); - - wake_up_interruptible(&rtc_wait); - - kill_fasync(&rtc_async_queue, SIGIO, POLL_IN); - - return IRQ_HANDLED; -} - -int rtc_register(rtc_task_t *task) -{ - if (task == NULL || task->func == NULL) - return -EINVAL; - - spin_lock_irq(&rtc_lock); - if (rtc_status == RTC_OPEN) { - spin_unlock_irq(&rtc_lock); - return -EBUSY; - } - - spin_lock(&rtc_task_lock); - if (rtc_callback != NULL) { - spin_unlock(&rtc_task_lock); - spin_unlock_irq(&rtc_task_lock); - return -EBUSY; - } - - rtc_callback = task; - spin_unlock(&rtc_task_lock); - - rtc_status = RTC_OPEN; - - spin_unlock_irq(&rtc_lock); - - return 0; -} - -EXPORT_SYMBOL_GPL(rtc_register); - -int rtc_unregister(rtc_task_t *task) -{ - spin_lock_irq(&rtc_task_lock); - if (task == NULL || rtc_callback != task) { - spin_unlock_irq(&rtc_task_lock); - return -ENXIO; - } - - spin_lock(&rtc_lock); - - rtc1_write(ECMPLREG, 0); - rtc1_write(ECMPMREG, 0); - rtc1_write(ECMPHREG, 0); - rtc1_write(RTCL1LREG, 0); - rtc1_write(RTCL1HREG, 0); - - rtc_status = RTC_RELEASE; - - spin_unlock(&rtc_lock); - - rtc_callback = NULL; - - spin_unlock_irq(&rtc_task_lock); - - disable_irq(ELAPSEDTIME_IRQ); - disable_irq(RTCLONG1_IRQ); - - return 0; -} - -EXPORT_SYMBOL_GPL(rtc_unregister); - -int rtc_control(rtc_task_t *task, unsigned int cmd, unsigned long arg) -{ - int retval = 0; - - spin_lock_irq(&rtc_task_lock); - - if (rtc_callback != task) - retval = -ENXIO; - else - rtc_do_ioctl(cmd, arg, FUNCTION_RTC_CONTROL); - - spin_unlock_irq(&rtc_task_lock); - - return retval; -} - -EXPORT_SYMBOL_GPL(rtc_control); - -static struct miscdevice rtc_miscdevice = { - .minor = RTC_MINOR, - .name = rtc_name, - .fops = &rtc_fops, -}; - -static int rtc_probe(struct device *dev) -{ - struct platform_device *pdev; - unsigned int irq; - int retval; - - pdev = to_platform_device(dev); - if (pdev->num_resources != 2) - return -EBUSY; - - rtc1_base = ioremap(pdev->resource[0].start, RTC1_SIZE); - if (rtc1_base == NULL) - return -EBUSY; - - rtc2_base = ioremap(pdev->resource[1].start, RTC2_SIZE); - if (rtc2_base == NULL) { - iounmap(rtc1_base); - rtc1_base = NULL; - return -EBUSY; - } - - retval = misc_register(&rtc_miscdevice); - if (retval < 0) { - iounmap(rtc1_base); - iounmap(rtc2_base); - rtc1_base = NULL; - rtc2_base = NULL; - return retval; - } - - spin_lock_irq(&rtc_lock); - - rtc1_write(ECMPLREG, 0); - rtc1_write(ECMPMREG, 0); - rtc1_write(ECMPHREG, 0); - rtc1_write(RTCL1LREG, 0); - rtc1_write(RTCL1HREG, 0); - - rtc_status = RTC_RELEASE; - rtc_irq_data = 0; - - spin_unlock_irq(&rtc_lock); - - init_waitqueue_head(&rtc_wait); - - irq = ELAPSEDTIME_IRQ; - retval = request_irq(irq, elapsedtime_interrupt, SA_INTERRUPT, - "elapsed_time", NULL); - if (retval == 0) { - irq = RTCLONG1_IRQ; - retval = request_irq(irq, rtclong1_interrupt, SA_INTERRUPT, - "rtclong1", NULL); - } - - if (retval < 0) { - printk(KERN_ERR "rtc: IRQ%d is busy\n", irq); - if (irq == RTCLONG1_IRQ) - free_irq(ELAPSEDTIME_IRQ, NULL); - iounmap(rtc1_base); - iounmap(rtc2_base); - rtc1_base = NULL; - rtc2_base = NULL; - return retval; - } - - disable_irq(ELAPSEDTIME_IRQ); - disable_irq(RTCLONG1_IRQ); - - spin_lock_init(&rtc_task_lock); - - printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n"); - - return 0; -} - -static int rtc_remove(struct device *dev) -{ - int retval; - - retval = misc_deregister(&rtc_miscdevice); - if (retval < 0) - return retval; - - free_irq(ELAPSEDTIME_IRQ, NULL); - free_irq(RTCLONG1_IRQ, NULL); - if (rtc1_base != NULL) - iounmap(rtc1_base); - if (rtc2_base != NULL) - iounmap(rtc2_base); - - return 0; -} - -static struct platform_device *rtc_platform_device; - -static struct device_driver rtc_device_driver = { - .name = rtc_name, - .bus = &platform_bus_type, - .probe = rtc_probe, - .remove = rtc_remove, -}; - -static int __devinit vr41xx_rtc_init(void) -{ - int retval; - - switch (current_cpu_data.cputype) { - case CPU_VR4111: - case CPU_VR4121: - rtc_resource[0].start = RTC1_TYPE1_START; - rtc_resource[0].end = RTC1_TYPE1_END; - rtc_resource[1].start = RTC2_TYPE1_START; - rtc_resource[1].end = RTC2_TYPE1_END; - break; - case CPU_VR4122: - case CPU_VR4131: - case CPU_VR4133: - rtc_resource[0].start = RTC1_TYPE2_START; - rtc_resource[0].end = RTC1_TYPE2_END; - rtc_resource[1].start = RTC2_TYPE2_START; - rtc_resource[1].end = RTC2_TYPE2_END; - break; - default: - return -ENODEV; - break; - } - - rtc_platform_device = platform_device_register_simple("RTC", -1, rtc_resource, RTC_NUM_RESOURCES); - if (IS_ERR(rtc_platform_device)) - return PTR_ERR(rtc_platform_device); - - retval = driver_register(&rtc_device_driver); - if (retval < 0) - platform_device_unregister(rtc_platform_device); - - return retval; -} - -static void __devexit vr41xx_rtc_exit(void) -{ - driver_unregister(&rtc_device_driver); - - platform_device_unregister(rtc_platform_device); -} - -module_init(vr41xx_rtc_init); -module_exit(vr41xx_rtc_exit); diff -Naur linux-2.6.12.6.orig/drivers/i2c/busses/i2c-au1550.c linux-2.6.12.6/drivers/i2c/busses/i2c-au1550.c --- linux-2.6.12.6.orig/drivers/i2c/busses/i2c-au1550.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/i2c/busses/i2c-au1550.c 2005-10-02 23:47:38.000000000 +0000 @@ -21,13 +21,12 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#include #include #include #include @@ -290,8 +289,8 @@ .functionality = au1550_func, }; -/* - * registering functions to load algorithms at runtime +/* + * registering functions to load algorithms at runtime * Prior to calling us, the 50MHz clock frequency and routing * must have been set up for the PSC indicated by the adapter. */ diff -Naur linux-2.6.12.6.orig/drivers/i2c/busses/i2c-sibyte.c linux-2.6.12.6/drivers/i2c/busses/i2c-sibyte.c --- linux-2.6.12.6.orig/drivers/i2c/busses/i2c-sibyte.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/i2c/busses/i2c-sibyte.c 2005-10-02 23:47:38.000000000 +0000 @@ -24,8 +24,8 @@ #include static struct i2c_algo_sibyte_data sibyte_board_data[2] = { - { NULL, 0, (void *) (KSEG1+A_SMB_BASE(0)) }, - { NULL, 1, (void *) (KSEG1+A_SMB_BASE(1)) } + { NULL, 0, (void *) (CKSEG1+A_SMB_BASE(0)) }, + { NULL, 1, (void *) (CKSEG1+A_SMB_BASE(1)) } }; static struct i2c_adapter sibyte_board_adapter[2] = { diff -Naur linux-2.6.12.6.orig/drivers/ide/Kconfig linux-2.6.12.6/drivers/ide/Kconfig --- linux-2.6.12.6.orig/drivers/ide/Kconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/ide/Kconfig 2005-10-02 23:47:38.000000000 +0000 @@ -771,6 +771,10 @@ This option enables the use of the sleep LED as a hard drive activity LED. +config BLK_DEV_IDE_SWARM + bool "IDE for Sibyte evaluation boards" + depends on SIBYTE_SB1xxx_SOC + config IDE_ARM def_bool ARM && (ARCH_A5K || ARCH_CLPS7500 || ARCH_RPC || ARCH_SHARK) diff -Naur linux-2.6.12.6.orig/drivers/ide/Makefile linux-2.6.12.6/drivers/ide/Makefile --- linux-2.6.12.6.orig/drivers/ide/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/ide/Makefile 2005-10-02 23:47:38.000000000 +0000 @@ -49,6 +49,6 @@ obj-$(CONFIG_BLK_DEV_IDETAPE) += ide-tape.o obj-$(CONFIG_BLK_DEV_IDEFLOPPY) += ide-floppy.o -obj-$(CONFIG_BLK_DEV_IDE) += legacy/ arm/ +obj-$(CONFIG_BLK_DEV_IDE) += legacy/ arm/ mips/ obj-$(CONFIG_BLK_DEV_HD) += legacy/ obj-$(CONFIG_ETRAX_IDE) += cris/ diff -Naur linux-2.6.12.6.orig/drivers/ide/ide.c linux-2.6.12.6/drivers/ide/ide.c --- linux-2.6.12.6.orig/drivers/ide/ide.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/ide/ide.c 2005-10-02 23:47:38.000000000 +0000 @@ -1843,6 +1843,12 @@ q40ide_init(); } #endif /* CONFIG_BLK_DEV_Q40IDE */ +#ifdef CONFIG_BLK_DEV_IDE_SWARM + { + extern void swarm_ide_probe(void); + swarm_ide_probe(); + } +#endif /* CONFIG_BLK_DEV_IDE_SWARM */ #ifdef CONFIG_BLK_DEV_BUDDHA { extern void buddha_init(void); diff -Naur linux-2.6.12.6.orig/drivers/ide/mips/Makefile linux-2.6.12.6/drivers/ide/mips/Makefile --- linux-2.6.12.6.orig/drivers/ide/mips/Makefile 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/ide/mips/Makefile 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,3 @@ +obj-$(CONFIG_BLK_DEV_IDE_SWARM) += swarm.o + +EXTRA_CFLAGS := -I../ diff -Naur linux-2.6.12.6.orig/drivers/ide/mips/swarm.c linux-2.6.12.6/drivers/ide/mips/swarm.c --- linux-2.6.12.6.orig/drivers/ide/mips/swarm.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/ide/mips/swarm.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2001, 2002, 2003 Broadcom Corporation + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * Copyright (C) 2004 MIPS Technologies, Inc. All rights reserved. + * Author: Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * Derived loosely from ide-pmac.c, so: + * Copyright (C) 1998 Paul Mackerras. + * Copyright (C) 1995-1998 Mark Lord + */ + +/* + * Boards with SiByte processors so far have supported IDE devices via + * the Generic Bus, PCI bus, and built-in PCMCIA interface. In all + * cases, byte-swapping must be avoided for these devices (whereas + * other PCI devices, for example, will require swapping). Any + * SiByte-targetted kernel including IDE support will include this + * file. Probing of a Generic Bus for an IDE device is controlled by + * the definition of "SIBYTE_HAVE_IDE", which is provided by + * for Broadcom boards. + */ + +#include +#include +#include +#include + +#include + +#include +#include +#include + +#define DRV_NAME "ide-swarm" + +static struct resource swarm_ide_resource = { + .name = "SWARM GenBus IDE", + .flags = IORESOURCE_MEM, +}; + +/* + * swarm_ide_probe - if the board header indicates the existence of + * Generic Bus IDE, allocate a HWIF for it. + */ +void __init swarm_ide_probe(void) +{ + ide_hwif_t *hwif; + u8 __iomem *base; + phys_t offset, size; + int i; + + if (!SIBYTE_HAVE_IDE) + return; + + /* Find an empty slot. */ + for (i = 0; i < MAX_HWIFS; i++) + if (!ide_hwifs[i].io_ports[IDE_DATA_OFFSET]) + break; + if (i >= MAX_HWIFS) { + printk(KERN_ERR DRV_NAME ": no free slot for interface\n"); + return; + } + hwif = ide_hwifs + i; + + base = ioremap(A_IO_EXT_BASE, 0x800); + offset = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_START_ADDR, IDE_CS)); + size = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_MULT_SIZE, IDE_CS)); + iounmap(base); + + offset = G_IO_START_ADDR(offset) << S_IO_ADDRBASE; + size = (G_IO_MULT_SIZE(size) + 1) << S_IO_REGSIZE; + if (offset < A_PHYS_GENBUS || offset >= A_PHYS_GENBUS_END) { + printk(KERN_INFO DRV_NAME + ": IDE interface at GenBus disabled\n"); + return; + } + + printk(KERN_INFO DRV_NAME ": IDE interface at GenBus slot %i\n", + IDE_CS); + + swarm_ide_resource.start = offset; + swarm_ide_resource.end = offset + size - 1; + if (request_resource(&iomem_resource, &swarm_ide_resource)) { + printk(KERN_ERR DRV_NAME + ": can't request I/O memory resource\n"); + return; + } + + base = ioremap(offset, size); + + /* Setup MMIO ops. */ + default_hwif_mmiops(hwif); + /* Prevent resource map manipulation. */ + hwif->mmio = 2; + hwif->noprobe = 0; + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) + hwif->hw.io_ports[i] = + (unsigned long)(base + ((0x1f0 + i) << 5)); + hwif->hw.io_ports[IDE_CONTROL_OFFSET] = + (unsigned long)(base + (0x3f6 << 5)); + hwif->hw.irq = K_INT_GB_IDE; + + memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports)); + hwif->irq = hwif->hw.irq; +} diff -Naur linux-2.6.12.6.orig/drivers/md/md.c linux-2.6.12.6/drivers/md/md.c --- linux-2.6.12.6.orig/drivers/md/md.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/md/md.c 2005-10-02 23:47:38.000000000 +0000 @@ -424,6 +424,7 @@ return ret; } +#if 0 static unsigned int calc_sb_csum(mdp_super_t * sb) { unsigned int disk_csum, csum; @@ -434,6 +435,23 @@ sb->sb_csum = disk_csum; return csum; } +#else +unsigned long calc_sb_csum(mdp_super_t *super) +{ + unsigned int oldcsum = super->sb_csum; + unsigned long long newcsum = 0; + unsigned long csum; + int i; + unsigned int *superc = (int*) super; + super->sb_csum = 0; + + for(i=0; i>32); + super->sb_csum = oldcsum; + return csum; +} +#endif /* diff -Naur linux-2.6.12.6.orig/drivers/media/video/Kconfig linux-2.6.12.6/drivers/media/video/Kconfig --- linux-2.6.12.6.orig/drivers/media/video/Kconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/media/video/Kconfig 2005-10-02 23:47:38.000000000 +0000 @@ -82,6 +82,14 @@ Check out for more information. +config VIDEO_SWARM_7114H + tristate "Philips SAA7114H for SiByte BCM91250A" + depends on SIBYTE_SWARM && VIDEO_DEV && I2C_ALGO_SIBYTE + help + Say Y or M to build the video4linux driver for the Philips + SAA7114H video decoder on Broadcom SWARM board (BCM91250A). + The decoder chip is on the BCM1250's "E2" 8-bit FIFO port. + config VIDEO_CPIA tristate "CPiA Video For Linux" depends on VIDEO_DEV diff -Naur linux-2.6.12.6.orig/drivers/media/video/Makefile linux-2.6.12.6/drivers/media/video/Makefile --- linux-2.6.12.6.orig/drivers/media/video/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/media/video/Makefile 2005-10-02 23:47:38.000000000 +0000 @@ -51,6 +51,9 @@ obj-$(CONFIG_VIDEO_BTCX) += btcx-risc.o obj-$(CONFIG_VIDEO_TVEEPROM) += tveeprom.o +obj-$(CONFIG_VIDEO_SWARM_7114H) += swarm_saa7114h.o +obj-$(CONFIG_TUNER_3036) += tuner-3036.o + obj-$(CONFIG_VIDEO_M32R_AR_M64278) += arv.o EXTRA_CFLAGS += -I$(srctree)/drivers/media/dvb/dvb-core diff -Naur linux-2.6.12.6.orig/drivers/media/video/swarm_saa7114h.c linux-2.6.12.6/drivers/media/video/swarm_saa7114h.c --- linux-2.6.12.6.orig/drivers/media/video/swarm_saa7114h.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/media/video/swarm_saa7114h.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,1691 @@ +/* + saa7114h - Philips SAA7114H video decoder driver + + Copyright (C) 2001,2002,2003 Broadcom Corporation + + From saa7111.c: + Copyright (C) 1998 Dave Perks + From cpia.c: + (C) Copyright 1999-2000 Peter Pregler + (C) Copyright 1999-2000 Scott J. Bertin + (C) Copyright 1999-2000 Johannes Erdfelt + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Important note: this driver is reasonably functional, and has been + * tested with the "camserv" v4l application. But it primarily a + * proof-of-concept, and example for setting up FIFO-mode. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#define SAA_BRIGHTNESS 0x0a +#define SAA_CONTRAST 0x0b +#define SAA_SATURATION 0x0c +#define SAA_HUE 0x0d + +#define DECODER_STATUS 0x1f +#define SLICER_STATUS_0 0x60 +#define SLICER_STATUS_1 0x61 +#define SLICER_STATUS_2 0x62 +#define SCALER_STATUS 0x8f + +#define NUM_FRAME 2 +#define MAX_HORIZ 720 +#define MAX_VERT 480 +#define MIN_HORIZ 180 +#define MIN_VERT 120 +#define MAX_PER_PIXEL 3 +#define MAX_FRAME_SIZE (MAX_HORIZ*MAX_VERT*MAX_PER_PIXEL) +#define MAX_MMAP_SIZE (PAGE_ALIGN(MAX_FRAME_SIZE*NUM_FRAME)) +#define RAW_PER_PIXEL 2 +#define RAW_LINE_PAD 8 +#define RAW_LINE_SIZE (((MAX_HORIZ*RAW_PER_PIXEL)+RAW_LINE_PAD+0x1f) & ~0x1f) +#define RAW_FRAME_SIZE (RAW_LINE_SIZE*MAX_VERT) + +#define NUM_DESCR 64 +#define INTR_PKT_CNT 8 + +/* Extensions to videodev.h IOCTL definitions */ +#define VIDIOREADREG _IOR('v', 50, int) +#define VIDIOWRITEREG _IOW('v', 50, int) +#define VIDIOGRABFRAME _IOR('v', 51, int) +#define VIDIOSHOWEAV _IOR('v', 52, int) + +#define IF_NAME "saa7114h" + +#define MAC2_CSR(r) (CKSEG1 + A_MAC_REGISTER(2, r)) +#define MAC2_DMARX0_CSR(r) (CKSEG1 + A_MAC_DMA_REGISTER(2, DMA_RX, 0, r)) + +/* Options */ +#define DMA_DEINTERLACE 1 +#define LAZY_READ 1 +#define NULL_DMA 0 + +/* Debug filters */ +#define DBG_NULL 0x0000 +#define DBG_IO 0x0001 +#define DBG_DESCR 0x0002 +#define DBG_INTR 0x0004 +#define DBG_CONVERT 0x0008 +#define DBG_FRAMING 0x0010 +#define DBG_REGISTER 0x0020 +#define DBG_CALL 0x0040 +#define DBG_FRAMING_LOUD 0x0080 + +/* XXXKW make this settable through /proc... */ +#define DEBUG_LVL (DBG_NULL) + +#if DEBUG_LVL +#define DBG(l, p) do { if (DEBUG_LVL & l) p; } while (0) +#else +#define DBG(l, p) +#endif + +/* ----------------------------------------------------------------------- */ + +enum { + FRAME_READY, /* Ready to grab into */ + FRAME_GRABBING, /* In the process of being grabbed into */ + FRAME_DONE, /* Finished grabbing, but not been synced yet */ + FRAME_UNUSED, /* Unused (belongs to driver, but can't be used) */ +}; + +struct saa_frame { + uint8_t *data; + uint8_t *pos; + int width; + int height; + uint32_t size; + volatile int state; + wait_queue_head_t read_wait; +}; + +typedef struct fifo_descr_s { + uint64_t descr_a; + uint64_t descr_b; +} fifo_descr_t; + +typedef unsigned long paddr_t; + +typedef struct fifo_s { + unsigned ringsz; + fifo_descr_t *descrtab; + fifo_descr_t *descrtab_end; + fifo_descr_t *next_descr; + paddr_t descrtab_phys; + void *dma_buf; /* DMA buffer */ +} fifo_t; + +struct saa7114h { + struct i2c_client *client; + struct video_device *vd; + struct video_window vw; + struct video_picture vp; + uint8_t reg[256]; + + fifo_t ff; + void *frame_buf; /* hold frames for the client */ + struct saa_frame frame[NUM_FRAME]; /* point into frame_buf */ + int hwframe; + int swframe; + + uint16_t depth; + uint16_t palette; + uint8_t bright; + uint8_t contrast; + uint8_t hue; + uint8_t sat; + + struct proc_dir_entry *proc_entry; + struct semaphore param_lock; + struct semaphore busy_lock; + + int dma_enable; + int opened; + int irq; + int interlaced; +}; + +static int saa7114h_probe(struct i2c_adapter *adap); +static int saa7114h_detach(struct i2c_client *device); + +struct i2c_driver i2c_driver_saa7114h = +{ + name: "saa7114h", /* name */ + id: I2C_DRIVERID_SAA7114H, /* ID */ + flags: I2C_DF_NOTIFY, /* XXXKW do I care? */ + attach_adapter: saa7114h_probe, + detach_client: saa7114h_detach +}; + +/* ----------------------------------------------------------------------- + * VM assist for MMAPed space + * ----------------------------------------------------------------------- */ + +/* Given PGD from the address space's page table, return the kernel + * virtual mapping of the physical memory mapped at ADR. + */ +static inline unsigned long uvirt_to_kva(pgd_t *pgd, unsigned long adr) +{ + unsigned long ret = 0UL; + pmd_t *pmd; + pte_t *ptep, pte; + + if (!pgd_none(*pgd)) { + pmd = pmd_offset(pgd, adr); + if (!pmd_none(*pmd)) { + ptep = pte_offset(pmd, adr); + pte = *ptep; + if (pte_present(pte)) { + ret = (unsigned long) page_address(pte_page(pte)); + ret |= (adr & (PAGE_SIZE-1)); + } + } + } + return ret; +} + +/* Here we want the physical address of the memory. + * This is used when initializing the contents of the + * area and marking the pages as reserved. + */ +static inline unsigned long kvirt_to_pa(unsigned long adr) +{ + unsigned long va, kva, ret; + + va = VMALLOC_VMADDR(adr); + kva = uvirt_to_kva(pgd_offset_k(va), va); + ret = __pa(kva); + return ret; +} + +static void *rvmalloc(unsigned long size) +{ + void *mem; + unsigned long adr, page; + + /* Round it off to PAGE_SIZE */ + size += (PAGE_SIZE - 1); + size &= ~(PAGE_SIZE - 1); + + mem = vmalloc_32(size); + if (!mem) + return NULL; + + memset(mem, 0, size); /* Clear the ram out, no junk to the user */ + adr = (unsigned long) mem; + while (size > 0) { + page = kvirt_to_pa(adr); + mem_map_reserve(virt_to_page(__va(page))); + adr += PAGE_SIZE; + if (size > PAGE_SIZE) + size -= PAGE_SIZE; + else + size = 0; + } + + return mem; +} + +static void rvfree(void *mem, unsigned long size) +{ + unsigned long adr, page; + + if (!mem) + return; + + size += (PAGE_SIZE - 1); + size &= ~(PAGE_SIZE - 1); + + adr = (unsigned long) mem; + while (size > 0) { + page = kvirt_to_pa(adr); + mem_map_unreserve(virt_to_page(__va(page))); + adr += PAGE_SIZE; + if (size > PAGE_SIZE) + size -= PAGE_SIZE; + else + size = 0; + } + vfree(mem); +} + +/* ----------------------------------------------------------------------- + * Control interface (i2c) + * ----------------------------------------------------------------------- */ + +static int saa7114h_reg_read(struct saa7114h *dev, unsigned char subaddr) +{ + return i2c_smbus_read_byte_data(dev->client, subaddr); +} + +static int saa7114h_reg_write(struct saa7114h *dev, unsigned char subaddr, int data) +{ + return i2c_smbus_write_byte_data(dev->client, subaddr, data & 0xff); +} + +static int saa7114h_reg_init(struct saa7114h *dev, unsigned const char *data, unsigned int len) +{ + int rc = 0; + int val; + + while (len && !rc) { + dev->reg[data[0]] = data[1]; + rc = saa7114h_reg_write(dev, data[0], data[1]); + if (!rc && (data[0] != 0)) { + val = saa7114h_reg_read(dev, data[0]); + if ((val < 0) || (val != data[1])) { + printk(KERN_ERR + IF_NAME ": init readback mismatch reg %02x = %02x (should be %02x)\n", + data[0], val, data[1]); + } + } + len -= 2; + data += 2; + } + return rc; +} + +/* ----------------------------------------------------------------------- + * /proc interface + * ----------------------------------------------------------------------- */ + +#ifdef CONFIG_PROC_FS +static struct proc_dir_entry *saa7114h_proc_root=NULL; + +static int decoder_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + char *out = page; + int len, status; + struct saa7114h *decoder = data; + + out += sprintf(out, " SWARM saa7114h\n------------------\n"); + status = saa7114h_reg_read(decoder, DECODER_STATUS); + out += sprintf(out, " Decoder status = %02x\n", status); + if (status & 0x80) + out += sprintf(out, " interlaced\n"); + if (status & 0x40) + out += sprintf(out, " not locked\n"); + if (status & 0x02) + out += sprintf(out, " Macrovision detected\n"); + if (status & 0x01) + out += sprintf(out, " color\n"); + out += sprintf(out, " Brightness = %02x\n", decoder->bright); + out += sprintf(out, " Contrast = %02x\n", decoder->contrast); + out += sprintf(out, " Saturation = %02x\n", decoder->sat); + out += sprintf(out, " Hue = %02x\n\n", decoder->hue); + + out += sprintf(out, " Scaler status = %02x\n", + (int)saa7114h_reg_read(decoder, SCALER_STATUS)); + + len = out - page; + len -= off; + if (len < count) { + *eof = 1; + if (len <= 0) return 0; + } else + len = count; + + *start = page + off; + return len; +} + +static int decoder_write_proc(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + struct saa7114h *d = data; + int retval; + unsigned int cmd, reg, reg_val; + + if (down_interruptible(&d->param_lock)) + return -ERESTARTSYS; + +#define VALUE \ + ({ \ + char *_p; \ + unsigned long int _ret; \ + while (count && isspace(*buffer)) { \ + buffer++; \ + count--; \ + } \ + _ret = simple_strtoul(buffer, &_p, 16); \ + if (_p == buffer) \ + retval = -EINVAL; \ + else { \ + count -= _p - buffer; \ + buffer = _p; \ + } \ + _ret; \ + }) + + retval = 0; + while (count && !retval) { + cmd = VALUE; + if (retval) + break; + switch (cmd) { + case 1: + reg = VALUE; + if (retval) + break; + reg_val = VALUE; + if (retval) + break; + printk(IF_NAME ": write reg %x <- %x\n", reg, reg_val); + if (saa7114h_reg_write(d, reg, reg_val) == -1) + retval = -EINVAL; + break; + case 2: + reg = VALUE; + if (retval) + break; + reg_val = saa7114h_reg_read(d, reg); + if (reg_val == -1) + retval = -EINVAL; + else + printk(IF_NAME ": read reg %x -> %x\n", reg, reg_val); + break; + default: + break; + } + } + up(&d->param_lock); + + return retval; +} + +static void create_proc_decoder(struct saa7114h *decoder) +{ + char name[8]; + struct proc_dir_entry *ent; + + if (!saa7114h_proc_root || !decoder) + return; + + sprintf(name, "video%d", decoder->vd->minor); + + ent = create_proc_entry(name, S_IFREG|S_IRUGO|S_IWUSR, saa7114h_proc_root); + if (!ent) { + printk(KERN_INFO IF_NAME ": Unable to initialize /proc/saa7114h/%s\n", name); + return; + } + + ent->data = decoder; + ent->read_proc = decoder_read_proc; + ent->write_proc = decoder_write_proc; + ent->size = 3626; /* XXXKW ??? */ + decoder->proc_entry = ent; +} + +static void destroy_proc_decoder(struct saa7114h *decoder) +{ + char name[7]; + + if (!decoder || !decoder->proc_entry) + return; + + sprintf(name, "video%d", decoder->vd->minor); + remove_proc_entry(name, saa7114h_proc_root); + decoder->proc_entry = NULL; +} + +static void proc_saa7114h_create(void) +{ + saa7114h_proc_root = create_proc_entry("saa7114h", S_IFDIR, 0); + + if (saa7114h_proc_root) + saa7114h_proc_root->owner = THIS_MODULE; + else + printk(KERN_INFO IF_NAME ": Unable to initialize /proc/saa7114h\n"); +} + +static void proc_saa7114h_destroy(void) +{ + remove_proc_entry("saa7114h", 0); +} +#endif /* CONFIG_PROC_FS */ + + +/* ----------------------------------------------------------------------- + * Initialization + * ----------------------------------------------------------------------- */ + +static int dma_setup(struct saa7114h *d) +{ + int i; + void *curbuf; + + /* Reset the port */ + __raw_writeq(M_MAC_PORT_RESET, MAC2_CSR(R_MAC_ENABLE)); + __raw_readq(MAC2_CSR(R_MAC_ENABLE)); + + /* Zero everything out, disable filters */ + __raw_writeq(0, MAC2_CSR(R_MAC_TXD_CTL)); + __raw_writeq(M_MAC_ALLPKT_EN, MAC2_CSR(R_MAC_ADFILTER_CFG)); + __raw_writeq(V_MAC_RX_RD_THRSH(4) | V_MAC_RX_RL_THRSH(4), + MAC2_CSR(R_MAC_THRSH_CFG)); + for (i=0; iff.descrtab = kmalloc(NUM_DESCR * sizeof(fifo_descr_t), GFP_KERNEL); + d->ff.descrtab_phys = __pa(d->ff.descrtab); + d->ff.descrtab_end = d->ff.descrtab + NUM_DESCR; + d->ff.next_descr = d->ff.descrtab; + d->ff.ringsz = NUM_DESCR; +#if 0 + /* XXXKW this won't work because the physical may not be + contiguous; how do I handle a bigger alloc then? */ + d->ff.dma_buf = rvmalloc(RAW_LINE_SIZE*NUM_DESCR); + printk(KERN_DEBUG IF_NAME ": DMA buffer allocated (%p)\n", + d->ff.dma_buf); +#else + d->ff.dma_buf = kmalloc(RAW_LINE_SIZE*NUM_DESCR, GFP_KERNEL); +#endif + if (!d->ff.dma_buf) { + printk(KERN_ERR IF_NAME ": couldn't allocate DMA buffer\n"); + return -ENOMEM; + } + memset(d->ff.dma_buf, 0, RAW_LINE_SIZE*NUM_DESCR); + + for (i=0, curbuf=d->ff.dma_buf; iff.ringsz; i++, curbuf+=RAW_LINE_SIZE) { + d->ff.descrtab[i].descr_a = (__pa(curbuf) | + V_DMA_DSCRA_A_SIZE(RAW_LINE_SIZE >> 5)); + d->ff.descrtab[i].descr_b = 0; + } + + __raw_writeq(V_DMA_INT_PKTCNT(INTR_PKT_CNT) | M_DMA_EOP_INT_EN | + V_DMA_RINGSZ(d->ff.ringsz) | M_DMA_TDX_EN, + MAC2_DMARX0_CSR(R_MAC_DMA_CONFIG0)); + __raw_writeq(M_DMA_L2CA, MAC2_DMARX0_CSR(R_MAC_DMA_CONFIG1)); + __raw_writeq(d->ff.descrtab_phys, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_BASE)); + + /* Enable interrupts and DMA */ + __raw_writeq(M_MAC_INT_EOP_COUNT<0xffffff)?0xff0000:(((x)<=0xffff)?0:(x)&0xff0000))>>16) + +static void yuvconvert_inplace(uint8_t *data, uint32_t in_uyvy, int out_fmt, int mmap) +{ + int y, u, v, r, g, b, y1; + uint8_t *src, *dst; + + if (out_fmt == VIDEO_PALETTE_RGB24) { + src = (uint8_t *)((int)data + in_uyvy); + dst = (uint8_t *)((int)data + in_uyvy + (in_uyvy >> 1)); + DBG(DBG_CONVERT, printk(KERN_DEBUG "inplace: %p %p %p\n", data, src, dst)); + while (src > data) { + if ((int)(src-data) < 4) + break; + //printk("freaky %p %p\n", src, data); + y1 = (*(--src) - 16) * 76310; + v = *(--src) - 128; + y = (*(--src) - 16) * 76310; + u = *(--src) - 128; + r = 104635 * v; + g = -25690 * u + -53294 * v; + b = 132278 * u; + /* XXXKW what on earth is up with mmap? */ + if (mmap) { + *(--dst) = LIMIT(r+y1); + *(--dst) = LIMIT(g+y1); + *(--dst) = LIMIT(b+y1); + *(--dst) = LIMIT(r+y); + *(--dst) = LIMIT(g+y); + *(--dst) = LIMIT(b+y); + } else { + *(--dst) = LIMIT(b+y1); + *(--dst) = LIMIT(g+y1); + *(--dst) = LIMIT(r+y1); + *(--dst) = LIMIT(b+y); + *(--dst) = LIMIT(g+y); + *(--dst) = LIMIT(r+y); + } + } + } +} + +static int saa7114h_get_cparams(struct saa7114h *decoder) +{ + /* XXX check for error code */ + decoder->bright = saa7114h_reg_read(decoder, SAA_BRIGHTNESS); + decoder->contrast = saa7114h_reg_read(decoder, SAA_CONTRAST); + decoder->sat = saa7114h_reg_read(decoder, SAA_SATURATION); + decoder->hue = saa7114h_reg_read(decoder, SAA_HUE); + + decoder->vp.brightness = (uint16_t)decoder->bright << 8; + decoder->vp.contrast = (uint16_t)decoder->contrast << 9; + decoder->vp.colour = decoder->sat << 9; + decoder->vp.hue = ((int16_t)decoder->hue + 128) << 8; + return 0; +} + +static int saa7114h_set_cparams(struct saa7114h *decoder) +{ + decoder->bright = decoder->vp.brightness >> 8; + decoder->contrast = decoder->vp.contrast >> 9; + decoder->sat = decoder->vp.colour >> 9; + decoder->hue = (uint8_t)((int8_t)(decoder->vp.hue >> 8) - 128); + + return (saa7114h_reg_write(decoder, SAA_BRIGHTNESS, decoder->bright) || + saa7114h_reg_write(decoder, SAA_CONTRAST, decoder->contrast) || + saa7114h_reg_write(decoder, SAA_SATURATION, decoder->sat) || + saa7114h_reg_write(decoder, SAA_HUE, decoder->hue)); +} + +/* ----------------------------------------------------------------------- + * Custom IOCTL support + * ----------------------------------------------------------------------- */ + +unsigned char eav[625][2]; +static int grab_frame(struct saa7114h *d, void *user_buf, int print_eav) +{ + int cur_idx = 0; + int to_go = 625; + int delta; + int i, len, eav_val, sav_val; + int started = 0; + uint8_t *buf; + fifo_descr_t *cur_d; + int swptr = d->ff.next_descr - d->ff.descrtab; + int hwptr; + + DBG(DBG_CALL, printk(IF_NAME ": grabbing frame\n")); + + /* Check for Macrovision -- if it's on, DMA won't happen */ + if (saa7114h_reg_read(d, DECODER_STATUS) & 0x2) + return -EACCES; + + __raw_writeq(d->ff.ringsz, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT)); + do { + hwptr = (unsigned) (((__raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_CUR_DSCRADDR)) & + M_DMA_CURDSCR_ADDR) - + d->ff.descrtab_phys) / + sizeof(fifo_descr_t)); + delta = (hwptr + d->ff.ringsz - swptr) % d->ff.ringsz; + + if (delta == 0) { +#if 0 + uint64_t val = __raw_readq(MAC2_DMARX0_CSR(R_MAC_STATUS)); + printk("mac status: %08x%08x\n", + (u32)(val >> 32), (u32)(val&0xffffffff)); +#endif + } + + for (i=0; iff.next_descr; + if (++d->ff.next_descr == d->ff.descrtab_end) + d->ff.next_descr = d->ff.descrtab; + + if (!(cur_d->descr_a & M_DMA_ETHRX_SOP)) { + printk("bogus RX\n"); + continue; + } + cur_d->descr_a &= ~M_DMA_ETHRX_SOP; + len = G_DMA_DSCRB_PKT_SIZE(cur_d->descr_b); + buf = (uint8_t *)__va(cur_d->descr_a & M_DMA_DSCRA_A_ADDR); + if (len != (d->vw.width*RAW_PER_PIXEL)+RAW_LINE_PAD) { + printk("funny size %d\n", len); + continue; + } + eav_val = buf[1]; + sav_val = buf[5]; + if (eav_val == 0xf1) { /* end of field 2, V-blank */ + if (started) { + started = 0; + delta = to_go = 0; + /* just let DMA finish in background */ + } else { + started = 1; + } + } + if (started) { + eav[cur_idx][0] = eav_val; + eav[cur_idx++][1] = sav_val; + if (copy_to_user(user_buf, &buf[6], 1440)) + return -EFAULT; + user_buf += 1440; + } + } + swptr = hwptr; + if (delta) { + if (started) + to_go -= delta; + if (delta > to_go) + delta = to_go; + __raw_writeq(delta, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT)); + } + } while (to_go); + + if (print_eav) { + for (i=0; iff.next_descr - d->ff.descrtab; + int hwptr; + + status_val = __raw_readq(MAC2_CSR(R_MAC_STATUS)); + + /* Process finished decsriptors */ + hwptr = (unsigned) (((__raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_CUR_DSCRADDR)) & + M_DMA_CURDSCR_ADDR) - d->ff.descrtab_phys) / + sizeof(fifo_descr_t)); + delta = (hwptr + d->ff.ringsz - swptr) % d->ff.ringsz; + if (!delta) { + if (status_val & M_MAC_INT_EOP_SEEN<ff.ringsz; + } else { + /* XXXKW why would this happen? */ + return; + } + } + + for (i=0; iff.next_descr; + if (++d->ff.next_descr == d->ff.descrtab_end) + d->ff.next_descr = d->ff.descrtab; + + if (!(cur_d->descr_a & M_DMA_ETHRX_SOP)) { + printk(KERN_DEBUG "bogus RX\n"); + continue; + } + cur_d->descr_a &= ~M_DMA_ETHRX_SOP; + if (!d->dma_enable) + continue; + + len = G_DMA_DSCRB_PKT_SIZE(cur_d->descr_b); + buf = (uint8_t *)__va(cur_d->descr_a & M_DMA_DSCRA_A_ADDR); + if (len != (d->vw.width*RAW_PER_PIXEL)+RAW_LINE_PAD) { + printk(KERN_DEBUG "funny size %d\n", len); +// continue; + } + len -= RAW_LINE_PAD; + eav_val = buf[1]; + DBG(DBG_FRAMING_LOUD, + printk(KERN_DEBUG "eav: %02x len: %d\n", eav_val, len)); + if (eav_val == 0xf1) { /* end of field 2, V-blank: start-of-frame */ + switch (d->frame[d->hwframe].state) { + case FRAME_UNUSED: + DBG(DBG_FRAMING, + printk(KERN_ERR "capture to unused frame %d\n", + d->hwframe)); + break; + case FRAME_READY: + DBG(DBG_FRAMING, + printk(KERN_DEBUG "frame started %d\n", + d->hwframe)); + /* start this frame (skip eav/sav) */ + memcpy(d->frame[d->hwframe].pos, &buf[6], len); +#if DMA_DEINTERLACE + if (!d->interlaced) + memcpy(d->frame[d->hwframe].pos-len, &buf[6], len); + d->frame[d->hwframe].pos += len*2; +#else + d->frame[d->hwframe].pos += len; +#endif + d->frame[d->hwframe].state = FRAME_GRABBING; + /* XXXKW check pos overflow */ + break; + case FRAME_GRABBING: + /* kick over to new frame */ + d->frame[d->hwframe].size = d->frame[d->hwframe].pos - + d->frame[d->hwframe].data; + d->frame[d->hwframe].state = FRAME_DONE; + DBG(DBG_FRAMING, + printk(KERN_DEBUG "frame finished %d\n", + d->frame[d->hwframe].size)); + /* wake up a waiting reader */ + DBG(DBG_IO, printk(KERN_DEBUG "wakeup\n")); + wake_up(&d->frame[d->hwframe].read_wait); + d->hwframe = (d->hwframe + 1) % NUM_FRAME; + if (d->frame[d->hwframe].state == FRAME_READY) { + /* start this frame */ + DBG(DBG_FRAMING, + printk(KERN_DEBUG "frame bumped %d\n", + d->hwframe)); + memcpy(d->frame[d->hwframe].pos, &buf[6], len); +#if DMA_DEINTERLACE + if (!d->interlaced) + memcpy(d->frame[d->hwframe].pos-len, &buf[6], len); + d->frame[d->hwframe].pos += len*2; +#else + d->frame[d->hwframe].pos += len; +#endif + d->frame[d->hwframe].state = FRAME_GRABBING; + } else { + /* drop on the floor, + note that we've stopped DMA'ing */ + DBG(DBG_FRAMING, + printk(KERN_DEBUG "frame capture halted\n")); + d->dma_enable = 0; + } + break; + case FRAME_DONE: + /* drop on the floor (must be waiting for sw) */ + DBG(DBG_FRAMING, + printk(KERN_DEBUG "frame capture halted\n")); + d->dma_enable = 0; + break; + } + } else { + switch (d->frame[d->hwframe].state) { + case FRAME_UNUSED: + DBG(DBG_FRAMING, + printk(KERN_ERR "capture to unused frame %d\n", + d->hwframe)); + break; + case FRAME_READY: + /* drop on the floor (must have dropped something) */ + DBG(DBG_FRAMING_LOUD, + printk(KERN_DEBUG "missed SOF\n")); + break; + case FRAME_DONE: + /* drop on the floor (must be waiting for sw) */ + DBG(DBG_FRAMING, + printk(KERN_DEBUG "frame overflow\n")); + d->dma_enable = 0; + break; + case FRAME_GRABBING: +#if DMA_DEINTERLACE + if (eav_val == 0xb6) { + d->frame[d->hwframe].pos = d->frame[d->hwframe].data; + } + memcpy(d->frame[d->hwframe].pos, &buf[6], len); + if (!d->interlaced) + memcpy(d->frame[d->hwframe].pos-len, &buf[6], len); + d->frame[d->hwframe].pos += len*2; +#else + memcpy(d->frame[d->hwframe].pos, &buf[6], len); + d->frame[d->hwframe].pos += len; +#endif + /* XXXKW check pos overflow */ + break; + } + } + } + + if (d->dma_enable) { + __raw_writeq(delta, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT)); + DBG(DBG_DESCR, + printk(KERN_DEBUG IF_NAME ": interrupt adds %d -> %d descrs\n", + delta, (int)__raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT)))); + } +} + +/* ----------------------------------------------------------------------- + * /dev/video interface + * ----------------------------------------------------------------------- */ + +static int saa7114h_open(struct video_device *vd, int nb) +{ + struct saa7114h *d = vd->priv; + uint32_t status; + + if (!d || d->opened) + return -EBUSY; + + d->opened = 1; + DBG(DBG_CALL, printk(KERN_DEBUG IF_NAME ": open\n")); + + /* XXKW Should check this periodically!? */ + status = saa7114h_reg_read(d, DECODER_STATUS); + d->interlaced = ((status & 0x80) != 0); + +#if !NULL_DMA + if (d->dma_enable) { + printk(IF_NAME ": open found DMA on?!\n"); +#if LAZY_READ + } +#else + } else { + int descr; + d->dma_enable = 1; + DBG(DBG_DESCR, printk(IF_NAME ": open enabling DMA\n")); + /* Force capture to start into frame buffer 0 */ + descr = __raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT)); + DBG(DBG_DESCR, + printk(IF_NAME ": open adds %d -> %d descrs\n", + d->ff.ringsz-desc, descr)); + __raw_writeq(d->ff.ringsz-descr, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT)); + } +#endif +#endif + + return 0; +} + +static void saa7114h_release(struct video_device *vd) +{ + struct saa7114h *d = vd->priv; + + DBG(DBG_CALL, printk(KERN_DEBUG IF_NAME ": release\n")); + d->opened = 0; + d->dma_enable = 0; + + /* XXXKW do a clean drain of outstanding DMAs? toss leftover + buffer contents to avoid stale pictures? */ + + return; +} + +static long saa7114h_read(struct video_device *vd, char *buf, + unsigned long count, int noblock) +{ + struct saa7114h *d = vd->priv; + int descr, status; + + if (!d) + return -ENODEV; + + /* XXKW Should check this periodically!? */ + status = saa7114h_reg_read(d, DECODER_STATUS); +// d->interlaced = ((status & 0x80) != 0); + +#if !NULL_DMA +#if LAZY_READ + if (!d->dma_enable) { + DBG(DBG_DESCR, printk(KERN_DEBUG IF_NAME ": enabling DMA\n")); + /* Give the buffer to the DMA engine (force ptr reset) */ + d->swframe = d->hwframe; + d->frame[d->swframe].state = FRAME_READY; +#if DMA_DEINTERLACE + d->frame[d->swframe].pos = d->frame[d->swframe].data+d->vw.width*RAW_PER_PIXEL; +#else + d->frame[d->swframe].pos = d->frame[d->swframe].data; +#endif + /* Fire up the DMA engine again if it stopped */ + d->dma_enable = 1; + descr = __raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT)); + __raw_writeq(d->ff.ringsz-descr, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT)); + } +#endif +#endif + + /* XXXKW mmap/read mixture could break the swframe sequence */ + + if (d->frame[d->swframe].state != FRAME_DONE) { + if (noblock) + return -EAGAIN; + else { + DBG(DBG_IO, + printk(KERN_DEBUG IF_NAME ": sleeping for frame\n")); + interruptible_sleep_on(&d->frame[d->swframe].read_wait); + DBG(DBG_IO, + printk(KERN_DEBUG IF_NAME ": awakened\n")); + if (signal_pending(current)) + return -ERESTARTSYS; + } + } + + if (count < d->frame[d->swframe].size) + return -EFAULT; + + count = d->frame[d->swframe].size; + yuvconvert_inplace(d->frame[d->swframe].data, d->frame[d->swframe].size, d->vp.palette, 0); + copy_to_user(buf, d->frame[d->swframe].data, d->frame[d->swframe].size); + d->swframe = (d->swframe + 1) % NUM_FRAME; + /* XXXKW doesn't do format conversion!!! */ +#if !NULL_DMA +#if !LAZY_READ + /* XXXKW Fire up the DMA engine again if it stopped ??? */ + if (!d->dma_enable) { + DBG(DBG_DESCR, printk(KERN_DEBUG IF_NAME ": enabling DMA\n")); + /* Fire up the DMA engine again if it stopped */ + d->dma_enable = 1; + descr = __raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT)); + __raw_writeq(d->ff.ringsz-descr, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT)); + } +#endif +#endif + + return count; +} + +static int saa7114h_ioctl(struct video_device *vd, unsigned int cmd, void *arg) +{ + struct saa7114h *d = vd->priv; + int val, reg, retval = 0; + + if (!d) + return -ENODEV; + + switch (cmd) { + case VIDIOCGCHAN: + { + struct video_channel v; + + if (copy_from_user(&v, arg, sizeof(v))) { + retval = -EFAULT; + break; + } + if (v.channel != 0) { + retval = -EINVAL; + break; + } + + v.channel = 0; + strcpy(v.name, "Camera"); + v.tuners = 0; + v.flags = 0; + v.type = VIDEO_TYPE_CAMERA; + v.norm = 0; + + if (copy_to_user(arg, &v, sizeof(v))) + retval = -EFAULT; + break; + } + + case VIDIOCSCHAN: + { + int v; + + if (copy_from_user(&v, arg, sizeof(v))) + retval = -EFAULT; + + if (retval == 0 && v != 0) + retval = -EINVAL; + + break; + } + + case VIDIOCGCAP: + { + struct video_capability b; + + strcpy(b.name, "Philips SAA7114H Decoder"); + b.type = VID_TYPE_CAPTURE /* | VID_TYPE_TELETEXT */ | VID_TYPE_SCALES; + b.channels = 1; + b.audios = 0; + b.maxwidth = MAX_HORIZ; + b.maxheight = MAX_VERT; + /* XXXKW find real values */ + b.minwidth = 48; + b.minheight = 48; + + if (copy_to_user(arg, &b, sizeof(b))) + retval = -EFAULT; + + break; + } + + /* image properties */ + case VIDIOCGPICT: + if (copy_to_user(arg, &d->vp, sizeof(struct video_picture))) + retval = -EFAULT; + break; + + case VIDIOCSPICT: + { + struct video_picture vp; + + /* copy_from_user */ + if (copy_from_user(&vp, arg, sizeof(vp))) { + retval = -EFAULT; + break; + } + + down(&d->param_lock); + /* brightness, colour, contrast need not check 0-65535 */ + memcpy( &d->vp, &vp, sizeof(vp) ); + /* update cam->params.colourParams */ + saa7114h_set_cparams(d); + up(&d->param_lock); + break; + } + + /* get/set capture window */ + case VIDIOCGWIN: + if (copy_to_user(arg, &d->vw, sizeof(struct video_window))) + retval = -EFAULT; + break; + + case VIDIOCSWIN: + { + /* copy_from_user, check validity, copy to internal structure */ + struct video_window vw; + if (copy_from_user(&vw, arg, sizeof(vw))) { + retval = -EFAULT; + break; + } + + if (vw.clipcount != 0) { /* clipping not supported */ + retval = -EINVAL; + break; + } + if (vw.clips != NULL) { /* clipping not supported */ + retval = -EINVAL; + break; + } + if ((vw.width > MAX_HORIZ || vw.width < MIN_HORIZ) || + (vw.height > MAX_VERT || vw.height < MIN_VERT)) { + retval = -EINVAL; + break; + } + + /* we set the video window to something smaller or equal to what + * is requested by the user??? + */ + down(&d->param_lock); + if (vw.width != d->vw.width || vw.height != d->vw.height) { + uint32_t scale_factor; + /* XXXKW base percentage on input stream, not MAX? */ + + /* Assert scaler reset */ + saa7114h_reg_write(d, 0x88, 0x98); + + /* Vertical scaling */ + scale_factor = (MAX_VERT*1024) / vw.height; + saa7114h_reg_write(d, 0x9e, vw.height & 0xff); + saa7114h_reg_write(d, 0x9f, (vw.height >> 8) & 0xf); + saa7114h_reg_write(d, 0xb0, scale_factor & 0xff); + saa7114h_reg_write(d, 0xb1, (scale_factor >> 8) & 0xff); + saa7114h_reg_write(d, 0xb2, scale_factor & 0xff); + saa7114h_reg_write(d, 0xb3, (scale_factor >> 8) & 0xff); + /* Horizontal scaling */ + scale_factor = (MAX_HORIZ*1024) / vw.width; + saa7114h_reg_write(d, 0x9c, vw.width & 0xff); + saa7114h_reg_write(d, 0x9d, (vw.width >> 8) & 0xf); + saa7114h_reg_write(d, 0xa8, scale_factor & 0xff); + saa7114h_reg_write(d, 0xa9, (scale_factor >> 8) & 0xff); + saa7114h_reg_write(d, 0xac, (scale_factor >> 1) & 0xff); + saa7114h_reg_write(d, 0xad, (scale_factor >> 9) & 0xff); +#if 0 + /* prescaler + saa7114h_reg_write(d, 0xa0, 2); + saa7114h_reg_write(d, 0xa1, 1); + saa7114h_reg_write(d, 0xa2, 1); + */ +#endif + + /* Release scaler reset */ + saa7114h_reg_write(d, 0x88, 0xb8); + d->vw.width = vw.width; + d->vw.height = vw.height; + } + up(&d->param_lock); + break; + } + + /* mmap interface */ + case VIDIOCGMBUF: + { + struct video_mbuf vm; + int i; + + memset(&vm, 0, sizeof(vm)); + vm.size = MAX_FRAME_SIZE*NUM_FRAME; + vm.frames = NUM_FRAME; + for (i = 0; i < NUM_FRAME; i++) + vm.offsets[i] = MAX_FRAME_SIZE * i; + + if (copy_to_user((void *)arg, (void *)&vm, sizeof(vm))) + retval = -EFAULT; + + break; + } + + case VIDIOCMCAPTURE: + { + struct video_mmap vm; + int descr, status; + + if (copy_from_user((void *)&vm, (void *)arg, sizeof(vm))) { + retval = -EFAULT; + break; + } + if (vm.frame<0||vm.frame>NUM_FRAME) { + retval = -EINVAL; + break; + } + + DBG(DBG_CALL, + printk(KERN_DEBUG IF_NAME ":ioctl MCAPTURE %d\n", vm.frame)); + + d->vp.palette = vm.format; + /* XXXKW set depth? */ + /* XXXKW match/update for vm.width, vm.height */ + + /* XXKW Should check this periodically!? */ + status = saa7114h_reg_read(d, DECODER_STATUS); +// d->interlaced = ((status & 0x80) != 0); + + /* Give the buffer to the DMA engine */ + /* XXXKW vm.frame vs d->swframe!! mmap/read mismatch */ +#if DMA_DEINTERLACE + d->frame[vm.frame].pos = d->frame[vm.frame].data + d->vw.width*RAW_PER_PIXEL; +#else + d->frame[vm.frame].pos = d->frame[vm.frame].data; +#endif +#if !NULL_DMA + d->frame[vm.frame].state = FRAME_READY; + /* Fire up the DMA engine again if it stopped */ + if (!d->dma_enable) { + d->dma_enable = 1; + d->hwframe = d->swframe = vm.frame; + descr = __raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT)); + DBG(DBG_DESCR, + printk(KERN_DEBUG IF_NAME ": capture adds %d -> %d descrs\n", + d->ff.ringsz-descr, descr)); + __raw_writeq(d->ff.ringsz-descr, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT)); + } +#endif + break; + } + + case VIDIOCSYNC: + { + int frame; + + if (copy_from_user((void *)&frame, arg, sizeof(int))) { + retval = -EFAULT; + break; + } + + if (frame<0 || frame >= NUM_FRAME) { + retval = -EINVAL; + break; + } + + DBG(DBG_CALL, printk(KERN_DEBUG IF_NAME ":ioctl CSYNC %d\n", frame)); + + switch (d->frame[frame].state) { + case FRAME_UNUSED: + DBG(DBG_IO, + printk(KERN_ERR IF_NAME ":sync to unused frame %d\n", frame)); + retval = -EINVAL; + break; + + case FRAME_READY: + case FRAME_GRABBING: + DBG(DBG_IO, + printk(KERN_DEBUG IF_NAME ": sleeping for frame %d\n", frame)); + interruptible_sleep_on(&d->frame[frame].read_wait); + DBG(DBG_IO, + printk(KERN_DEBUG IF_NAME ": awakened\n")); + if (signal_pending(current)) + return -ERESTARTSYS; + case FRAME_DONE: +#if !NULL_DMA + yuvconvert_inplace(d->frame[frame].data, + d->frame[frame].size, + d->vp.palette, 1); + d->frame[frame].state = FRAME_UNUSED; +#endif + DBG(DBG_IO, + printk(KERN_DEBUG IF_NAME ": sync finished %d\n", + frame)); + break; + } + break; + } + + case VIDIOREADREG: + reg = *(int *)arg; + DBG(DBG_REGISTER, printk(KERN_DEBUG IF_NAME ": read of %02x\n", reg)); + if ((reg > 0xEF) || (reg < 0)) + return -EINVAL; + val = saa7114h_reg_read((struct saa7114h *)vd->priv, reg); + if (val == -1) + return -EIO; + *(int *)arg = val; + break; + case VIDIOWRITEREG: + if (copy_from_user(®, arg, sizeof(int)) || + copy_from_user(&val, arg+sizeof(int), sizeof(int))) + return -EFAULT; + DBG(DBG_REGISTER, printk(KERN_DEBUG IF_NAME ": write of %02x <- %02x\n", reg, val)); + if ((reg > 0xEF) || (reg < 0)) + return -EINVAL; + val = saa7114h_reg_write((struct saa7114h *)vd->priv, reg, val); + if (val == -1) + return -EIO; + break; + case VIDIOGRABFRAME: + return grab_frame((struct saa7114h *)vd->priv, arg, 0); + case VIDIOSHOWEAV: + return grab_frame((struct saa7114h *)vd->priv, arg, 1); + default: + retval = -EINVAL; + break; + } + + return retval; +} + +static int saa7114h_mmap(struct video_device *vd, const char *adr, + unsigned long size) +{ + struct saa7114h *d = vd->priv; + unsigned long start = (unsigned long)adr; + unsigned long page, pos; + + if (!d) + return -ENODEV; + + if (size > MAX_MMAP_SIZE) { + printk("mmap: bad size %lu > %lu\n", size, MAX_MMAP_SIZE); + return -EINVAL; + } + + /* make this _really_ smp-safe */ + if (down_interruptible(&d->busy_lock)) + return -EINTR; + + pos = (unsigned long)(d->frame_buf); + while (size > 0) { + page = kvirt_to_pa(pos); + if (remap_page_range(start, page, PAGE_SIZE, PAGE_SHARED)) { + up(&d->busy_lock); + return -EAGAIN; + } + start += PAGE_SIZE; + pos += PAGE_SIZE; + if (size > PAGE_SIZE) + size -= PAGE_SIZE; + else + size = 0; + } + up(&d->busy_lock); + + return 0; +} + +/* ----------------------------------------------------------------------- + * Device probing and initialization + * ----------------------------------------------------------------------- */ + +/* Default values to program into SAA7114H */ +static const unsigned char reg_init[] = { + 0x00, 0x00, /* 00 - ID byte */ + + /*front end */ + 0x01, 0x08, /* 01 - Horizontal increment -> recommended delay */ + 0x02, 0xC4, /* 02 - AI Control 1 (CVBS AI23) */ + 0x03, 0x10, /* 03 - AI Control 2 */ + 0x04, 0x90, /* 04 - AI Control 3 (Gain ch 1) */ + 0x05, 0x90, /* 05 - AI Control 4 (Gain ch 2) */ + + /* decoder */ + 0x06, 0xEB, /* 06 - Horiz sync start */ + 0x07, 0xE0, /* 07 - Horiz sync stop */ + 0x08, 0x98, /* 08 - Sync control */ + 0x09, 0x40, /* 09 - L Control */ + 0x0a, 0x80, /* 0a - L Brightness */ + 0x0b, 0x44, /* 0b - L Contrast */ + 0x0c, 0x40, /* 0c - C Saturation */ + 0x0d, 0x00, /* 0d - C Hue */ + 0x0e, 0x89, /* 0e - C Control 1 */ + 0x0f, 0x0f, /* 0f - C Gain (??? 0x2A recommended) */ + 0x10, 0x0E, /* 10 - C Control 2 */ + 0x11, 0x00, /* 11 - Mode/Delay */ + 0x12, 0x00, /* 12 - RT signal control */ + 0x13, 0x00, /* 13 - RT/X output */ + 0x14, 0x00, /* 14 - Analog, Compat */ + 0x15, 0x11, /* 15 - VGATE start */ + 0x16, 0xFE, /* 16 - VGATE stop */ + 0x17, 0x40, /* 17 - Misc VGATE (disable LLC2) */ + 0x18, 0x40, /* 18 - Raw data gain - 128 */ + 0x19, 0x80, /* 19 - Raw data offset - 0 */ + + /* Global settings */ + 0x88, 0x98, /* 88 - AI1x on, AI2x off; decoder/slicer off; ACLK gen off */ + 0x83, 0x00, /* 83 - X-port output disabled */ + 0x84, 0xF0, /* 84 - I-port V/G output framing, IGP1=0=IGP0=0 */ + 0x85, 0x00, /* 85 - I-port default polarities, X-port signals */ + 0x86, 0x40, /* 86 - more IGP1/0, FIFO level, only video transmitted */ + 0x87, 0x01, /* 87 - ICK default, IDQ default, I-port output enabled */ + + /* Task A: scaler input config and output format */ + 0x90, 0x00, /* 90 - Task handling */ + 0x91, 0x08, /* 91 - Scalar input and format */ + 0x92, 0x10, /* 92 - Reference signal def */ + 0x93, 0x80, /* 93 - I-port output */ + + /* Task B */ + 0xc0, 0x42, /* 90 - Task handling */ + 0xc1, 0x08, /* 91 - Scalar input and format */ + 0xc2, 0x10, /* 92 - Reference signal def */ + 0xc3, 0x80, /* 93 - I-port output */ + + /* Input and Output windows */ + 0x94, 0x10, /* - */ + 0x95, 0x00, /* - */ + 0x96, 0xD0, /* - */ + 0x97, 0x02, /* - */ + 0x98, 0x0A, /* - */ + 0x99, 0x00, /* - */ + 0x9a, 0xF2, /* - */ + 0x9b, 0x00, /* - */ + 0x9c, 0xD0, /* - */ + 0x9d, 0x02, /* - */ + 0xc4, 0x10, /* - */ + 0xc5, 0x00, /* - */ + 0xc6, 0xD0, /* - */ + 0xc7, 0x02, /* - */ + 0xc8, 0x0A, /* - */ + 0xc9, 0x00, /* - */ + 0xca, 0xF2, /* - */ + 0xcb, 0x00, /* - */ + 0xcc, 0xD0, /* - */ + 0xcd, 0x02, /* - */ + + 0x9e, 0xf0, /* - */ + 0x9f, 0x00, /* - */ + 0xce, 0xf0, /* - */ + 0xcf, 0x00, /* - */ + + /* Prefiltering and prescaling */ + 0xa0, 0x01, /* - */ + 0xa1, 0x00, /* - */ + 0xa2, 0x00, /* - */ + 0xa4, 0x80, /* - */ + 0xa5, 0x40, /* - */ + 0xa6, 0x40, /* - */ + 0xd4, 0x80, /* - */ + 0xd5, 0x40, /* - */ + 0xd6, 0x40, /* - */ + + /* Horizontal phase scaling */ + 0xa8, 0x00, /* - */ + 0xa9, 0x04, /* - */ + 0xaa, 0x00, /* - */ + 0xd8, 0x00, /* - */ + 0xd9, 0x04, /* - */ + 0xda, 0x00, /* - */ + + 0xac, 0x00, /* - */ + 0xad, 0x02, /* - */ + 0xae, 0x00, /* - */ + 0xdc, 0x00, /* - */ + 0xdd, 0x02, /* - */ + 0xde, 0x00, /* - */ + + /* Vertical phase scaling */ + 0xb0, 0x00, /* - */ + 0xb1, 0x04, /* - */ + 0xb2, 0x00, /* - */ + 0xb3, 0x04, /* - */ + 0xe0, 0x00, /* - */ + 0xe1, 0x04, /* - */ + 0xe2, 0x00, /* - */ + 0xe3, 0x04, /* - */ + 0xb4, 0x00, /* b4 - vscale mode control */ + 0xe4, 0x00, /* b4 - vscale mode control */ + + /* Task enables */ + 0x80, 0x10, /* 80 - LLC->ICLK, dq->IDQ, scaler->F/V timing, task enables */ + + /* Reset the slicer */ + 0x88, 0xb8, /* 88 - AI1x on, AI2x off; decoder/slicer on; ACLK gen off */ +}; + +static int saa7114h_attach(struct i2c_adapter *adap, int addr, unsigned short flags, int kind) +{ + struct i2c_client *client; + struct video_device *vd; + struct saa7114h *decoder; + int err; + int val, i; + + client = kmalloc(sizeof(*client), GFP_KERNEL); + if (client == NULL) + return -ENOMEM; + client->adapter = adap; + client->addr = addr; + client->driver = &i2c_driver_saa7114h; + strcpy(client->name, IF_NAME); + + decoder = kmalloc(sizeof(*decoder), GFP_KERNEL); + if (decoder == NULL) { + kfree(client); + return -ENOMEM; + } + memset(decoder, 0, sizeof(struct saa7114h)); + decoder->client = client; + decoder->dma_enable = 0; + decoder->palette = VIDEO_PALETTE_UYVY; + decoder->depth = 16; + decoder->vw.width = MAX_HORIZ; + decoder->vw.height = MAX_VERT; + decoder->frame_buf = rvmalloc(MAX_FRAME_SIZE*NUM_FRAME); + if (!decoder->frame_buf) { + kfree(decoder); + kfree(client); + return -ENOMEM; + } + /* XXXKW use clear_page? */ + memset(decoder->frame_buf, 0, MAX_FRAME_SIZE*NUM_FRAME); + printk("saa7114h_attach: frame_buf = (fb=%8p / %08lx)\n", + decoder->frame_buf, kvirt_to_pa((int)decoder->frame_buf)); + for (i=0; iframe[i].data = decoder->frame_buf+i*MAX_FRAME_SIZE; +#if NULL_DMA + decoder->frame[i].state = FRAME_DONE; +#else + decoder->frame[i].state = FRAME_UNUSED; +#endif + init_waitqueue_head(&decoder->frame[i].read_wait); + } + decoder->irq = K_INT_MAC_2; + if (request_irq + (decoder->irq, saa7114h_interrupt, 0, "Philips SAA7114h", decoder)) { + rvfree(decoder->frame_buf, MAX_FRAME_SIZE*NUM_FRAME); + kfree(decoder); + kfree(client); + return -ENOMEM; + } + init_MUTEX(&decoder->param_lock); + init_MUTEX(&decoder->busy_lock); + + if ((err = i2c_attach_client(client)) < 0) { + kfree(client); + kfree(decoder); + return err; + } + + if (saa7114h_reg_init(decoder, reg_init, sizeof(reg_init)) || + saa7114h_get_cparams(decoder)) { + i2c_detach_client(client); + kfree(client); + kfree(decoder); + return -ENODEV; + } + + vd = kmalloc(sizeof(*vd), GFP_KERNEL); + memset(vd, 0, sizeof(*vd)); + if (vd == NULL) { + i2c_detach_client(client); + kfree(client); + kfree(decoder); + return -ENOMEM; + } + vd->priv = decoder; + strcpy(vd->name, IF_NAME); + vd->type = VID_TYPE_CAPTURE; + vd->hardware = VID_HARDWARE_SAA7114H; + vd->open = saa7114h_open; + vd->close = saa7114h_release; + vd->read = saa7114h_read; + vd->ioctl = saa7114h_ioctl; + vd->mmap = saa7114h_mmap; + + if ((err = video_register_device(vd, VFL_TYPE_GRABBER, -1)) < 0) { + i2c_detach_client(client); + kfree(client); + kfree(decoder); + kfree(vd); + return err; + } + + client->data = vd; + decoder->vd = vd; + + /* Turn on the ITRDY - preserve the GENO pin for syncser */ + val = __raw_readq(CKSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)); + __raw_writeq(M_MAC_MDIO_OUT | (val & M_MAC_GENC), + CKSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)); + + if ((err = dma_setup(decoder))) { + i2c_detach_client(client); + kfree(client); + kfree(decoder); + kfree(vd); + return err; + } + + printk("saa7114h_attach successful\n"); + +#ifdef CONFIG_PROC_FS + proc_saa7114h_create(); + create_proc_decoder(vd->priv); +#endif + + return 0; +} + +/* Addresses to scan */ +static unsigned short normal_i2c[] = {I2C_CLIENT_END}; +static unsigned short normal_i2c_range[] = {0x20, 0x21, I2C_CLIENT_END}; +static unsigned short probe[2] = { I2C_CLIENT_END, I2C_CLIENT_END }; +static unsigned short probe_range[2] = { I2C_CLIENT_END, I2C_CLIENT_END }; +static unsigned short ignore[2] = { I2C_CLIENT_END, I2C_CLIENT_END }; +static unsigned short ignore_range[2] = { I2C_CLIENT_END, I2C_CLIENT_END }; +static unsigned short force[2] = { I2C_CLIENT_END, I2C_CLIENT_END }; + +static struct i2c_client_address_data addr_data = { + normal_i2c, normal_i2c_range, + probe, probe_range, + ignore, ignore_range, + force +}; + +static int saa7114h_probe(struct i2c_adapter *adap) +{ + /* Look for this device on the given adapter (bus) */ + if (adap->id == (I2C_ALGO_SIBYTE | I2C_HW_SIBYTE)) + return i2c_probe(adap, &addr_data, &saa7114h_attach); + else + return 0; +} + +static int saa7114h_detach(struct i2c_client *device) +{ +#if 0 + kfree(device->data); +#endif +#ifdef CONFIG_PROC_FS + destroy_proc_decoder(((struct video_device *)device->data)->priv); + proc_saa7114h_destroy(); +#endif + return 0; +} + +/* ----------------------------------------------------------------------- */ + +static int __init swarm_7114h_init(void) +{ + return i2c_add_driver(&i2c_driver_saa7114h); +} + +static void __exit swarm_7114h_cleanup(void) +{ +} + +MODULE_AUTHOR("Kip Walker, Broadcom Corp."); +MODULE_DESCRIPTION("Philips SAA7114H Driver for Broadcom SWARM board"); + +module_init(swarm_7114h_init); +module_exit(swarm_7114h_cleanup); diff -Naur linux-2.6.12.6.orig/drivers/media/video/vino.c linux-2.6.12.6/drivers/media/video/vino.c --- linux-2.6.12.6.orig/drivers/media/video/vino.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/media/video/vino.c 2005-10-02 23:47:38.000000000 +0000 @@ -1,6 +1,6 @@ /* * (incomplete) Driver for the VINO (Video In No Out) system found in SGI Indys. - * + * * This file is subject to the terms and conditions of the GNU General Public * License version 2 as published by the Free Software Foundation. * @@ -139,7 +139,7 @@ static int i2c_vino_client_unreg(struct i2c_client *client) { int res = 0; - + down(&Vino->input_lock); if (client == Vino->decoder.driver) { if (Vino->decoder.owner) @@ -223,7 +223,7 @@ { unsigned long rev; int i, ret = 0; - + /* VINO is Indy specific beast */ if (ip22_is_fullhouse()) return -ENODEV; @@ -231,7 +231,7 @@ /* * VINO is in the EISA address space, so the sysid register will tell * us if the EISA_PRESENT pin on MC has been pulled low. - * + * * If EISA_PRESENT is not set we definitely don't have a VINO equiped * system. */ diff -Naur linux-2.6.12.6.orig/drivers/mtd/devices/Kconfig linux-2.6.12.6/drivers/mtd/devices/Kconfig --- linux-2.6.12.6.orig/drivers/mtd/devices/Kconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/mtd/devices/Kconfig 2005-10-02 23:47:38.000000000 +0000 @@ -47,6 +47,11 @@ accelerator. Say Y here if you have a DECstation 5000/2x0 or a DECsystem 5900 equipped with such a module. + If you want to compile this driver as a module ( = code which can be + inserted in and removed from the running kernel whenever you want), + say M here and read . The module will + be called ms02-nv.o. + config MTD_SLRAM tristate "Uncached system RAM" depends on MTD diff -Naur linux-2.6.12.6.orig/drivers/mtd/devices/docprobe.c linux-2.6.12.6/drivers/mtd/devices/docprobe.c --- linux-2.6.12.6.orig/drivers/mtd/devices/docprobe.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/mtd/devices/docprobe.c 2005-10-02 23:47:38.000000000 +0000 @@ -84,10 +84,10 @@ 0xe4000000, #elif defined(CONFIG_MOMENCO_OCELOT) 0x2f000000, - 0xff000000, + 0xff000000, #elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C) - 0xff000000, -##else + 0xff000000, +#else #warning Unknown architecture for DiskOnChip. No default probe locations defined #endif 0xffffffff }; diff -Naur linux-2.6.12.6.orig/drivers/mtd/devices/ms02-nv.c linux-2.6.12.6/drivers/mtd/devices/ms02-nv.c --- linux-2.6.12.6.orig/drivers/mtd/devices/ms02-nv.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/mtd/devices/ms02-nv.c 2005-10-02 23:47:38.000000000 +0000 @@ -99,8 +99,8 @@ * The firmware writes MS02NV_ID at MS02NV_MAGIC and also * a diagnostic status at MS02NV_DIAG. */ - ms02nv_diagp = (ms02nv_uint *)(KSEG1ADDR(addr + MS02NV_DIAG)); - ms02nv_magicp = (ms02nv_uint *)(KSEG1ADDR(addr + MS02NV_MAGIC)); + ms02nv_diagp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_DIAG)); + ms02nv_magicp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_MAGIC)); err = get_dbe(ms02nv_magic, ms02nv_magicp); if (err) return 0; @@ -233,7 +233,7 @@ goto err_out_csr_res; } - printk(KERN_INFO "mtd%d: %s at 0x%08lx, size %uMiB.\n", + printk(KERN_INFO "mtd%d: %s at 0x%08lx, size %zuMiB.\n", mtd->index, ms02nv_name, addr, size >> 20); mp->next = root_ms02nv_mtd; @@ -293,13 +293,13 @@ switch (mips_machtype) { case MACH_DS5000_200: - csr = (volatile u32 *)KN02_CSR_BASE; + csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); if (*csr & KN02_CSR_BNK32M) stride = 2; break; case MACH_DS5000_2X0: case MACH_DS5900: - csr = (volatile u32 *)KN03_MCR_BASE; + csr = (volatile u32 *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); if (*csr & KN03_MCR_BNK32M) stride = 2; break; diff -Naur linux-2.6.12.6.orig/drivers/mtd/maps/Kconfig linux-2.6.12.6/drivers/mtd/maps/Kconfig --- linux-2.6.12.6.orig/drivers/mtd/maps/Kconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/mtd/maps/Kconfig 2005-10-02 23:47:38.000000000 +0000 @@ -201,87 +201,12 @@ help Support for the flash chip on Tsunami TIG bus. -config MTD_LASAT - tristate "Flash chips on LASAT board" - depends on LASAT - help - Support for the flash chips on the Lasat 100 and 200 boards. - config MTD_NETtel tristate "CFI flash device on SnapGear/SecureEdge" depends on X86 && MTD_PARTITIONS && MTD_JEDECPROBE help Support for flash chips on NETtel/SecureEdge/SnapGear boards. -config MTD_PB1XXX - tristate "Flash devices on Alchemy PB1xxx boards" - depends on MIPS && ( MIPS_PB1000 || MIPS_PB1100 || MIPS_PB1500 ) - help - Flash memory access on Alchemy Pb1000/Pb1100/Pb1500 boards - -config MTD_PB1XXX_BOOT - bool "PB1x00 boot flash device" - depends on MTD_PB1XXX && ( MIPS_PB1100 || MIPS_PB1500 ) - help - Use the first of the two 32MiB flash banks on Pb1100/Pb1500 board. - You can say 'Y' to both this and 'MTD_PB1XXX_USER' below, to use - both banks. - -config MTD_PB1XXX_USER - bool "PB1x00 user flash device" - depends on MTD_PB1XXX && ( MIPS_PB1100 || MIPS_PB1500 ) - default y if MTD_PB1XX_BOOT = n - help - Use the second of the two 32MiB flash banks on Pb1100/Pb1500 board. - You can say 'Y' to both this and 'MTD_PB1XXX_BOOT' above, to use - both banks. - -config MTD_PB1550 - tristate "Flash devices on Alchemy PB1550 board" - depends on MIPS && MIPS_PB1550 - help - Flash memory access on Alchemy Pb1550 board - -config MTD_PB1550_BOOT - bool "PB1550 boot flash device" - depends on MTD_PB1550 - help - Use the first of the two 64MiB flash banks on Pb1550 board. - You can say 'Y' to both this and 'MTD_PB1550_USER' below, to use - both banks. - -config MTD_PB1550_USER - bool "PB1550 user flash device" - depends on MTD_PB1550 - default y if MTD_PB1550_BOOT = n - help - Use the second of the two 64MiB flash banks on Pb1550 board. - You can say 'Y' to both this and 'MTD_PB1550_BOOT' above, to use - both banks. - -config MTD_DB1550 - tristate "Flash devices on Alchemy DB1550 board" - depends on MIPS && MIPS_DB1550 - help - Flash memory access on Alchemy Db1550 board - -config MTD_DB1550_BOOT - bool "DB1550 boot flash device" - depends on MTD_DB1550 - help - Use the first of the two 64MiB flash banks on Db1550 board. - You can say 'Y' to both this and 'MTD_DB1550_USER' below, to use - both banks. - -config MTD_DB1550_USER - bool "DB1550 user flash device" - depends on MTD_DB1550 - default y if MTD_DB1550_BOOT = n - help - Use the second of the two 64MiB flash banks on Db1550 board. - You can say 'Y' to both this and 'MTD_DB1550_BOOT' above, to use - both banks. - config MTD_DILNETPC tristate "CFI Flash device mapped on DIL/Net PC" depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT @@ -357,6 +282,24 @@ Mapping for the Flaga digital module. If you don't have one, ignore this setting. +config MTD_ALCHEMY + tristate ' AMD Alchemy Pb1xxx/Db1xxx/RDK MTD support' + depends on MIPS && SOC_AU1X00 + help + Flash memory access on AMD Alchemy Pb/Db/RDK Reference Boards + +config MTD_XXS1500 + tristate "MyCable XXS1500 Flash device" + depends on MIPS && MIPS_XXS1500 + help + Flash memory access on MyCable XXS1500 Board + +config MTD_MTX1 + tristate "4-G Systems MTX-1 Flash device" + depends on MIPS && MIPS_MTX1 + help + Flash memory access on 4-G Systems MTX-1 Board + config MTD_BEECH tristate "CFI Flash device mapped on IBM 405LP Beech" depends on MTD_CFI && PPC32 && 40x && BEECH @@ -457,6 +400,12 @@ NVRAM on the Momenco Ocelot board. If you have one of these boards and would like access to either of these, say 'Y'. +config MTD_LASAT + tristate "LASAT flash device" + depends on LASAT && MTD_CFI + help + Support for the flash chips on the Lasat 100 and 200 boards. + config MTD_SOLUTIONENGINE tristate "CFI Flash device mapped on Hitachi SolutionEngine" depends on SUPERH && MTD_CFI && MTD_REDBOOT_PARTS diff -Naur linux-2.6.12.6.orig/drivers/mtd/maps/Makefile linux-2.6.12.6/drivers/mtd/maps/Makefile --- linux-2.6.12.6.orig/drivers/mtd/maps/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/mtd/maps/Makefile 2005-10-02 23:47:38.000000000 +0000 @@ -44,11 +44,9 @@ obj-$(CONFIG_MTD_OCELOT) += ocelot.o obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o obj-$(CONFIG_MTD_PCI) += pci.o -obj-$(CONFIG_MTD_PB1XXX) += pb1xxx-flash.o -obj-$(CONFIG_MTD_DB1X00) += db1x00-flash.o -obj-$(CONFIG_MTD_PB1550) += pb1550-flash.o -obj-$(CONFIG_MTD_DB1550) += db1550-flash.o obj-$(CONFIG_MTD_LASAT) += lasat.o +obj-$(CONFIG_MTD_PB1550) += pb1550-flash.o +obj-$(CONFIG_MTD_DB1550) += db1550-flash.o obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o obj-$(CONFIG_MTD_EDB7312) += edb7312.o obj-$(CONFIG_MTD_IMPA7) += impa7.o @@ -70,4 +68,4 @@ obj-$(CONFIG_MTD_IXP2000) += ixp2000.o obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o obj-$(CONFIG_MTD_DMV182) += dmv182.o -obj-$(CONFIG_MTD_SHARP_SL) += sharpsl-flash.o +obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o diff -Naur linux-2.6.12.6.orig/drivers/mtd/maps/alchemy-flash.c linux-2.6.12.6/drivers/mtd/maps/alchemy-flash.c --- linux-2.6.12.6.orig/drivers/mtd/maps/alchemy-flash.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/mtd/maps/alchemy-flash.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,192 @@ +/* + * Flash memory access on AMD Alchemy evaluation boards + * + * $Id: alchemy-flash.c,v 1.1 2005/02/27 22:03:20 ppopov Exp $ + * + * (C) 2003, 2004 Pete Popov + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#ifdef DEBUG_RW +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +#ifdef CONFIG_MIPS_PB1000 +#define BOARD_MAP_NAME "Pb1000 Flash" +#define BOARD_FLASH_SIZE 0x00800000 /* 8MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif + +#ifdef CONFIG_MIPS_PB1500 +#define BOARD_MAP_NAME "Pb1500 Flash" +#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif + +#ifdef CONFIG_MIPS_PB1100 +#define BOARD_MAP_NAME "Pb1100 Flash" +#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif + +#ifdef CONFIG_MIPS_PB1550 +#define BOARD_MAP_NAME "Pb1550 Flash" +#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif + +#ifdef CONFIG_MIPS_PB1200 +#define BOARD_MAP_NAME "Pb1200 Flash" +#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ +#define BOARD_FLASH_WIDTH 2 /* 16-bits */ +#endif + +#ifdef CONFIG_MIPS_DB1000 +#define BOARD_MAP_NAME "Db1000 Flash" +#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif + +#ifdef CONFIG_MIPS_DB1500 +#define BOARD_MAP_NAME "Db1500 Flash" +#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif + +#ifdef CONFIG_MIPS_DB1100 +#define BOARD_MAP_NAME "Db1100 Flash" +#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif + +#ifdef CONFIG_MIPS_DB1550 +#define BOARD_MAP_NAME "Db1550 Flash" +#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif + +#ifdef CONFIG_MIPS_DB1200 +#define BOARD_MAP_NAME "Db1200 Flash" +#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ +#define BOARD_FLASH_WIDTH 2 /* 16-bits */ +#endif + +#ifdef CONFIG_MIPS_HYDROGEN3 +#define BOARD_MAP_NAME "Hydrogen3 Flash" +#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#define USE_LOCAL_ACCESSORS /* why? */ +#endif + +#ifdef CONFIG_MIPS_BOSPORUS +#define BOARD_MAP_NAME "Bosporus Flash" +#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */ +#define BOARD_FLASH_WIDTH 2 /* 16-bits */ +#endif + +#ifdef CONFIG_MIPS_MIRAGE +#define BOARD_MAP_NAME "Mirage Flash" +#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#define USE_LOCAL_ACCESSORS /* why? */ +#endif + +static struct map_info alchemy_map = { + .name = BOARD_MAP_NAME, +}; + +static struct mtd_partition alchemy_partitions[] = { + { + .name = "User FS", + .size = BOARD_FLASH_SIZE - 0x00400000, + .offset = 0x0000000 + },{ + .name = "YAMON", + .size = 0x0100000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE + },{ + .name = "raw kernel", + .size = (0x300000 - 0x40000), /* last 256KB is yamon env */ + .offset = MTDPART_OFS_APPEND, + } +}; + +#define NB_OF(x) (sizeof(x)/sizeof(x[0])) + +static struct mtd_info *mymtd; + +int __init alchemy_mtd_init(void) +{ + struct mtd_partition *parts; + int nb_parts = 0; + unsigned long window_addr; + unsigned long window_size; + + /* Default flash buswidth */ + alchemy_map.bankwidth = BOARD_FLASH_WIDTH; + + window_addr = 0x20000000 - BOARD_FLASH_SIZE; + window_size = BOARD_FLASH_SIZE; +#ifdef CONFIG_MIPS_MIRAGE_WHY + /* Boot ROM flash bank only; no user bank */ + window_addr = 0x1C000000; + window_size = 0x04000000; + /* USERFS from 0x1C00 0000 to 0x1FC00000 */ + alchemy_partitions[0].size = 0x03C00000; +#endif + + /* + * Static partition definition selection + */ + parts = alchemy_partitions; + nb_parts = NB_OF(alchemy_partitions); + alchemy_map.size = window_size; + + /* + * Now let's probe for the actual flash. Do it here since + * specific machine settings might have been set above. + */ + printk(KERN_NOTICE BOARD_MAP_NAME ": probing %d-bit flash bus\n", + alchemy_map.bankwidth*8); + alchemy_map.virt = ioremap(window_addr, window_size); + mymtd = do_map_probe("cfi_probe", &alchemy_map); + if (!mymtd) { + iounmap(alchemy_map.virt); + return -ENXIO; + } + mymtd->owner = THIS_MODULE; + + add_mtd_partitions(mymtd, parts, nb_parts); + return 0; +} + +static void __exit alchemy_mtd_cleanup(void) +{ + if (mymtd) { + del_mtd_partitions(mymtd); + map_destroy(mymtd); + iounmap(alchemy_map.virt); + } +} + +module_init(alchemy_mtd_init); +module_exit(alchemy_mtd_cleanup); + +MODULE_AUTHOR("Embedded Alley Solutions, Inc"); +MODULE_DESCRIPTION(BOARD_MAP_NAME " MTD driver"); +MODULE_LICENSE("GPL"); diff -Naur linux-2.6.12.6.orig/drivers/mtd/maps/db1550-flash.c linux-2.6.12.6/drivers/mtd/maps/db1550-flash.c --- linux-2.6.12.6.orig/drivers/mtd/maps/db1550-flash.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/mtd/maps/db1550-flash.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,187 +0,0 @@ -/* - * Flash memory access on Alchemy Db1550 board - * - * $Id: db1550-flash.c,v 1.7 2004/11/04 13:24:14 gleixner Exp $ - * - * (C) 2004 Embedded Edge, LLC, based on db1550-flash.c: - * (C) 2003, 2004 Pete Popov - * - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#ifdef DEBUG_RW -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -static unsigned long window_addr; -static unsigned long window_size; - - -static struct map_info db1550_map = { - .name = "Db1550 flash", -}; - -static unsigned char flash_bankwidth = 4; - -/* - * Support only 64MB NOR Flash parts - */ - -#if defined(CONFIG_MTD_DB1550_BOOT) && defined(CONFIG_MTD_DB1550_USER) -#define DB1550_BOTH_BANKS -#elif defined(CONFIG_MTD_DB1550_BOOT) && !defined(CONFIG_MTD_DB1550_USER) -#define DB1550_BOOT_ONLY -#elif !defined(CONFIG_MTD_DB1550_BOOT) && defined(CONFIG_MTD_DB1550_USER) -#define DB1550_USER_ONLY -#endif - -#ifdef DB1550_BOTH_BANKS -/* both banks will be used. Combine the first bank and the first - * part of the second bank together into a single jffs/jffs2 - * partition. - */ -static struct mtd_partition db1550_partitions[] = { - /* assume boot[2:0]:swap is '0000' or '1000', which translates to: - * 1C00 0000 1FFF FFFF CE0 64MB Boot NOR Flash - * 1800 0000 1BFF FFFF CE0 64MB Param NOR Flash - */ - { - .name = "User FS", - .size = (0x1FC00000 - 0x18000000), - .offset = 0x0000000 - },{ - .name = "yamon", - .size = 0x0100000, - .offset = MTDPART_OFS_APPEND, - .mask_flags = MTD_WRITEABLE - },{ - .name = "raw kernel", - .size = (0x300000 - 0x40000), /* last 256KB is yamon env */ - .offset = MTDPART_OFS_APPEND, - } -}; -#elif defined(DB1550_BOOT_ONLY) -static struct mtd_partition db1550_partitions[] = { - /* assume boot[2:0]:swap is '0000' or '1000', which translates to: - * 1C00 0000 1FFF FFFF CE0 64MB Boot NOR Flash - */ - { - .name = "User FS", - .size = 0x03c00000, - .offset = 0x0000000 - },{ - .name = "yamon", - .size = 0x0100000, - .offset = MTDPART_OFS_APPEND, - .mask_flags = MTD_WRITEABLE - },{ - .name = "raw kernel", - .size = (0x300000-0x40000), /* last 256KB is yamon env */ - .offset = MTDPART_OFS_APPEND, - } -}; -#elif defined(DB1550_USER_ONLY) -static struct mtd_partition db1550_partitions[] = { - /* assume boot[2:0]:swap is '0000' or '1000', which translates to: - * 1800 0000 1BFF FFFF CE0 64MB Param NOR Flash - */ - { - .name = "User FS", - .size = (0x4000000 - 0x200000), /* reserve 2MB for raw kernel */ - .offset = 0x0000000 - },{ - .name = "raw kernel", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; -#else -#error MTD_DB1550 define combo error /* should never happen */ -#endif - -#define NB_OF(x) (sizeof(x)/sizeof(x[0])) - -static struct mtd_info *mymtd; - -/* - * Probe the flash density and setup window address and size - * based on user CONFIG options. There are times when we don't - * want the MTD driver to be probing the boot or user flash, - * so having the option to enable only one bank is important. - */ -int setup_flash_params(void) -{ -#if defined(DB1550_BOTH_BANKS) - window_addr = 0x18000000; - window_size = 0x8000000; -#elif defined(DB1550_BOOT_ONLY) - window_addr = 0x1C000000; - window_size = 0x4000000; -#else /* USER ONLY */ - window_addr = 0x18000000; - window_size = 0x4000000; -#endif - return 0; -} - -int __init db1550_mtd_init(void) -{ - struct mtd_partition *parts; - int nb_parts = 0; - - /* Default flash bankwidth */ - db1550_map.bankwidth = flash_bankwidth; - - if (setup_flash_params()) - return -ENXIO; - - /* - * Static partition definition selection - */ - parts = db1550_partitions; - nb_parts = NB_OF(db1550_partitions); - db1550_map.size = window_size; - - /* - * Now let's probe for the actual flash. Do it here since - * specific machine settings might have been set above. - */ - printk(KERN_NOTICE "Db1550 flash: probing %d-bit flash bus\n", - db1550_map.bankwidth*8); - db1550_map.virt = ioremap(window_addr, window_size); - mymtd = do_map_probe("cfi_probe", &db1550_map); - if (!mymtd) return -ENXIO; - mymtd->owner = THIS_MODULE; - - add_mtd_partitions(mymtd, parts, nb_parts); - return 0; -} - -static void __exit db1550_mtd_cleanup(void) -{ - if (mymtd) { - del_mtd_partitions(mymtd); - map_destroy(mymtd); - iounmap((void *) db1550_map.virt); - } -} - -module_init(db1550_mtd_init); -module_exit(db1550_mtd_cleanup); - -MODULE_AUTHOR("Embedded Edge, LLC"); -MODULE_DESCRIPTION("Db1550 mtd map driver"); -MODULE_LICENSE("GPL"); diff -Naur linux-2.6.12.6.orig/drivers/mtd/maps/db1x00-flash.c linux-2.6.12.6/drivers/mtd/maps/db1x00-flash.c --- linux-2.6.12.6.orig/drivers/mtd/maps/db1x00-flash.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/mtd/maps/db1x00-flash.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,226 +0,0 @@ -/* - * Flash memory access on Alchemy Db1xxx boards - * - * $Id: db1x00-flash.c,v 1.6 2004/11/04 13:24:14 gleixner Exp $ - * - * (C) 2003 Pete Popov - * - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#ifdef DEBUG_RW -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -/* MTD CONFIG OPTIONS */ -#if defined(CONFIG_MTD_DB1X00_BOOT) && defined(CONFIG_MTD_DB1X00_USER) -#define DB1X00_BOTH_BANKS -#elif defined(CONFIG_MTD_DB1X00_BOOT) && !defined(CONFIG_MTD_DB1X00_USER) -#define DB1X00_BOOT_ONLY -#elif !defined(CONFIG_MTD_DB1X00_BOOT) && defined(CONFIG_MTD_DB1X00_USER) -#define DB1X00_USER_ONLY -#endif - -static unsigned long window_addr; -static unsigned long window_size; -static unsigned long flash_size; - -static unsigned short *bcsr = (unsigned short *)0xAE000000; -static unsigned char flash_bankwidth = 4; - -/* - * The Db1x boards support different flash densities. We setup - * the mtd_partition structures below for default of 64Mbit - * flash densities, and override the partitions sizes, if - * necessary, after we check the board status register. - */ - -#ifdef DB1X00_BOTH_BANKS -/* both banks will be used. Combine the first bank and the first - * part of the second bank together into a single jffs/jffs2 - * partition. - */ -static struct mtd_partition db1x00_partitions[] = { - { - .name = "User FS", - .size = 0x1c00000, - .offset = 0x0000000 - },{ - .name = "yamon", - .size = 0x0100000, - .offset = MTDPART_OFS_APPEND, - .mask_flags = MTD_WRITEABLE - },{ - .name = "raw kernel", - .size = (0x300000-0x40000), /* last 256KB is env */ - .offset = MTDPART_OFS_APPEND, - } -}; -#elif defined(DB1X00_BOOT_ONLY) -static struct mtd_partition db1x00_partitions[] = { - { - .name = "User FS", - .size = 0x00c00000, - .offset = 0x0000000 - },{ - .name = "yamon", - .size = 0x0100000, - .offset = MTDPART_OFS_APPEND, - .mask_flags = MTD_WRITEABLE - },{ - .name = "raw kernel", - .size = (0x300000-0x40000), /* last 256KB is env */ - .offset = MTDPART_OFS_APPEND, - } -}; -#elif defined(DB1X00_USER_ONLY) -static struct mtd_partition db1x00_partitions[] = { - { - .name = "User FS", - .size = 0x0e00000, - .offset = 0x0000000 - },{ - .name = "raw kernel", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; -#else -#error MTD_DB1X00 define combo error /* should never happen */ -#endif -#define NB_OF(x) (sizeof(x)/sizeof(x[0])) - -#define NAME "Db1x00 Linux Flash" - -static struct map_info db1xxx_mtd_map = { - .name = NAME, -}; - -static struct mtd_partition *parsed_parts; -static struct mtd_info *db1xxx_mtd; - -/* - * Probe the flash density and setup window address and size - * based on user CONFIG options. There are times when we don't - * want the MTD driver to be probing the boot or user flash, - * so having the option to enable only one bank is important. - */ -int setup_flash_params(void) -{ - switch ((bcsr[2] >> 14) & 0x3) { - case 0: /* 64Mbit devices */ - flash_size = 0x800000; /* 8MB per part */ -#if defined(DB1X00_BOTH_BANKS) - window_addr = 0x1E000000; - window_size = 0x2000000; -#elif defined(DB1X00_BOOT_ONLY) - window_addr = 0x1F000000; - window_size = 0x1000000; -#else /* USER ONLY */ - window_addr = 0x1E000000; - window_size = 0x1000000; -#endif - break; - case 1: - /* 128 Mbit devices */ - flash_size = 0x1000000; /* 16MB per part */ -#if defined(DB1X00_BOTH_BANKS) - window_addr = 0x1C000000; - window_size = 0x4000000; - /* USERFS from 0x1C00 0000 to 0x1FC0 0000 */ - db1x00_partitions[0].size = 0x3C00000; -#elif defined(DB1X00_BOOT_ONLY) - window_addr = 0x1E000000; - window_size = 0x2000000; - /* USERFS from 0x1E00 0000 to 0x1FC0 0000 */ - db1x00_partitions[0].size = 0x1C00000; -#else /* USER ONLY */ - window_addr = 0x1C000000; - window_size = 0x2000000; - /* USERFS from 0x1C00 0000 to 0x1DE00000 */ - db1x00_partitions[0].size = 0x1DE0000; -#endif - break; - case 2: - /* 256 Mbit devices */ - flash_size = 0x4000000; /* 64MB per part */ -#if defined(DB1X00_BOTH_BANKS) - return 1; -#elif defined(DB1X00_BOOT_ONLY) - /* Boot ROM flash bank only; no user bank */ - window_addr = 0x1C000000; - window_size = 0x4000000; - /* USERFS from 0x1C00 0000 to 0x1FC00000 */ - db1x00_partitions[0].size = 0x3C00000; -#else /* USER ONLY */ - return 1; -#endif - break; - default: - return 1; - } - db1xxx_mtd_map.size = window_size; - db1xxx_mtd_map.bankwidth = flash_bankwidth; - db1xxx_mtd_map.phys = window_addr; - db1xxx_mtd_map.bankwidth = flash_bankwidth; - return 0; -} - -int __init db1x00_mtd_init(void) -{ - struct mtd_partition *parts; - int nb_parts = 0; - - if (setup_flash_params()) - return -ENXIO; - - /* - * Static partition definition selection - */ - parts = db1x00_partitions; - nb_parts = NB_OF(db1x00_partitions); - - /* - * Now let's probe for the actual flash. Do it here since - * specific machine settings might have been set above. - */ - printk(KERN_NOTICE "Db1xxx flash: probing %d-bit flash bus\n", - db1xxx_mtd_map.bankwidth*8); - db1xxx_mtd_map.virt = ioremap(window_addr, window_size); - db1xxx_mtd = do_map_probe("cfi_probe", &db1xxx_mtd_map); - if (!db1xxx_mtd) return -ENXIO; - db1xxx_mtd->owner = THIS_MODULE; - - add_mtd_partitions(db1xxx_mtd, parts, nb_parts); - return 0; -} - -static void __exit db1x00_mtd_cleanup(void) -{ - if (db1xxx_mtd) { - del_mtd_partitions(db1xxx_mtd); - map_destroy(db1xxx_mtd); - if (parsed_parts) - kfree(parsed_parts); - } -} - -module_init(db1x00_mtd_init); -module_exit(db1x00_mtd_cleanup); - -MODULE_AUTHOR("Pete Popov"); -MODULE_DESCRIPTION("Db1x00 mtd map driver"); -MODULE_LICENSE("GPL"); diff -Naur linux-2.6.12.6.orig/drivers/mtd/maps/lasat.c linux-2.6.12.6/drivers/mtd/maps/lasat.c --- linux-2.6.12.6.orig/drivers/mtd/maps/lasat.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/mtd/maps/lasat.c 2005-10-02 23:47:38.000000000 +0000 @@ -7,7 +7,7 @@ * modify it under the terms of the GNU General Public License version * 2 as published by the Free Software Foundation. * - * $Id: lasat.c,v 1.9 2004/11/04 13:24:15 gleixner Exp $ + * $Id: lasat.c,v 1.7 2004/07/12 21:59:44 dwmw2 Exp $ * */ @@ -50,7 +50,7 @@ ENABLE_VPP((&lasat_map)); lasat_map.phys = lasat_flash_partition_start(LASAT_MTD_BOOTLOADER); - lasat_map.virt = ioremap_nocache( + lasat_map.virt = (unsigned long)ioremap_nocache( lasat_map.phys, lasat_board_info.li_flash_size); lasat_map.size = lasat_board_info.li_flash_size; diff -Naur linux-2.6.12.6.orig/drivers/mtd/maps/pb1550-flash.c linux-2.6.12.6/drivers/mtd/maps/pb1550-flash.c --- linux-2.6.12.6.orig/drivers/mtd/maps/pb1550-flash.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/mtd/maps/pb1550-flash.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,203 +0,0 @@ -/* - * Flash memory access on Alchemy Pb1550 board - * - * $Id: pb1550-flash.c,v 1.6 2004/11/04 13:24:15 gleixner Exp $ - * - * (C) 2004 Embedded Edge, LLC, based on pb1550-flash.c: - * (C) 2003 Pete Popov - * - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#ifdef DEBUG_RW -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -static unsigned long window_addr; -static unsigned long window_size; - - -static struct map_info pb1550_map = { - .name = "Pb1550 flash", -}; - -static unsigned char flash_bankwidth = 4; - -/* - * Support only 64MB NOR Flash parts - */ - -#ifdef PB1550_BOTH_BANKS -/* both banks will be used. Combine the first bank and the first - * part of the second bank together into a single jffs/jffs2 - * partition. - */ -static struct mtd_partition pb1550_partitions[] = { - /* assume boot[2:0]:swap is '0000' or '1000', which translates to: - * 1C00 0000 1FFF FFFF CE0 64MB Boot NOR Flash - * 1800 0000 1BFF FFFF CE0 64MB Param NOR Flash - */ - { - .name = "User FS", - .size = (0x1FC00000 - 0x18000000), - .offset = 0x0000000 - },{ - .name = "yamon", - .size = 0x0100000, - .offset = MTDPART_OFS_APPEND, - .mask_flags = MTD_WRITEABLE - },{ - .name = "raw kernel", - .size = (0x300000 - 0x40000), /* last 256KB is yamon env */ - .offset = MTDPART_OFS_APPEND, - } -}; -#elif defined(PB1550_BOOT_ONLY) -static struct mtd_partition pb1550_partitions[] = { - /* assume boot[2:0]:swap is '0000' or '1000', which translates to: - * 1C00 0000 1FFF FFFF CE0 64MB Boot NOR Flash - */ - { - .name = "User FS", - .size = 0x03c00000, - .offset = 0x0000000 - },{ - .name = "yamon", - .size = 0x0100000, - .offset = MTDPART_OFS_APPEND, - .mask_flags = MTD_WRITEABLE - },{ - .name = "raw kernel", - .size = (0x300000-0x40000), /* last 256KB is yamon env */ - .offset = MTDPART_OFS_APPEND, - } -}; -#elif defined(PB1550_USER_ONLY) -static struct mtd_partition pb1550_partitions[] = { - /* assume boot[2:0]:swap is '0000' or '1000', which translates to: - * 1800 0000 1BFF FFFF CE0 64MB Param NOR Flash - */ - { - .name = "User FS", - .size = (0x4000000 - 0x200000), /* reserve 2MB for raw kernel */ - .offset = 0x0000000 - },{ - .name = "raw kernel", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; -#else -#error MTD_PB1550 define combo error /* should never happen */ -#endif - -#define NB_OF(x) (sizeof(x)/sizeof(x[0])) - -static struct mtd_info *mymtd; - -/* - * Probe the flash density and setup window address and size - * based on user CONFIG options. There are times when we don't - * want the MTD driver to be probing the boot or user flash, - * so having the option to enable only one bank is important. - */ -int setup_flash_params(void) -{ - u16 boot_swapboot; - boot_swapboot = (au_readl(MEM_STSTAT) & (0x7<<1)) | - ((bcsr->status >> 6) & 0x1); - printk("Pb1550 MTD: boot:swap %d\n", boot_swapboot); - - switch (boot_swapboot) { - case 0: /* 512Mbit devices, both enabled */ - case 1: - case 8: - case 9: -#if defined(PB1550_BOTH_BANKS) - window_addr = 0x18000000; - window_size = 0x8000000; -#elif defined(PB1550_BOOT_ONLY) - window_addr = 0x1C000000; - window_size = 0x4000000; -#else /* USER ONLY */ - window_addr = 0x1E000000; - window_size = 0x4000000; -#endif - break; - case 0xC: - case 0xD: - case 0xE: - case 0xF: - /* 64 MB Boot NOR Flash is disabled */ - /* and the start address is moved to 0x0C00000 */ - window_addr = 0x0C000000; - window_size = 0x4000000; - default: - printk("Pb1550 MTD: unsupported boot:swap setting\n"); - return 1; - } - return 0; -} - -int __init pb1550_mtd_init(void) -{ - struct mtd_partition *parts; - int nb_parts = 0; - - /* Default flash bankwidth */ - pb1550_map.bankwidth = flash_bankwidth; - - if (setup_flash_params()) - return -ENXIO; - - /* - * Static partition definition selection - */ - parts = pb1550_partitions; - nb_parts = NB_OF(pb1550_partitions); - pb1550_map.size = window_size; - - /* - * Now let's probe for the actual flash. Do it here since - * specific machine settings might have been set above. - */ - printk(KERN_NOTICE "Pb1550 flash: probing %d-bit flash bus\n", - pb1550_map.bankwidth*8); - pb1550_map.virt = ioremap(window_addr, window_size); - mymtd = do_map_probe("cfi_probe", &pb1550_map); - if (!mymtd) return -ENXIO; - mymtd->owner = THIS_MODULE; - - add_mtd_partitions(mymtd, parts, nb_parts); - return 0; -} - -static void __exit pb1550_mtd_cleanup(void) -{ - if (mymtd) { - del_mtd_partitions(mymtd); - map_destroy(mymtd); - } -} - -module_init(pb1550_mtd_init); -module_exit(pb1550_mtd_cleanup); - -MODULE_AUTHOR("Embedded Edge, LLC"); -MODULE_DESCRIPTION("Pb1550 mtd map driver"); -MODULE_LICENSE("GPL"); diff -Naur linux-2.6.12.6.orig/drivers/mtd/maps/pb1xxx-flash.c linux-2.6.12.6/drivers/mtd/maps/pb1xxx-flash.c --- linux-2.6.12.6.orig/drivers/mtd/maps/pb1xxx-flash.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/mtd/maps/pb1xxx-flash.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,178 +0,0 @@ -/* - * Flash memory access on Alchemy Pb1xxx boards - * - * (C) 2001 Pete Popov - * - * $Id: pb1xxx-flash.c,v 1.14 2004/11/04 13:24:15 gleixner Exp $ - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#ifdef DEBUG_RW -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -#ifdef CONFIG_MIPS_PB1000 - -#define WINDOW_ADDR 0x1F800000 -#define WINDOW_SIZE 0x800000 - -static struct mtd_partition pb1xxx_partitions[] = { - { - .name = "yamon env", - .size = 0x00020000, - .offset = 0, - .mask_flags = MTD_WRITEABLE}, - { - .name = "User FS", - .size = 0x003e0000, - .offset = 0x20000,}, - { - .name = "boot code", - .size = 0x100000, - .offset = 0x400000, - .mask_flags = MTD_WRITEABLE}, - { - .name = "raw/kernel", - .size = 0x300000, - .offset = 0x500000} -}; - -#elif defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1100) - -#if defined(CONFIG_MTD_PB1500_BOOT) && defined(CONFIG_MTD_PB1500_USER) -/* both 32MB banks will be used. Combine the first 32MB bank and the - * first 28MB of the second bank together into a single jffs/jffs2 - * partition. - */ -#define WINDOW_ADDR 0x1C000000 -#define WINDOW_SIZE 0x4000000 -static struct mtd_partition pb1xxx_partitions[] = { - { - .name = "User FS", - .size = 0x3c00000, - .offset = 0x0000000 - },{ - .name = "yamon", - .size = 0x0100000, - .offset = 0x3c00000, - .mask_flags = MTD_WRITEABLE - },{ - .name = "raw kernel", - .size = 0x02c0000, - .offset = 0x3d00000 - } -}; -#elif defined(CONFIG_MTD_PB1500_BOOT) && !defined(CONFIG_MTD_PB1500_USER) -#define WINDOW_ADDR 0x1E000000 -#define WINDOW_SIZE 0x2000000 -static struct mtd_partition pb1xxx_partitions[] = { - { - .name = "User FS", - .size = 0x1c00000, - .offset = 0x0000000 - },{ - .name = "yamon", - .size = 0x0100000, - .offset = 0x1c00000, - .mask_flags = MTD_WRITEABLE - },{ - .name = "raw kernel", - .size = 0x02c0000, - .offset = 0x1d00000 - } -}; -#elif !defined(CONFIG_MTD_PB1500_BOOT) && defined(CONFIG_MTD_PB1500_USER) -#define WINDOW_ADDR 0x1C000000 -#define WINDOW_SIZE 0x2000000 -static struct mtd_partition pb1xxx_partitions[] = { - { - .name = "User FS", - .size = 0x1e00000, - .offset = 0x0000000 - },{ - .name = "raw kernel", - .size = 0x0200000, - .offset = 0x1e00000, - } -}; -#else -#error MTD_PB1500 define combo error /* should never happen */ -#endif -#else -#error Unsupported board -#endif - -#define NAME "Pb1x00 Linux Flash" -#define PADDR WINDOW_ADDR -#define BUSWIDTH 4 -#define SIZE WINDOW_SIZE -#define PARTITIONS 4 - -static struct map_info pb1xxx_mtd_map = { - .name = NAME, - .size = SIZE, - .bankwidth = BUSWIDTH, - .phys = PADDR, -}; - -static struct mtd_info *pb1xxx_mtd; - -int __init pb1xxx_mtd_init(void) -{ - struct mtd_partition *parts; - int nb_parts = 0; - char *part_type; - - /* - * Static partition definition selection - */ - part_type = "static"; - parts = pb1xxx_partitions; - nb_parts = ARRAY_SIZE(pb1xxx_partitions); - - /* - * Now let's probe for the actual flash. Do it here since - * specific machine settings might have been set above. - */ - printk(KERN_NOTICE "Pb1xxx flash: probing %d-bit flash bus\n", - BUSWIDTH*8); - pb1xxx_mtd_map.virt = ioremap(WINDOW_ADDR, WINDOW_SIZE); - - simple_map_init(&pb1xxx_mtd_map); - - pb1xxx_mtd = do_map_probe("cfi_probe", &pb1xxx_mtd_map); - if (!pb1xxx_mtd) return -ENXIO; - pb1xxx_mtd->owner = THIS_MODULE; - - add_mtd_partitions(pb1xxx_mtd, parts, nb_parts); - return 0; -} - -static void __exit pb1xxx_mtd_cleanup(void) -{ - if (pb1xxx_mtd) { - del_mtd_partitions(pb1xxx_mtd); - map_destroy(pb1xxx_mtd); - iounmap((void *) pb1xxx_mtd_map.virt); - } -} - -module_init(pb1xxx_mtd_init); -module_exit(pb1xxx_mtd_cleanup); - -MODULE_AUTHOR("Pete Popov"); -MODULE_DESCRIPTION("Pb1xxx CFI map driver"); -MODULE_LICENSE("GPL"); diff -Naur linux-2.6.12.6.orig/drivers/mtd/nand/au1550nd.c linux-2.6.12.6/drivers/mtd/nand/au1550nd.c --- linux-2.6.12.6.orig/drivers/mtd/nand/au1550nd.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/mtd/nand/au1550nd.c 2005-10-02 23:47:38.000000000 +0000 @@ -11,6 +11,7 @@ * */ +#include #include #include #include diff -Naur linux-2.6.12.6.orig/drivers/net/Kconfig linux-2.6.12.6/drivers/net/Kconfig --- linux-2.6.12.6.orig/drivers/net/Kconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/Kconfig 2005-10-02 23:47:38.000000000 +0000 @@ -425,6 +425,14 @@ This is the driver for the onboard card of MIPS Magnum 4000, Acer PICA, Olivetti M700-10 and a few other identical OEM systems. +config GALILEO_64240_ETH + tristate "Galileo GT64240 Ethernet support" + depends on NET_ETHERNET && MOMENCO_OCELOT_G + select MII + help + This is the driver for the ethernet interfaces integrated into + the Galileo (now Marvell) GT64240 chipset. + config MIPS_GT96100ETH bool "MIPS GT96100 Ethernet support" depends on NET_ETHERNET && MIPS_GT96100 @@ -439,10 +447,6 @@ If you have an Alchemy Semi AU1X00 based system say Y. Otherwise, say N. -config NET_SB1250_MAC - tristate "SB1250 Ethernet support" - depends on NET_ETHERNET && SIBYTE_SB1xxx_SOC - config SGI_IOC3_ETH bool "SGI IOC3 Ethernet" depends on NET_ETHERNET && PCI && SGI_IP27 @@ -1923,6 +1927,10 @@ If in doubt, say N. +config NET_SB1250_MAC + tristate "SB1250 Ethernet support" + depends on SIBYTE_SB1xxx_SOC + config R8169_VLAN bool "VLAN support" depends on R8169 && VLAN_8021Q @@ -2057,8 +2065,8 @@ depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MOMENCO_OCELOT_3 || PPC_MULTIPLATFORM help This driver supports the gigabit Ethernet on the Marvell MV643XX - chipset which is used in the Momenco Ocelot C and Jaguar ATX and - Pegasos II, amongst other PPC and MIPS boards. + chipset which is used in the Momenco Ocelot C Ocelot, Jaguar ATX + and Pegasos II, amongst other PPC and MIPS boards. config MV643XX_ETH_0 bool "MV-643XX Port 0" @@ -2081,6 +2089,20 @@ This enables support for Port 2 of the Marvell MV643XX Gigabit Ethernet. +config BIG_SUR_FE + bool "PMC-Sierra TITAN Fast Ethernet Support" + depends on NET_ETHERNET && PMC_BIG_SUR + help + This enables support for the the integrated ethernet of + PMC-Sierra's Big Sur SoC. + +config TITAN_GE + bool "PMC-Sierra TITAN Gigabit Ethernet Support" + depends on PMC_YOSEMITE + help + This enables support for the the integrated ethernet of + PMC-Sierra's Titan SoC. + endmenu # diff -Naur linux-2.6.12.6.orig/drivers/net/Makefile linux-2.6.12.6/drivers/net/Makefile --- linux-2.6.12.6.orig/drivers/net/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/Makefile 2005-10-02 23:47:38.000000000 +0000 @@ -28,6 +28,8 @@ obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o obj-$(CONFIG_SUNGEM) += sungem.o sungem_phy.o +obj-$(CONFIG_SGI_O2MACE_ETH) += meth.o + obj-$(CONFIG_MACE) += mace.o obj-$(CONFIG_BMAC) += bmac.o @@ -100,6 +102,11 @@ obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o +obj-$(CONFIG_GALILEO_64240_ETH) += gt64240eth.o +obj-$(CONFIG_MV64340_ETH) += mv64340_eth.o +obj-$(CONFIG_BIG_SUR_FE) += big_sur_ge.o +obj-$(CONFIG_TITAN_GE) += titan_mdio.o titan_ge.o + obj-$(CONFIG_PPP) += ppp_generic.o slhc.o obj-$(CONFIG_PPP_ASYNC) += ppp_async.o obj-$(CONFIG_PPP_SYNC_TTY) += ppp_synctty.o @@ -120,7 +127,6 @@ obj-$(CONFIG_SUN3LANCE) += sun3lance.o obj-$(CONFIG_DEFXX) += defxx.o obj-$(CONFIG_SGISEEQ) += sgiseeq.o -obj-$(CONFIG_SGI_O2MACE_ETH) += meth.o obj-$(CONFIG_AT1700) += at1700.o obj-$(CONFIG_FMV18X) += fmv18x.o obj-$(CONFIG_EL1) += 3c501.o diff -Naur linux-2.6.12.6.orig/drivers/net/au1000_eth.c linux-2.6.12.6/drivers/net/au1000_eth.c --- linux-2.6.12.6.orig/drivers/net/au1000_eth.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/au1000_eth.c 2005-10-02 23:47:38.000000000 +0000 @@ -32,6 +32,7 @@ * */ +#include #include #include #include @@ -151,13 +152,6 @@ SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \ SUPPORTED_Autoneg -static char *phy_link[] = -{ "unknown", - "10Base2", "10BaseT", - "AUI", - "100BaseT", "100BaseTX", "100BaseFX" -}; - int bcm_5201_init(struct net_device *dev, int phy_addr) { s16 data; @@ -785,6 +779,7 @@ {"Broadcom BCM5201 10/100 BaseT PHY",0x0040,0x6212, &bcm_5201_ops,0}, {"Broadcom BCM5221 10/100 BaseT PHY",0x0040,0x61e4, &bcm_5201_ops,0}, {"Broadcom BCM5222 10/100 BaseT PHY",0x0040,0x6322, &bcm_5201_ops,1}, + {"NS DP83847 PHY", 0x2000, 0x5c30, &bcm_5201_ops ,0}, {"AMD 79C901 HomePNA PHY",0x0000,0x35c8, &am79c901_ops,0}, {"AMD 79C874 10/100 BaseT PHY",0x0022,0x561b, &am79c874_ops,0}, {"LSI 80227 10/100 BaseT PHY",0x0016,0xf840, &lsi_80227_ops,0}, @@ -1045,7 +1040,7 @@ #endif if (aup->mii->chip_info == NULL) { - printk(KERN_ERR "%s: Au1x No MII transceivers found!\n", + printk(KERN_ERR "%s: Au1x No known MII transceivers found!\n", dev->name); return -1; } @@ -1546,6 +1541,9 @@ printk(KERN_ERR "%s: out of memory\n", dev->name); goto err_out; } + aup->mii->next = NULL; + aup->mii->chip_info = NULL; + aup->mii->status = 0; aup->mii->mii_control_reg = 0; aup->mii->mii_data_reg = 0; diff -Naur linux-2.6.12.6.orig/drivers/net/big_sur_ge.c linux-2.6.12.6/drivers/net/big_sur_ge.c --- linux-2.6.12.6.orig/drivers/net/big_sur_ge.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/net/big_sur_ge.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,2005 @@ +/* + * drivers/net/big_sur_ge.c - Driver for PMC-Sierra Big Sur ethernet ports + * + * Copyright (C) 2003 PMC-Sierra Inc. + * Author : Manish Lachwani (lachwani@pmc-sierra.com) + * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +/************************************************************************* + * Description : + * + * The driver has three modes of operation: FIFO non-DMA, Simple DMA + * and SG DMA. There is also a Polled mode and an Interrupt mode of + * operation. SG DMA should do zerocopy and check offload. Probably, + * zerocopy on the Rx might also work. Simple DMA is the non-zerocpy + * case on the Tx and the Rx. + * + * We turn on Simple DMA and interrupt mode. Although, support has been + * added for the SG mode also but not for the polled mode. This is a + * Fast Ethernet driver although there will be support for Gigabit soon. + * + * The driver is divided into two parts: Hardware dependent and a + * Hardware independent. There is currently no support for checksum offload + * zerocopy and Rx NAPI. There is support for Interrupt Mitigation. + ****************************************************************************/ + +/************************************************************* + * Hardware Indepenent Part of the driver + *************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "big_sur_ge.h" + +#define TX_TIMEOUT (60*HZ) /* Transmission timeout is 60 seconds. */ + +static struct net_device *dev_list = NULL; +static DEFINE_SPINLOCK(dev_lock); + +typedef enum DUPLEX { UNKNOWN, HALF_DUPLEX, FULL_DUPLEX } DUPLEX; + +/* Big Sur Ethernet MAC structure */ +struct big_sur_ge_enet { + struct net_device_stats stats; /* Statistics for this device */ + struct net_device *next_dev; /* The next device in dev_list */ + struct timer_list phy_timer; /* PHY monitoring timer */ + u32 index; /* Which interface is this */ + u32 save_base_address; /* Saved physical base address */ + struct sk_buff *saved_skb; /* skb being transmitted */ + spinlock_t lock; /* For atomic access to saved_skb */ + u8 mii_addr; /* The MII address of the PHY */ + big_sur_ge emac; /* GE driver structure */ +}; + +/* Manish : For testing purposes only */ +static unsigned char big_sur_mac_addr_base[6] = "00:11:22:33:44:55"; + +/********************************************************************* + * Function Prototypes (whole bunch of them) + *********************************************************************/ +unsigned long big_sur_ge_dma_control(xdma_channel *); +void big_sur_ge_dma_reset(xdma_channel *); +static void handle_fifo_intr(big_sur_ge *); +void big_sur_ge_check_fifo_recv_error(big_sur_ge *); +void big_sur_ge_check_fifo_send_error(big_sur_ge *); +static int big_sur_ge_config_fifo(big_sur_ge *); +big_sur_ge_config *big_sur_ge_lookup_config(unsigned int); +static int big_sur_ge_config_dma(big_sur_ge *); +void big_sur_ge_enet_reset(big_sur_ge *); +void big_sur_ge_check_mac_error(big_sur_ge *, unsigned long); + +/********************************************************************* + * DMA Channel Initialization + **********************************************************************/ +static int big_sur_ge_dma_init(xdma_channel * dma, unsigned long base_address) +{ + dma->reg_base_address = base_address; + dma->get_ptr = NULL; + dma->put_ptr = NULL; + dma->commit_ptr = NULL; + dma->last_ptr = NULL; + dma->total_desc_count = (unsigned long) NULL; + dma->active_desc_count = (unsigned long) NULL; + dma->ready = 1; /* DMA channel is ready */ + + big_sur_ge_dma_reset(dma); + + return 0; +} + +/********************************************************************* + * Is the DMA channel ready yet ? + **********************************************************************/ +static int big_sur_ge_dma_ready(xdma_channel * dma) +{ + return dma->ready == 1; +} + +/********************************************************************* + * Perform the self test on the DMA channel + **********************************************************************/ +#define BIG_SUR_GE_CONTROL_REG_RESET_MASK 0x98000000 + +static int big_sur_ge_dma_self_test(xdma_channel * dma) +{ + unsigned long reg_data; + + big_sur_ge_dma_reset(dma); + + reg_data = big_sur_ge_dma_control(dma); + if (reg_data != BIG_SUR_GE_CONTROL_REG_RESET_MASK) { + printk(KERN_ERR "DMA Channel Self Test Failed \n"); + return -1; + } + + return 0; +} + +/********************************************************************* + * Reset the DMA channel + **********************************************************************/ +static void big_sur_ge_dma_reset(xdma_channel * dma) +{ + BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_RST_REG_OFFSET, + BIG_SUR_GE_RESET_MASK); +} + +/********************************************************************* + * Get control of the DMA channel + **********************************************************************/ +static unsigned long big_sur_ge_dma_control(xdma_channel * dma) +{ + return BIG_SUR_GE_READ(dma->reg_base_address + + BIG_SUR_GE_DMAC_REG_OFFSET); +} + +/********************************************************************* + * Set control of the DMA channel + **********************************************************************/ +static void big_sur_ge_set_dma_control(xdma_channel * dma, unsigned long control) +{ + BIG_SUR_GE_WRITE(dma->reg_base_address + + BIG_SUR_GE_DMAC_REG_OFFSET, control); +} + +/********************************************************************* + * Get the status of the DMA channel + *********************************************************************/ +static unsigned long big_sur_ge_dma_status(xdma_channel * dma) +{ + return BIG_SUR_GE_READ(dma->reg_base_address + + BIG_SUR_GE_DMAS_REG_OFFSET); +} + +/********************************************************************* + * Set the interrupt status of the DMA channel + *********************************************************************/ +static void big_sur_ge_set_intr_status(xdma_channel * dma, unsigned long status) +{ + BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_IS_REG_OFFSET, + status); +} + +/********************************************************************* + * Get the interrupt status of the DMA channel + *********************************************************************/ +static unsigned long big_sur_ge_get_intr_status(xdma_channel * dma) +{ + return BIG_SUR_GE_READ(dma->reg_base_address + + BIG_SUR_GE_IS_REG_OFFSET); +} + +/********************************************************************* + * Set the Interrupt Enable + *********************************************************************/ +static void big_sur_ge_set_intr_enable(xdma_channel * dma, unsigned long enable) +{ + BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_IE_REG_OFFSET, + enable); +} + +/********************************************************************* + * Get the Interrupt Enable field to make a check + *********************************************************************/ +static unsigned long big_sur_ge_get_intr_enable(xdma_channel * dma) +{ + return BIG_SUR_GE_READ(dma->reg_base_address + + BIG_SUR_GE_IE_REG_OFFSET); +} + +/********************************************************************* + * Transfer the data over the DMA channel + *********************************************************************/ +static void big_sur_ge_dma_transfer(xdma_channel * dma, unsigned long *source, + unsigned long *dest, unsigned long length) +{ + BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_SA_REG_OFFSET, + (unsigned long) source); + + BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_DA_REG_OFFSET, + (unsigned long) dest); + + BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_LEN_REG_OFFSET, + length); +} + +/********************************************************************* + * Get the DMA descriptor + *********************************************************************/ +static int big_sur_ge_get_descriptor(xdma_channel * dma, + xbuf_descriptor ** buffer_desc) +{ + unsigned long reg_data; + + reg_data = xbuf_descriptor_GetControl(dma->get_ptr); + xbuf_descriptor_SetControl(dma->get_ptr, reg_data | + BIG_SUR_GE_DMACR_SG_DISABLE_MASK); + + *buffer_desc = dma->get_ptr; + + dma->get_ptr = xbuf_descriptor_GetNextPtr(dma->get_ptr); + dma->active_desc_count--; + + return 0; +} + +/********************************************************************* + * Get the packet count + *********************************************************************/ +static int big_sur_ge_get_packet_count(xdma_channel * dma) +{ + return (BIG_SUR_GE_READ + (dma->reg_base_address + BIG_SUR_GE_UPC_REG_OFFSET)); +} + +/********************************************************************* + * Descrement the packet count + *********************************************************************/ +static void big_sur_ge_decr_packet_count(xdma_channel * dma) +{ + unsigned long reg_data; + + reg_data = + BIG_SUR_GE_READ(dma->base_address + BIG_SUR_GE_UPC_REG_OFFSET); + if (reg_data > 0) + BIG_SUR_GE_WRITE(dma->base_address + + BIG_SUR_GE_UPC_REG_OFFSET, 1); +} + +/**************************************************************************** + * Start of the code that deals with the Packet Fifo + *****************************************************************************/ + +/**************************************************************************** + * Init the packet fifo + ****************************************************************************/ +static int packet_fifo_init(packet_fifo * fifo, u32 reg, u32 data) +{ + fifo->reg_base_addr = reg; + fifo->data_base_address = data; + fifo->ready_status = 1; + + BIG_SUR_GE_FIFO_RESET(fifo); + + return 0; +} + +/**************************************************************************** + * Packet fifo self test + ****************************************************************************/ +static int packet_fifo_self_test(packet_fifo * fifo, unsigned long type) +{ + unsigned long reg_data; + + BIG_SUR_GE_FIFO_RESET(fifo); + reg_data = + BIG_SUR_GE_READ(fifo->reg_base_addr + + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET); + + if (type == BIG_SUR_GE_READ_FIFO_TYPE) { + if (reg_data != BIG_SUR_GE_EMPTY_FULL_MASK) { + printk(KERN_ERR "Read FIFO not empty \n"); + return -1; + } + } else if (!(reg_data & BIG_SUR_GE_EMPTY_FULL_MASK)) { + printk(KERN_ERR "Write FIFO is full \n"); + return -1; + } + + return 0; +} + +/**************************************************************************** + * Packet FIFO read + ****************************************************************************/ +static int packet_fifo_read(packet_fifo * fifo, u8 * buffer, unsigned int len) +{ + unsigned long fifo_count, word_count, extra_byte; + unsigned long *buffer_data = (unsigned long *) buffer; + + fifo_count = + BIG_SUR_GE_READ(fifo->reg_base_addr + + BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT); + fifo_count &= BIG_SUR_GE_COUNT_MASK; + + if ((fifo_count * BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT) < len) + return -1; + + word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT; + extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT; + + for (fifo_count = 0; fifo_count < word_count; fifo_count++) + buffer_data[fifo_count] = + BIG_SUR_GE_READ(fifo->reg_base_addr); + + if (extra_byte > 0) { + unsigned long last_word; + int *extra_buffer_data = + (int *) (buffer_data + word_count); + + last_word = BIG_SUR_GE_READ(fifo->data_base_address); + if (extra_byte == 1) + extra_buffer_data[0] = (int) (last_word << 24); + else if (extra_byte == 2) { + extra_buffer_data[0] = (int) (last_word << 24); + extra_buffer_data[1] = (int) (last_word << 16); + } else if (extra_byte == 3) { + extra_buffer_data[0] = (int) (last_word << 24); + extra_buffer_data[1] = (int) (last_word << 16); + extra_buffer_data[2] = (int) (last_word << 8); + } + } + + return 0; +} + +/***************************************************************************** + * Write the data into the packet fifo + *****************************************************************************/ +static int packet_fifo_write(packet_fifo * fifo, int *buffer, int len) +{ + unsigned long fifo_count, word_count, extra_byte; + unsigned long *buffer_data = (unsigned long *) buffer; + + fifo_count = + BIG_SUR_GE_READ(fifo->reg_base_addr + + BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT); + fifo_count &= BIG_SUR_GE_COUNT_MASK; + + word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT; + extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT; + + /* You should see what the ppc driver does here. It just slobbers */ + if (extra_byte > 0) + if (fifo_count > (word_count + 1)) { + printk(KERN_ERR + "No room in the packet send fifo \n"); + return -1; + } + + for (fifo_count = 0; fifo_count < word_count; fifo_count++) + BIG_SUR_GE_WRITE(fifo->data_base_address, + buffer_data[fifo_count]); + + + if (extra_byte > 0) { + unsigned long last_word = 0; + int *extra_buffer_data = + (int *) (buffer_data + word_count); + + if (extra_byte == 1) + last_word = extra_buffer_data[0] << 24; + else if (extra_byte == 2) + last_word = (extra_buffer_data[0] << 24 | + extra_buffer_data[1] << 16); + + else if (extra_byte == 3) + last_word = (extra_buffer_data[0] << 24 | + extra_buffer_data[1] << 16 | + extra_buffer_data[2] << 8); + + + BIG_SUR_GE_WRITE(fifo->data_base_address, last_word); + } + + return 0; +} + + +/***************************************************************************** + * Interrupt handlers: We handle any errors associated with the FIFO. + * FIFO is for simple dma case and we do want to handle the simple DMA + * case. We dont handle the Scatter Gather DMA for now since it is not working. + ******************************************************************************/ + +/********************************************************************************* + * FIFO send for Simple DMA with Interrupts + **********************************************************************************/ +static int big_sur_ge_enet_fifo_send(big_sur_ge * emac, u8 * buffer, + unsigned long byte_cnt) +{ + unsigned long int_status, reg_data; + + /* Silly checks here that we really dont need */ + if (!emac->started) + return -1; + + if (emac->polled) + return -1; + + if (emac->dma_sg) + return -1; + + int_status = + BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET); + if (int_status & BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK) { + printk(KERN_ERR "Tx FIFO error: Queue is Full \n"); + return -1; + } + + /* + * Write the data to the FIFO in the hardware + */ + if ((BIG_SUR_GE_GET_COUNT(&emac->send_fifo) * + sizeof(unsigned long)) < byte_cnt) { + printk(KERN_ERR "Send FIFO on chip is full \n"); + return -1; + } + + if (big_sur_ge_dma_status(&emac->send_channel) & + BIG_SUR_GE_DMASR_BUSY_MASK) { + printk(KERN_ERR "Send channel FIFO engine busy \n"); + return -1; + } + + big_sur_ge_set_dma_control(&emac->send_channel, + BIG_SUR_GE_DMACR_SOURCE_INCR_MASK | + BIG_SUR_GE_DMACR_DEST_LOCAL_MASK | + BIG_SUR_GE_DMACR_SG_DISABLE_MASK); + + big_sur_ge_dma_transfer(&emac->send_channel, + (unsigned long *) buffer, + (unsigned long *) (emac->base_address + + BIG_SUR_GE_PFIFO_TXDATA_OFFSET), + byte_cnt); + + reg_data = big_sur_ge_dma_status(&emac->send_channel); + while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) { + reg_data = big_sur_ge_dma_status(&emac->recv_channel); + if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK)) + break; + } + + if ((reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) || + (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) { + printk(KERN_ERR "Send side DMA error \n"); + return -1; + } + + BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_TPLR_OFFSET, + byte_cnt); + + return 0; +} + +/************************************************************************* + * FIFO receive for Simple DMA case + *************************************************************************/ +static int big_sur_ge_enet_fifo_recv(big_sur_ge * emac, u8 * buffer, + unsigned long *byte_cnt) +{ + unsigned long int_status, reg_data; + + /* Silly checks here that we really dont need */ + if (!emac->started) + return -1; + + if (emac->polled) + return -1; + + if (emac->dma_sg) + return -1; + + if (*byte_cnt < BIG_SUR_GE_MAX_FRAME_SIZE) + return -1; + + int_status = + BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET); + if (int_status & BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK) { + BIG_SUR_GE_WRITE(emac->base_address + + XIIF_V123B_IISR_OFFSET, + BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK); + return -1; + } + + if (big_sur_ge_dma_status(&emac->recv_channel) & + BIG_SUR_GE_DMASR_BUSY_MASK) { + printk(KERN_ERR "Rx side DMA Engine busy \n"); + return -1; + } + + if (BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_RPLR_OFFSET) == + 0) { + printk(KERN_ERR "MAC has the FIFO packet length 0 \n"); + return -1; + } + + /* For the simple DMA case only */ + big_sur_ge_set_dma_control(&emac->recv_channel, + BIG_SUR_GE_DMACR_DEST_INCR_MASK | + BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK | + BIG_SUR_GE_DMACR_SG_DISABLE_MASK); + + if (packet_fifo_read(&emac->recv_fifo, buffer, + BIG_SUR_GE_READ(emac->base_address + + BIG_SUR_GE_RPLR_OFFSET)) == + -1) { + printk(KERN_ERR "Not enough space in the FIFO \n"); + return -1; + } + + big_sur_ge_dma_transfer(&emac->recv_channel, + (unsigned long *) (emac->base_address + + BIG_SUR_GE_PFIFO_RXDATA_OFFSET), + (unsigned long *) + buffer, + BIG_SUR_GE_READ(emac->base_address + + BIG_SUR_GE_RPLR_OFFSET)); + + reg_data = big_sur_ge_dma_status(&emac->recv_channel); + while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) { + reg_data = big_sur_ge_dma_status(&emac->recv_channel); + if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK)) + break; + } + + if ((reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) || + (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) { + printk(KERN_ERR "DMA Bus Error \n"); + return -1; + } + + *byte_cnt = + BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_RPLR_OFFSET); + + return 0; +} + +static irqreturn_t big_sur_ge_int_handler(int irq, void *dev_id, + struct pt_regs *regs) +{ + struct net_device *netdev = dev_id; + struct big_sur_ge_enet *lp = netdev->priv; + big_sur_ge *emac = (big_sur_ge *)emac_ptr; + void *emac_ptr = &lp->emac; + unsigned long int_status; + + int_status = + BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_DIPR_OFFSET); + if (int_status & BIG_SUR_GE_IPIF_EMAC_MASK) + handle_fifo_intr(emac); + + if (int_status & BIG_SUR_GE_IPIF_RECV_FIFO_MASK) + big_sur_ge_check_fifo_recv_error(emac); + + if (int_status & BIG_SUR_GE_IPIF_SEND_FIFO_MASK) + big_sur_ge_check_fifo_send_error(emac); + + if (int_status & XIIF_V123B_ERROR_MASK) + BIG_SUR_GE_WRITE(emac->base_address + + XIIF_V123B_DISR_OFFSET, + XIIF_V123B_ERROR_MASK); + + return IRQ_HANDLED; +} + +/**************************************************************************** + * Set the FIFO send handler + ***************************************************************************/ +static void big_sur_ge_set_fifo_send_handler(big_sur_ge * emac, void *call_back, + big_sur_fifo_handler function) +{ + emac->big_sur_ge_fifo_send_handler = function; + emac->fifo_send_ref = call_back; +} + +/**************************************************************************** + * Set the FIFO recv handler + ***************************************************************************/ +static void big_sur_ge_set_fifo_recv_handler(big_sur_ge * emac, void *call_back, + big_sur_fifo_handler function) +{ + emac->big_sur_ge_fifo_recv_handler = function; + emac->fifo_recv_ref = call_back; +} + +/**************************************************************************** + * Main Fifo intr handler + ***************************************************************************/ +static void handle_fifo_intr(big_sur_ge * emac) +{ + unsigned long int_status; + + /* Ack the interrupts asap */ + int_status = + BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET); + BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IISR_OFFSET, + int_status); + + /* Process the Rx side */ + if (int_status & BIG_SUR_GE_EIR_RECV_DONE_MASK) { + emac->big_sur_ge_fifo_recv_handler(&emac->fifo_recv_ref); + BIG_SUR_GE_WRITE(emac->base_address + + XIIF_V123B_IISR_OFFSET, + BIG_SUR_GE_EIR_RECV_DONE_MASK); + } + + if (int_status & BIG_SUR_GE_EIR_XMIT_DONE_MASK) { + /* We dont collect stats and hence we dont need to get status */ + + emac->big_sur_ge_fifo_send_handler(emac->fifo_recv_ref); + BIG_SUR_GE_WRITE(emac->base_address + + XIIF_V123B_IISR_OFFSET, + BIG_SUR_GE_EIR_XMIT_DONE_MASK); + } + + big_sur_ge_check_mac_error(emac, int_status); +} + +/****************************************************************** + * Handle the Receive side DMA interrupts. The PPC driver has + * callbacks all over the place. This has been eliminated here by + * using the following approach: + * + * The ISR is set to the main interrrupt handler. This will handle + * all the interrupts including the ones for DMA. In this main isr, + * we determine if we need to call recv or send side intr functions. + * Pretty complex but thats the way it is now. + *******************************************************************/ +static void big_sur_ge_handle_recv_intr(big_sur_ge * emac) +{ + unsigned long int_status; + + int_status = big_sur_ge_get_intr_status(&emac->recv_channel); + if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK | + BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK)) { + u32 num_packets; + u32 num_processed; + u32 num_buffers; + u32 num_bytes; + xbuf_descriptor *first_desc_ptr = NULL; + xbuf_descriptor *buffer_desc; + int is_last = 0; + + /* The number of packets we need to process on the Rx */ + num_packets = + big_sur_ge_get_packet_count(&emac->recv_channel); + + for (num_processed = 0; num_processed < num_packets; + num_processed++) { + while (!is_last) { + if (big_sur_ge_get_descriptor + (&emac->recv_channel, + &buffer_desc) == -1) + break; + + if (first_desc_ptr == NULL) + first_desc_ptr = buffer_desc; + + num_bytes += + xbuf_descriptor_GetLength(buffer_desc); + + if (xbuf_descriptor_IsLastStatus + (buffer_desc)) { + is_last = 1; + } + + num_buffers++; + } + + /* Number of buffers is always 1 since we dont do SG */ + + /* + * Only for SG DMA which is currently not supported. In the + * future, as we have SG channel working, we will code this + * receive side routine. For now, do nothing. This is never + * called from FIFO mode - Manish + */ + big_sur_ge_decr_packet_count(&emac->recv_channel); + } + } + + /* Ack the interrupts */ + big_sur_ge_set_intr_status(&emac->recv_channel, int_status); + + if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) { + /* We need a reset here */ + } + + big_sur_ge_set_intr_status(&emac->recv_channel, int_status); +} + +/**************************************************************** + * Handle the send side DMA interrupt + ****************************************************************/ +static void big_sur_ge_handle_send_intr(big_sur_ge * emac) +{ + unsigned long int_status; + + int_status = big_sur_ge_get_intr_status(&emac->send_channel); + + if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK | + BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK)) { + unsigned long num_frames = 0; + unsigned long num_processed = 0; + unsigned long num_buffers = 0; + unsigned long num_bytes = 0; + unsigned long is_last = 0; + xbuf_descriptor *first_desc_ptr = NULL; + xbuf_descriptor *buffer_desc; + + num_frames = + big_sur_ge_get_packet_count(&emac->send_channel); + + for (num_processed = 0; num_processed < num_frames; + num_processed++) { + while (!is_last) { + if (big_sur_ge_get_descriptor + (&emac->send_channel, &buffer_desc) + == -1) { + break; + } + + if (first_desc_ptr == NULL) + first_desc_ptr = buffer_desc; + + num_bytes += + xbuf_descriptor_GetLength(buffer_desc); + if (xbuf_descriptor_IsLastControl + (buffer_desc)) + is_last = 1; + + num_buffers++; + } + + /* + * Only for SG DMA which is currently not supported. In the + * future, as we have SG channel working, we will code this + * receive side routine. For now, do nothing. This is never + * called from FIFO mode - Manish + */ + big_sur_ge_decr_packet_count(&emac->send_channel); + } + } + + /* Ack the interrupts and reset DMA channel if necessary */ + big_sur_ge_set_intr_status(&emac->send_channel, int_status); + if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) { + /* Manish : need reset */ + } + + big_sur_ge_set_intr_status(&emac->send_channel, int_status); +} + +/***************************************************************** + * For now, the MAC address errors dont trigger a update of the + * stats. There is no stats framework in place. Hence, we just + * check for the errors below and do a reset if needed. + *****************************************************************/ +static void big_sur_ge_check_mac_error(big_sur_ge * emac, + unsigned long int_status) +{ + if (int_status & (BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK | + BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK | + BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK | + BIG_SUR_GE_EIR_RECV_ERROR_MASK | + BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK | + BIG_SUR_GE_EIR_RECV_COLLISION_MASK | + BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK | + BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK | + BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK | + BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK | + BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK | + BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK | + BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK | + BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK | + BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK)) { + + BIG_SUR_GE_WRITE(emac->base_address + + XIIF_V123B_IIER_OFFSET, 0); + /* + * Manish Reset the MAC here + */ + } +} + +/***************************************************************** + * Check for FIFO Recv errors + *****************************************************************/ +static void big_sur_ge_check_fifo_recv_error(big_sur_ge * emac) +{ + if (BIG_SUR_GE_IS_DEADLOCKED(&emac->recv_fifo)) { + unsigned long intr_enable; + + intr_enable = + BIG_SUR_GE_READ(emac->base_address + + XIIF_V123B_DIER_OFFSET); + BIG_SUR_GE_WRITE(emac->base_address + + XIIF_V123B_DIER_OFFSET, + intr_enable & + ~(BIG_SUR_GE_IPIF_RECV_FIFO_MASK)); + + } +} + +/***************************************************************** + * Check for FIFO Send errors + *****************************************************************/ +static void big_sur_ge_check_fifo_send_error(big_sur_ge * emac) +{ + if (BIG_SUR_GE_IS_DEADLOCKED(&emac->send_fifo)) { + unsigned long intr_enable; + + intr_enable = + BIG_SUR_GE_READ(emac->base_address + + XIIF_V123B_DIER_OFFSET); + BIG_SUR_GE_WRITE(emac->base_address + + XIIF_V123B_DIER_OFFSET, + intr_enable & + ~(BIG_SUR_GE_IPIF_SEND_FIFO_MASK)); + } +} + +/***************************************************************** + * GE unit init + ****************************************************************/ +static int big_sur_ge_enet_init(big_sur_ge * emac, unsigned int device_id) +{ + unsigned long reg_data; + big_sur_ge_config *config; + int err; + + /* Assume that the device has been stopped */ + + config = big_sur_ge_lookup_config(device_id); + if (config == NULL) + return -1; + + emac->ready = 0; + emac->started = 0; + emac->dma_sg = 0; /* This MAC has no support for Scatter Gather DMA */ + emac->has_mii = config->has_mii; + emac->has_mcast_hash_table = 0; + emac->dma_config = config->dma_config; + + /* + * Initialize the FIFO send and recv handlers to the stub handlers. + * We only deal with the FIFO mode of operation since SG is not supported. + * Also, there is no error handler. We try to handle as much of error as + * possible and then return. No error codes also. + */ + + emac->base_address = config->base_address; + + if (big_sur_ge_config_dma(emac) == -1) + return -1; + + err = big_sur_ge_config_fifo(emac); + if (err == -1) + return err; + + /* Now, we know that the FIFO initialized successfully. So, set the ready flag */ + emac->ready = 1; + + /* Do we need a PHY reset here also. It did cause problems on some boards */ + big_sur_ge_enet_reset(emac); + + /* PHY reset code. Remove if causes a problem on the board */ + reg_data = + BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET); + reg_data &= ~(BIG_SUR_GE_ECR_PHY_ENABLE_MASK); + BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET, + reg_data); + reg_data |= BIG_SUR_GE_ECR_PHY_ENABLE_MASK; + BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET, + reg_data); + + return 0; +} + +/******************************************************************* + * Start the GE unit for Tx, Rx and Interrupts + *******************************************************************/ +static int big_sur_ge_start(big_sur_ge * emac) +{ + unsigned long reg_data; + + /* + * Basic mode of operation is polled and interrupt mode. We disable the polled + * mode for good. We may use the polled mode for Rx NAPI but that does not + * require all the interrupts to be disabled + */ + + emac->polled = 0; + + /* + * DMA: Three modes of operation - simple, FIFO, SG. SG is surely not working + * and so is kept off using the dma_sg flag. Simple and FIFO work. But, we may + * not use FIFO at all. So, we enable the interrupts below + */ + + BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DIER_OFFSET, + BIG_SUR_GE_IPIF_FIFO_DFT_MASK | + XIIF_V123B_ERROR_MASK); + + BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IIER_OFFSET, + BIG_SUR_GE_EIR_DFT_FIFO_MASK); + + /* Toggle the started flag */ + emac->started = 1; + + /* Start the Tx and Rx units respectively */ + reg_data = + BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET); + reg_data &= + ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK | + BIG_SUR_GE_ECR_RECV_RESET_MASK); + reg_data |= + (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | + BIG_SUR_GE_ECR_RECV_ENABLE_MASK); + + BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET, + reg_data); + + return 0; +} + +/************************************************************************** + * Stop the GE unit + **************************************************************************/ +static int big_sur_ge_stop(big_sur_ge * emac) +{ + unsigned long reg_data; + + /* We assume that the device is not already stopped */ + if (!emac->started) + return 0; + + /* Disable the Tx and Rx unit respectively */ + reg_data = + BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET); + reg_data &= + ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | + BIG_SUR_GE_ECR_RECV_ENABLE_MASK); + BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET, + reg_data); + + /* Disable the interrupts */ + BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DGIER_OFFSET, 0); + + /* Toggle the started flag */ + emac->started = 0; + + return 0; +} + +/************************************************************************ + * Reset the GE MAC unit + *************************************************************************/ +static void big_sur_ge_enet_reset(big_sur_ge * emac) +{ + unsigned long reg_data; + + (void) big_sur_ge_stop(emac); + + BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_RESETR_OFFSET, + XIIF_V123B_RESET_MASK); + + /* + * For now, configure the receiver to not strip off FCS and padding since + * this is not currently supported. In the future, just take the default + * and provide the option for the user to change this behavior. + */ + reg_data = + BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET); + reg_data &= + ~(BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK | + BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK); + reg_data &= ~(BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK); + BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET, + reg_data); +} + +/************************************************************************* + * Set the MAC address of the GE mac unit + *************************************************************************/ +static int big_sur_ge_set_mac_address(big_sur_ge * emac, unsigned char *addr) +{ + unsigned long mac_addr = 0; + + /* Device is started and so mac address must be set */ + if (emac->started == 1) + return 0; + + mac_addr = ((addr[0] << 8) | addr[1]); + BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAH_OFFSET, + mac_addr); + + mac_addr |= ((addr[2] << 24) | (addr[3] << 16) | + (addr[4] << 8) | addr[5]); + + BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAL_OFFSET, + mac_addr); + + return 0; +} + +/**************************************************************************** + * Get the MAC address of the GE MAC unit + ***************************************************************************/ +static void big_sur_ge_get_mac_unit(big_sur_ge * emac, unsigned int *addr) +{ + unsigned long mac_addr_hi, mac_addr_lo; + + mac_addr_hi = + BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAH_OFFSET); + mac_addr_lo = + BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAL_OFFSET); + + addr[0] = (mac_addr_hi >> 8); + addr[1] = mac_addr_hi; + + addr[2] = (mac_addr_lo >> 24); + addr[3] = (mac_addr_lo >> 16); + addr[4] = (mac_addr_lo >> 8); + addr[5] = mac_addr_lo; +} + +/********************************************************************************* + * Configure the GE MAC for DMA capabilities. Not for Scatter Gather, only Simple + *********************************************************************************/ +static int big_sur_ge_config_dma(big_sur_ge * emac) +{ + if (big_sur_ge_dma_init(&emac->recv_channel, emac->base_address + + BIG_SUR_GE_DMA_RECV_OFFSET) == -1) { + printk(KERN_ERR "Could not initialize the DMA unit \n"); + return -1; + } + + if (big_sur_ge_dma_init(&emac->send_channel, emac->base_address + + BIG_SUR_GE_DMA_SEND_OFFSET) == -1) { + printk(KERN_ERR "Could not initialize the DMA unit \n"); + return -1; + } + + return 0; +} + +/****************************************************************************** + * Configure the FIFO for simple DMA + ******************************************************************************/ +static int big_sur_ge_config_fifo(big_sur_ge * emac) +{ + int err = 0; + + err = packet_fifo_init(&emac->recv_fifo, emac->base_address + + BIG_SUR_GE_PFIFO_RXREG_OFFSET, + emac->base_address + + BIG_SUR_GE_PFIFO_RXDATA_OFFSET); + + if (err == -1) { + printk(KERN_ERR + "Could not initialize Rx packet FIFO for Simple DMA \n"); + return err; + } + + err = packet_fifo_init(&emac->send_fifo, emac->base_address + + BIG_SUR_GE_PFIFO_TXREG_OFFSET, + emac->base_address + + BIG_SUR_GE_PFIFO_TXDATA_OFFSET); + + if (err == -1) { + printk(KERN_ERR + "Could not initialize Tx packet FIFO for Simple DMA \n"); + } + + return err; +} + +#define BIG_SUR_GE_NUM_INSTANCES 2 + + +/********************************************************************************** + * Look up the config of the MAC + **********************************************************************************/ +static big_sur_ge_config *big_sur_ge_lookup_config(unsigned int device_id) +{ + big_sur_ge_config *config = NULL; + int i = 0; + + for (i = 0; i < BIG_SUR_GE_NUM_INSTANCES; i++) { + /* Manish : Init the config here */ + break; + } + + return config; +} + +typedef struct { + unsigned long option; + unsigned long mask; +} option_map; + +static option_map option_table[] = { + {BIG_SUR_GE_UNICAST_OPTION, BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK}, + {BIG_SUR_GE_BROADCAST_OPTION, BIG_SUR_GE_ECR_BROAD_ENABLE_MASK}, + {BIG_SUR_GE_PROMISC_OPTION, BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK}, + {BIG_SUR_GE_FDUPLEX_OPTION, BIG_SUR_GE_ECR_FULL_DUPLEX_MASK}, + {BIG_SUR_GE_LOOPBACK_OPTION, BIG_SUR_GE_ECR_LOOPBACK_MASK}, + {BIG_SUR_GE_MULTICAST_OPTION, BIG_SUR_GE_ECR_MULTI_ENABLE_MASK}, + {BIG_SUR_GE_FLOW_CONTROL_OPTION, BIG_SUR_GE_ECR_PAUSE_FRAME_MASK}, + {BIG_SUR_GE_INSERT_PAD_OPTION, + BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK}, + {BIG_SUR_GE_INSERT_FCS_OPTION, + BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK}, + {BIG_SUR_GE_INSERT_ADDR_OPTION, + BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK}, + {BIG_SUR_GE_OVWRT_ADDR_OPTION, + BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK}, + {BIG_SUR_GE_STRIP_PAD_OPTION, BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK}, + {BIG_SUR_GE_STRIP_FCS_OPTION, BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK}, + {BIG_SUR_GE_STRIP_PAD_FCS_OPTION, + BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK} +}; + +#define BIG_SUR_GE_NUM_OPTIONS (sizeof(option_table) / sizeof(option_map)) + +/********************************************************************** + * Set the options for the GE + **********************************************************************/ +static int big_sur_ge_set_options(big_sur_ge * emac, unsigned long option_flag) +{ + unsigned long reg_data; + unsigned int index; + + /* Assume that the device is stopped before calling this function */ + + reg_data = + BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET); + for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) { + if (option_flag & option_table[index].option) + reg_data |= option_table[index].mask; + else + reg_data &= ~(option_table[index].mask); + + } + + BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET, + reg_data); + + /* No polled option */ + emac->polled = 0; + + return 0; +} + +/******************************************************* + * Get the options from the GE + *******************************************************/ +static unsigned long big_sur_ge_get_options(big_sur_ge * emac) +{ + unsigned long option_flag = 0, reg_data; + unsigned int index; + + reg_data = + BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET); + + for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) { + if (option_flag & option_table[index].option) + reg_data |= option_table[index].mask; + } + + /* No polled mode */ + + return option_flag; +} + +/******************************************************** + * Set the Inter frame gap + ********************************************************/ +static int big_sur_ge_set_frame_gap(big_sur_ge * emac, int part1, int part2) +{ + unsigned long config; + + /* Assume that the device is stopped before calling this */ + + config = ((part1 << BIG_SUR_GE_IFGP_PART1_SHIFT) | + (part2 << BIG_SUR_GE_IFGP_PART2_SHIFT)); + + BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_IFGP_OFFSET, + config); + + return 0; +} + +/******************************************************** + * Get the Inter frame gap + ********************************************************/ +static void big_sur_ge_get_frame_gap(big_sur_ge * emac, int *part1, int *part2) +{ + unsigned long config; + + config = + BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_IFGP_OFFSET); + *part1 = + ((config & BIG_SUR_GE_IFGP_PART1_SHIFT) >> + BIG_SUR_GE_IFGP_PART1_SHIFT); + *part2 = + ((config & BIG_SUR_GE_IFGP_PART2_SHIFT) >> + BIG_SUR_GE_IFGP_PART2_SHIFT); +} + +/******************************************************************* + * PHY specific functions for the MAC + *******************************************************************/ +#define BIG_SUR_GE_MAX_PHY_ADDR 32 +#define BIG_SUR_GE_MAX_PHY_REG 32 + +/******************************************************************* + * Read the PHY reg + *******************************************************************/ +static int big_sur_ge_phy_read(big_sur_ge * emac, unsigned long addr, + unsigned long reg_num, unsigned int *data) +{ + unsigned long mii_control, mii_data; + + if (!emac->has_mii) + return -1; + + mii_control = + BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET); + if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) { + printk(KERN_ERR "PHY busy \n"); + return -1; + } + + mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT); + mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT); + mii_control |= + (BIG_SUR_GE_MGTCR_RW_NOT_MASK | BIG_SUR_GE_MGTCR_START_MASK | + BIG_SUR_GE_MGTCR_MII_ENABLE_MASK); + + BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET, + mii_control); + + while (mii_control & BIG_SUR_GE_MGTCR_START_MASK) + if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK)) + break; + + mii_data = + BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET); + *data = (unsigned int) mii_data; + + return 0; +} + +/********************************************************************** + * Write to the PHY register + **********************************************************************/ +static int big_sur_ge_phy_write(big_sur_ge * emac, unsigned long addr, + unsigned long reg_num, unsigned int data) +{ + unsigned long mii_control; + + if (!emac->has_mii) + return -1; + + mii_control = + BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET); + if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) { + printk(KERN_ERR "PHY busy \n"); + return -1; + } + + BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET, + (unsigned long) data); + + mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT); + mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT); + mii_control |= + (BIG_SUR_GE_MGTCR_START_MASK | + BIG_SUR_GE_MGTCR_MII_ENABLE_MASK); + + BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET, + mii_control); + + while (mii_control & BIG_SUR_GE_MGTCR_START_MASK) + if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK)) + break; + + return 0; +} + + + + + + +/******************************************************************** + * The hardware dependent part of the driver begins here + ********************************************************************/ + + +/******************************************************************* + * Reset the GE system + *******************************************************************/ +static void big_sur_ge_reset(struct net_device *netdev, DUPLEX duplex) +{ + struct big_sur_ge_enet *lp = netdev->priv; + struct sk_buff *skb; + unsigned long options; + int ifcfg1, ifcfg2; + + /* Stop the queue */ + netif_stop_queue(netdev); + + big_sur_ge_get_frame_gap(&lp->emac, &ifcfg1, &ifcfg2); + options = big_sur_ge_get_options(&lp->emac); + switch (duplex) { + case HALF_DUPLEX: + options &= ~(BIG_SUR_GE_FDUPLEX_OPTION); + break; + + case FULL_DUPLEX: + options |= BIG_SUR_GE_FDUPLEX_OPTION; + break; + + case UNKNOWN: + break; + } + + /* There is no support for SG DMA in a 100 Mpbs NIC */ + + big_sur_ge_enet_reset(&lp->emac); + + /* Set the necessary options for the MAC unit */ + big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr); + big_sur_ge_set_frame_gap(&lp->emac, ifcfg1, ifcfg2); + big_sur_ge_set_options(&lp->emac, options); + + (void) big_sur_ge_start(&lp->emac); + + spin_lock_irq(&lp->lock); + skb = lp->saved_skb; + lp->saved_skb = NULL; + spin_unlock_irq(&lp->lock); + + if (skb) + dev_kfree_skb(skb); + + /* Wake the queue */ + netif_wake_queue(netdev); +} + +/******************************************************************** + * Get the PHY status + *******************************************************************/ +static int big_sur_ge_get_phy_status(struct net_device *netdev, + DUPLEX * duplex, int *linkup) +{ + struct big_sur_ge_enet *lp = netdev->priv; + unsigned int reg_data; + int err = 0; + + err = + big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_BMCR, + ®_data); + if (err == -1) { + printk(KERN_ERR "%s: Could not read PHY control register", + netdev->name); + return err; + } + + if (!(reg_data & BMCR_ANENABLE)) { + if (reg_data & BMCR_FULLDPLX) + *duplex = FULL_DUPLEX; + else + *duplex = HALF_DUPLEX; + } else { + unsigned int advertise, partner, neg; + + err = + big_sur_ge_phy_read(&lp->emac, lp->mii_addr, + MII_ADVERTISE, &advertise); + if (err == -1) { + printk(KERN_ERR + "%s: Could not read PHY control register", + netdev->name); + return err; + } + + err = + big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_LPA, + &partner); + if (err == -1) { + printk(KERN_ERR + "%s: Could not read PHY control register", + netdev->name); + return err; + } + + neg = advertise & partner & ADVERTISE_ALL; + if (neg & ADVERTISE_100FULL) + *duplex = FULL_DUPLEX; + else if (neg & ADVERTISE_100HALF) + *duplex = HALF_DUPLEX; + else if (neg & ADVERTISE_10FULL) + *duplex = FULL_DUPLEX; + else + *duplex = HALF_DUPLEX; + + err = + big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_BMSR, + ®_data); + if (err == -1) { + printk(KERN_ERR + "%s: Could not read PHY control register", + netdev->name); + return err; + } + + *linkup = (reg_data & BMSR_LSTATUS) != 0; + + } + return 0; +} + +/************************************************************ + * Poll the MII for duplex and link status + ***********************************************************/ +static void big_sur_ge_poll_mii(unsigned long data) +{ + struct net_device *netdev = (struct net_device *) data; + struct big_sur_ge_enet *lp = netdev->priv; + unsigned long options; + DUPLEX mac_duplex, phy_duplex; + int phy_carrier, netif_carrier; + + if (big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier) == + -1) { + printk(KERN_ERR "%s: Terminating link monitoring.\n", + netdev->name); + return; + } + + options = big_sur_ge_get_options(&lp->emac); + if (options & BIG_SUR_GE_FDUPLEX_OPTION) + mac_duplex = FULL_DUPLEX; + else + mac_duplex = HALF_DUPLEX; + + if (mac_duplex != phy_duplex) { + disable_irq(netdev->irq); + big_sur_ge_reset(netdev, phy_duplex); + enable_irq(netdev->irq); + } + + netif_carrier = netif_carrier_ok(netdev) != 0; + + if (phy_carrier != netif_carrier) { + if (phy_carrier) { + printk(KERN_INFO "%s: Link carrier restored.\n", + netdev->name); + netif_carrier_on(netdev); + } else { + printk(KERN_INFO "%s: Link carrier lost.\n", + netdev->name); + netif_carrier_off(netdev); + } + } + + /* Set up the timer so we'll get called again in 2 seconds. */ + lp->phy_timer.expires = jiffies + 2 * HZ; + add_timer(&lp->phy_timer); +} + +/************************************************************** + * Open the network interface + *************************************************************/ +static int big_sur_ge_open(struct net_device *netdev) +{ + struct big_sur_ge_enet *lp = netdev->priv; + unsigned long options; + DUPLEX phy_duplex, mac_duplex; + int phy_carrier, retval; + + (void) big_sur_ge_stop(&lp->emac); + + if (big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr) == -1) { + printk(KERN_ERR "%s: Could not set MAC address.\n", + netdev->name); + return -EIO; + } + + options = big_sur_ge_get_options(&lp->emac); + + retval = + request_irq(netdev->irq, &big_sur_ge_int_handler, 0, + netdev->name, netdev); + if (retval) { + printk(KERN_ERR + "%s: Could not allocate interrupt %d.\n", + netdev->name, netdev->irq); + + return retval; + } + + if (! + (big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier))) + { + if (options & BIG_SUR_GE_FDUPLEX_OPTION) + mac_duplex = FULL_DUPLEX; + else + mac_duplex = HALF_DUPLEX; + + if (mac_duplex != phy_duplex) { + switch (phy_duplex) { + case HALF_DUPLEX: + options &= ~(BIG_SUR_GE_FDUPLEX_OPTION); + break; + case FULL_DUPLEX: + options |= BIG_SUR_GE_FDUPLEX_OPTION; + break; + case UNKNOWN: + break; + } + + big_sur_ge_set_options(&lp->emac, options); + } + } + + if (big_sur_ge_start(&lp->emac) == -1) { + printk(KERN_ERR "%s: Could not start device.\n", + netdev->name); + free_irq(netdev->irq, netdev); + return -EBUSY; + } + + netif_start_queue(netdev); + + lp->phy_timer.expires = jiffies + 2 * HZ; + lp->phy_timer.data = (unsigned long) netdev; + lp->phy_timer.function = &big_sur_ge_poll_mii; + add_timer(&lp->phy_timer); + + return 0; +} + +/********************************************************************* + * Close the network device interface + *********************************************************************/ +static int big_sur_ge_close(struct net_device *netdev) +{ + struct big_sur_ge_enet *lp = netdev->priv; + + del_timer_sync(&lp->phy_timer); + netif_stop_queue(netdev); + + free_irq(netdev->irq, netdev); + + if (big_sur_ge_stop(&lp->emac) == -1) { + printk(KERN_ERR "%s: Could not stop device.\n", + netdev->name); + return -EBUSY; + } + + return 0; +} + +/********************************************************************* + * Get the network device stats. For now, do nothing + *********************************************************************/ +static struct net_device_stats *big_sur_ge_get_stats(struct net_device + *netdev) +{ + /* Do nothing */ + return (struct net_device_stats *) 0; +} + +/******************************************************************** + * FIFO send for a packet that needs to be transmitted + ********************************************************************/ +static int big_sur_ge_fifo_send(struct sk_buff *orig_skb, + struct net_device *netdev) +{ + struct big_sur_ge_enet *lp = netdev->priv; + struct sk_buff *new_skb; + unsigned int len, align; + + netif_stop_queue(netdev); + len = orig_skb->len; + + if (!(new_skb = dev_alloc_skb(len + 4))) { + dev_kfree_skb(orig_skb); + printk(KERN_ERR + "%s: Could not allocate transmit buffer.\n", + netdev->name); + netif_wake_queue(netdev); + return -EBUSY; + } + + align = 4 - ((unsigned long) new_skb->data & 3); + if (align != 4) + skb_reserve(new_skb, align); + + skb_put(new_skb, len); + memcpy(new_skb->data, orig_skb->data, len); + + dev_kfree_skb(orig_skb); + + lp->saved_skb = new_skb; + if (big_sur_ge_enet_fifo_send(&lp->emac, (u8 *) new_skb->data, len) + == -1) { + spin_lock_irq(&lp->lock); + new_skb = lp->saved_skb; + lp->saved_skb = NULL; + spin_unlock_irq(&lp->lock); + + dev_kfree_skb(new_skb); + printk(KERN_ERR "%s: Could not transmit buffer.\n", + netdev->name); + netif_wake_queue(netdev); + return -EIO; + } + return 0; +} + +/********************************************************************** + * Call the fifo send handler + **********************************************************************/ +static void big_sur_ge_fifo_send_handler(void *callback) +{ + struct net_device *netdev = (struct net_device *) callback; + struct big_sur_ge_enet *lp = netdev->priv; + struct sk_buff *skb; + + spin_lock_irq(&lp->lock); + skb = lp->saved_skb; + lp->saved_skb = NULL; + spin_unlock_irq(&lp->lock); + + if (skb) + dev_kfree_skb(skb); + + netif_wake_queue(netdev); +} + +/********************************************************************** + * Handle the timeout of the ethernet device + **********************************************************************/ +static void big_sur_ge_tx_timeout(struct net_device *netdev) +{ + printk + ("%s: Exceeded transmit timeout of %lu ms. Resetting mac.\n", + netdev->name, TX_TIMEOUT * 1000UL / HZ); + + disable_irq(netdev->irq); + big_sur_ge_reset(netdev, UNKNOWN); + enable_irq(netdev->irq); +} + +/********************************************************************* + * When in FIFO mode, the callback function for packets received + *********************************************************************/ +static void big_sur_ge_fifo_recv_handler(void *callback) +{ + struct net_device *netdev = (struct net_device *) callback; + struct big_sur_ge_enet *lp = netdev->priv; + struct sk_buff *skb; + unsigned long len = BIG_SUR_GE_MAX_FRAME_SIZE; + unsigned int align; + + if (!(skb = dev_alloc_skb(len + 4))) { + printk(KERN_ERR "%s: Could not allocate receive buffer.\n", + netdev->name); + return; + } + + align = 4 - ((unsigned long) skb->data & 3); + if (align != 4) + skb_reserve(skb, align); + + if (big_sur_ge_enet_fifo_recv(&lp->emac, (u8 *) skb->data, &len) == + -1) { + dev_kfree_skb(skb); + + printk(KERN_ERR "%s: Could not receive buffer \n", + netdev->name); + netdev->tx_timeout = NULL; + big_sur_ge_reset(netdev, UNKNOWN); + netdev->tx_timeout = big_sur_ge_tx_timeout; + } + + skb_put(skb, len); /* Tell the skb how much data we got. */ + skb->dev = netdev; /* Fill out required meta-data. */ + skb->protocol = eth_type_trans(skb, netdev); + + netif_rx(skb); /* Send the packet upstream. */ +} + +/********************************************************************* + * Set the Multicast Hash list + *********************************************************************/ +static void big_sur_ge_set_multicast_hash_list(struct net_device *netdev) +{ + struct big_sur_ge_enet *lp = netdev->priv; + unsigned long options; + + disable_irq(netdev->irq); + local_bh_disable(); + + (void) big_sur_ge_stop(&lp->emac); + options = big_sur_ge_get_options(&lp->emac); + options &= + ~(BIG_SUR_GE_PROMISC_OPTION | BIG_SUR_GE_MULTICAST_OPTION); + + /* Do nothing for now */ + + (void) big_sur_ge_start(&lp->emac); + local_bh_enable(); + enable_irq(netdev->irq); +} + +/*********************************************************************** + * IOCTL support + ***********************************************************************/ +static int big_sur_ge_ioctl(struct net_device *netdev, struct ifreq *rq, + int cmd) +{ + struct big_sur_ge_enet *lp = netdev->priv; + struct mii_ioctl_data *data = + (struct mii_ioctl_data *) &rq->ifr_data; + + switch (cmd) { + case SIOCGMIIPHY: /* Get address of MII PHY in use. */ + case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */ + data->phy_id = lp->mii_addr; + + case SIOCGMIIREG: /* Read MII PHY register. */ + case SIOCDEVPRIVATE + 1: /* for binary compat, remove in 2.5 */ + if (data->phy_id > 31 || data->reg_num > 31) + return -ENXIO; + + del_timer_sync(&lp->phy_timer); + + if (big_sur_ge_phy_read(&lp->emac, data->phy_id, + data->reg_num, + &data->val_out) == -1) { + printk(KERN_ERR "%s: Could not read from PHY", + netdev->name); + return -EBUSY; + } + + lp->phy_timer.expires = jiffies + 2 * HZ; + add_timer(&lp->phy_timer); + + return 0; + + case SIOCSMIIREG: /* Write MII PHY register. */ + case SIOCDEVPRIVATE + 2: /* for binary compat, remove in 2.5 */ + if (data->phy_id > 31 || data->reg_num > 31) + return -ENXIO; + + del_timer_sync(&lp->phy_timer); + + if (big_sur_ge_phy_write + (&lp->emac, data->phy_id, data->reg_num, + data->val_in) == -1) { + printk(KERN_ERR "%s: Could not write to PHY", + netdev->name); + return -EBUSY; + } + + lp->phy_timer.expires = jiffies + 2 * HZ; + add_timer(&lp->phy_timer); + + return 0; + + default: + return -EOPNOTSUPP; + } +} + +/***************************************************************** + * Get the config from the config table + *****************************************************************/ +static big_sur_ge_config *big_sur_ge_get_config(int index) +{ + /* Manish */ + return (big_sur_ge_config *) 0; +} + +/***************************************************************** + * Release the network device structure + *****************************************************************/ +static void big_sur_ge_remove_head(void) +{ + struct net_device *netdev; + struct big_sur_ge_enet *lp; + big_sur_ge_config *config; + + spin_lock(&dev_lock); + netdev = dev_list; + lp = netdev->priv; + + spin_unlock(&dev_lock); + + config = big_sur_ge_get_config(lp->index); + iounmap((void *) config->base_address); + config->base_address = lp->save_base_address; + + if (lp->saved_skb) + dev_kfree_skb(lp->saved_skb); + kfree(lp); + + unregister_netdev(netdev); + kfree(netdev); +} + +/***************************************************************** + * Initial Function to probe the network interface + *****************************************************************/ +static int __init big_sur_ge_probe(int index) +{ + static const unsigned long remap_size = + BIG_SUR_GE_EMAC_0_HIGHADDR - BIG_SUR_GE_EMAC_0_BASEADDR + 1; + struct net_device *netdev; + struct big_sur_ge_enet *lp; + big_sur_ge_config *config; + unsigned int irq; + unsigned long maddr; + goto err; + + switch (index) { + case 0: + irq = (31 - BIG_SUR_GE_INTC_0_EMAC_0_VEC_ID); + break; + case 1: + irq = (31 - BIG_SUR_GE_INTC_1_EMAC_1_VEC_ID); + break; + case 2: + irq = (31 - BIG_SUR_GE_INTC_2_EMAC_2_VEC_ID); + break; + default: + err = -ENODEV; + goto out; + } + + config = big_sur_ge_get_config(index); + if (!config) { + err = -ENODEV; + goto out; + } + + netdev = alloc_etherdev(sizeof(big_sur_ge_config)); + + if (!netdev) { + err = -ENOMEM; + goto out; + } + + SET_MODULE_OWNER(netdev); + + netdev->irq = irq; + + lp = (struct big_sur_ge_enet *) netdev->priv; + memset(lp, 0, sizeof(struct big_sur_ge_enet)); + spin_lock_init(&lp->lock); + spin_lock(&dev_lock); + lp->next_dev = dev_list; + dev_list = netdev; + spin_unlock(&dev_lock); + + lp->save_base_address = config->base_address; + config->base_address = + (unsigned long) ioremap(lp->save_base_address, remap_size); + if (!config->base_address) { + err = -ENOMEM; + goto out_unlock; + } + + if (big_sur_ge_enet_init(&lp->emac, config->device_id) == -1) { + printk(KERN_ERR "%s: Could not initialize device.\n", + netdev->name); + err = -ENODEV; + goto out_unmap; + } + + /* Manish: dev_addr value */ + memcpy(netdev->dev_addr, big_sur_mac_addr_base, 6); + if (big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr) == -1) { + printk(KERN_ERR "%s: Could not set MAC address.\n", + netdev->name); + err = -EIO; + goto out_unmap; + } + + /* + * There is no Scatter Gather support but there is a Simple DMA support + */ + big_sur_ge_set_fifo_recv_handler(&lp->emac, netdev, + big_sur_ge_fifo_recv_handler); + big_sur_ge_set_fifo_send_handler(&lp->emac, netdev, + big_sur_ge_fifo_send_handler); + netdev->hard_start_xmit = big_sur_ge_fifo_send; + + lp->mii_addr = 0xFF; + + for (maddr = 0; maddr < 31; maddr++) { + unsigned int reg_data; + + if (big_sur_ge_phy_read + (&lp->emac, maddr, MII_BMCR, ®_data) == 0) { + lp->mii_addr = maddr; + break; + } + } + + if (lp->mii_addr == 0xFF) { + lp->mii_addr = 0; + printk(KERN_WARNING + "%s: No PHY detected. Assuming a PHY at address %d.\n", + netdev->name, lp->mii_addr); + } + + netdev->open = big_sur_ge_open; + netdev->stop = big_sur_ge_close; + netdev->get_stats = big_sur_ge_get_stats; /* Does nothing */ + netdev->do_ioctl = big_sur_ge_ioctl; + netdev->tx_timeout = big_sur_ge_tx_timeout; + netdev->watchdog_timeo = TX_TIMEOUT; + + err = register_netdev(netdev)) + if (!err) + goto out_unmap; + + printk(KERN_INFO "%s: PMC-Sierra Big Sur Ethernet Device %d at 0x%08X " + "mapped to 0x%08X, irq=%d\n", netdev->name, index, + lp->save_base_address, config->base_address, netdev->irq); + + return ret; + +out_unmap: + iounmap(config->base_address); + +out_unlock: + big_sur_ge_remove_head(); + +out: + return ret; +} + +static int __init big_sur_ge_init(void) +{ + int index = 0; + + while (big_sur_ge_probe(index++) == 0); + + return (index > 1) ? 0 : -ENODEV; +} + +static void __exit big_sur_ge_cleanup(void) +{ + while (dev_list) + big_sur_ge_remove_head(); +} + +module_init(big_sur_ge_init); +module_exit(big_sur_ge_cleanup); + +MODULE_AUTHOR("Manish Lachwani "); +MODULE_DESCRIPTION("PMC-Sierra Big Sur Ethernet MAC Driver"); +MODULE_LICENSE("GPL"); diff -Naur linux-2.6.12.6.orig/drivers/net/big_sur_ge.h linux-2.6.12.6/drivers/net/big_sur_ge.h --- linux-2.6.12.6.orig/drivers/net/big_sur_ge.h 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/net/big_sur_ge.h 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,713 @@ +/* + * drivers/net/big_sur_ge.h - Driver for PMC-Sierra Big Sur + * ethernet ports + * + * Copyright (C) 2003 PMC-Sierra Inc. + * Author : Manish Lachwani (lachwani@pmc-sierra.com) + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef __BIG_SUR_GE_H__ +#define __BIG_SUR_GE_H__ + +#include +#include +#include +#include +#include + +#define BIG_SUR_DEVICE_NAME "big sur" +#define BIG_SUR_DEVICE_DESC "Big Sur Ethernet 10/100 MAC" + +#define BIG_SUR_GE_BASE 0xbb000000 + +#define BIG_SUR_GE_WRITE(ofs,data) *(volatile u32 *)(BIG_SUR_GE_BASE+(ofs)) = data + +#define BIG_SUR_GE_READ(ofs) *(volatile u32 *)(BIG_SUR_GE_BASE+(ofs)) + +/* Manish : Need to fix these defines later */ +#define BIG_SUR_GE_EMAC_0_HIGHADDR +#define BIG_SUR_GE_EMAC_0_BASEADDR +#define BIG_SUR_GE_INTC_0_EMAC_0_VEC_ID 1 +#define BIG_SUR_GE_INTC_1_EMAC_1_VEC_ID 2 +#define BIG_SUR_GE_INTC_2_EMAC_2_VEC_ID 3 +#define BIG_SUR_GE_EMAC_0_ERR_COUNT_EXIST +#define BIG_SUR_GE_EMAC_0_DMA_PRESENT +#define BIG_SUR_GE_EMAC_0_MII_EXIST +#define BIG_SUR_GE_OPB_ETHERNET_0_BASEADDR +#define BIG_SUR_GE_EMAC_0_DEVICE_ID +#define BIG_SUR_GE_OPB_ETHERNET_0_ERR_COUNT_EXIST +#define BIG_SUR_GE_OPB_ETHERNET_0_DMA_PRESENT +#define BIG_SUR_GE_OPB_ETHERNET_0_MII_EXIST +#define BIG_SUR_GE_OPB_ETHERNET_0_DEVICE_ID + +#define BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT 4UL +/* IPIF specific defines */ +#define XIIF_V123B_DISR_OFFSET 0UL /* device interrupt status register */ +#define XIIF_V123B_DIPR_OFFSET 4UL /* device interrupt pending register */ +#define XIIF_V123B_DIER_OFFSET 8UL /* device interrupt enable register */ +#define XIIF_V123B_DIIR_OFFSET 24UL /* device interrupt ID register */ +#define XIIF_V123B_DGIER_OFFSET 28UL /* device global interrupt enable reg */ +#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ +#define XIIF_V123B_IIER_OFFSET 40UL /* IP interrupt enable register */ +#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ +#define XIIF_V123B_RESET_MASK 0xAUL +#define XIIF_V123B_ERROR_MASK 0x1UL + +/* defines */ +#define BIG_SUR_GE_UNICAST_OPTION 0x00000001 +#define BIG_SUR_GE_BROADCAST_OPTION 0x00000002 +#define BIG_SUR_GE_PROMISC_OPTION 0x00000004 +#define BIG_SUR_GE_FDUPLEX_OPTION 0x00000008 +#define BIG_SUR_GE_POLLED_OPTION 0x00000010 +#define BIG_SUR_GE_LOOPBACK_OPTION 0x00000020 +#define BIG_SUR_GE_FLOW_CONTROL_OPTION 0x00000080 +#define BIG_SUR_GE_INSERT_PAD_OPTION 0x00000100 +#define BIG_SUR_GE_INSERT_FCS_OPTION 0x00000200 +#define BIG_SUR_GE_INSERT_ADDR_OPTION 0x00000400 +#define BIG_SUR_GE_OVWRT_ADDR_OPTION 0x00000800 +#define BIG_SUR_GE_STRIP_PAD_FCS_OPTION 0x00002000 + +/* Not Supported */ +#define BIG_SUR_GE_MULTICAST_OPTION 0x00000040 +#define BIG_SUR_GE_FLOW_CONTROL_OPTION 0x00000080 +#define BIG_SUR_GE_INSERT_PAD_OPTION 0x00000100 +#define BIG_SUR_GE_INSERT_FCS_OPTION 0x00000200 +#define BIG_SUR_GE_INSERT_ADDR_OPTION 0x00000400 +#define BIG_SUR_GE_OVWRT_ADDR_OPTION 0x00000800 +#define BIG_SUR_GE_STRIP_PAD_OPTION 0x00001000 +#define BIG_SUR_GE_STRIP_FCS_OPTION 0x00002000 + + +/* Defaults for Interrupt Coalescing in the SG DMA Engine */ +#define BIG_SUR_GE_SGDMA_DFT_THRESHOLD 1 /* Default pkt threshold */ +#define BIG_SUR_GE_SGDMA_MAX_THRESHOLD 255 /* Maximum pkt theshold */ +#define BIG_SUR_GE_SGDMA_DFT_WAITBOUND 5 /* Default pkt wait bound (msec) */ +#define BIG_SUR_GE_SGDMA_MAX_WAITBOUND 1023 /* Maximum pkt wait bound (msec) */ + +/* Direction */ +#define BIG_SUR_GE_SEND 1 +#define BIG_SUR_GE_RECV 2 + +/* SG DMA */ +#define BIG_SUR_GE_SGDMA_NODELAY 0 /* start SG DMA immediately */ +#define BIG_SUR_GE_SGDMA_DELAY 1 /* do not start SG DMA */ + +#define BIG_SUR_GE_CFG_NO_IPIF 0 /* Not supported by the driver */ +#define BIG_SUR_GE_CFG_NO_DMA 1 /* No DMA */ +#define BIG_SUR_GE_CFG_SIMPLE_DMA 2 /* Simple DMA */ +#define BIG_SUR_GE_CFG_DMA_SG 3 /* DMA scatter gather */ + +#define BIG_SUR_GE_MAC_ADDR_SIZE 6 /* six-byte MAC address */ +#define BIG_SUR_GE_MTU 1500 /* max size of Ethernet frame */ +#define BIG_SUR_GE_HDR_SIZE 14 /* size of Ethernet header */ +#define BIG_SUR_GE_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */ +#define BIG_SUR_GE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */ +#define BIG_SUR_GE_MAX_FRAME_SIZE \ + (BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_SIZE + BIG_SUR_GE_TRL_SIZE) + +#define BIG_SUR_GE_MAX_VLAN_FRAME_SIZE \ + (BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_VLAN_SIZE + BIG_SUR_GE_TRL_SIZE) + +/* Send and Receive buffers */ +#define BIG_SUR_GE_MIN_RECV_BUFS 32 /* minimum # of recv buffers */ +#define BIG_SUR_GE_DFT_RECV_BUFS 64 /* default # of recv buffers */ + +#define BIG_SUR_GE_MIN_SEND_BUFS 16 /* minimum # of send buffers */ +#define BIG_SUR_GE_DFT_SEND_BUFS 32 /* default # of send buffers */ + +#define BIG_SUR_GE_MIN_BUFFERS (BIG_SUR_GE_MIN_RECV_BUFS + BIG_SUR_GE_MIN_SEND_BUFS) +#define BIG_SUR_GE_DFT_BUFFERS (BIG_SUR_GE_DFT_RECV_BUFS + BIG_SUR_GE_DFT_SEND_BUFS) + +/* Send and Receive Descriptors */ +#define BIG_SUR_GE_MIN_RECV_DESC 16 /* minimum # of recv descriptors */ +#define BIG_SUR_GE_DFT_RECV_DESC 32 /* default # of recv descriptors */ + +#define BIG_SUR_GE_MIN_SEND_DESC 8 /* minimum # of send descriptors */ +#define BIG_SUR_GE_DFT_SEND_DESC 16 /* default # of send descriptors */ + +/* FIFO Specific Defines */ +#define BIG_SUR_GE_READ_FIFO_TYPE 0 /* a read FIFO */ +#define BIG_SUR_GE_WRITE_FIFO_TYPE 1 /* a write FIFO */ +#define BIG_SUR_GE_RESET_REG_OFFSET 0UL +#define BIG_SUR_GE_MODULE_INFO_REG_OFFSET 0UL +#define BIG_SUR_GE_COUNT_STATUS_REG_OFFSET 4UL +#define BIG_SUR_GE_RESET_FIFO_MASK 0x0000000A +#define BIG_SUR_GE_COUNT_MASK 0x0000FFFF +#define BIG_SUR_GE_DEADLOCK_MASK 0x20000000 +#define BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK 0x40000000 +#define BIG_SUR_GE_EMPTY_FULL_MASK 0x80000000 + +#define BIG_SUR_GE_FIFO_RESET(fifo) \ + BIG_SUR_GE_WRITE((fifo)->reg_base_addr + BIG_SUR_GE_RESET_REG_OFFSET, BIG_SUR_GE_RESET_FIFO_MASK) + +#define BIG_SUR_GE_GET_COUNT(fifo) \ + (BIG_SUR_GE_READ((fifo)->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ + BIG_SUR_GE_COUNT_MASK) + +#define BIG_SUR_GE_IS_ALMOST_EMPTY(fifo) \ + (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ + BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK) + +#define BIG_SUR_GE_IS_ALMOST_FULL(fifo) \ + (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ + BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK) + +#define BIG_SUR_GE_IS_EMPTY(fifo) \ + (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ + BIG_SUR_GE_EMPTY_FULL_MASK) + +#define BIG_SUR_GE_IS_FULL(fifo) \ + (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ + BIG_SUR_GE_EMPTY_FULL_MASK) + +#define BIG_SUR_GE_IS_DEADLOCKED(fifo) \ + (BIG_SUR_GE_READ((fifo)->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \ + BIG_SUR_GE_DEADLOCK_MASK) + +/* Device Config */ +typedef struct _big_sur_ge_config { + u16 device_id; + u32 base_address; + u32 has_counters; + u32 has_sg_dma; + u8 dma_config; + u32 has_mii; +} big_sur_ge_config; + +#define BIG_SUR_GE_SIZE_IN_WORDS 10 +typedef unsigned long xbuf_descriptor[BIG_SUR_GE_SIZE_IN_WORDS]; + +/* Callback Functions */ +typedef void (*big_sur_sg_handler) (void *callback, xbuf_descriptor *desc, u32 num_desc); +typedef void (*big_sur_fifo_handler) (void *callback); +typedef void (*big_sur_irq_handler) (void *instance); + +typedef struct _xdma_channel_tag { + u32 reg_base_address; + u32 base_address; + u32 ready; + xbuf_descriptor *put_ptr; + xbuf_descriptor *get_ptr; + xbuf_descriptor *commit_ptr; + xbuf_descriptor *last_ptr; + + u32 total_desc_count; + u32 active_desc_count; +} xdma_channel; + +typedef struct _packet_fifo { + u32 reg_base_addr; + u32 ready_status; + u32 data_base_address; +} packet_fifo; + + +/* Big Sur GE driver structure */ +typedef struct _big_sur_ge { + u32 base_address; + u32 started; + u32 ready; + u32 polled; + u32 dma_sg; + + u8 dma_config; + u32 has_mii; + u32 has_mcast_hash_table; + + /* For the FIFO and simple DMA case only */ + packet_fifo recv_fifo; + packet_fifo send_fifo; + + big_sur_fifo_handler big_sur_ge_fifo_recv_handler; + big_sur_fifo_handler big_sur_ge_fifo_send_handler; + + void *fifo_send_ref; + void *fifo_recv_ref; + + /* For SG DMA only */ + xdma_channel recv_channel; + xdma_channel send_channel; +} big_sur_ge; + +/* Offset of the MAC registers from the IPIF base address */ +#define BIG_SUR_GE_REG_OFFSET 0x1100UL + +/* + * Register offsets for the Ethernet MAC. Each register is 32 bits. + */ +#define BIG_SUR_GE_EMIR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x0) /* EMAC Module ID */ +#define BIG_SUR_GE_ECR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x4) /* MAC Control */ +#define BIG_SUR_GE_IFGP_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x8) /* Interframe Gap */ +#define BIG_SUR_GE_SAH_OFFSET (BIG_SUR_GE_REG_OFFSET + 0xC) /* Station addr, high */ +#define BIG_SUR_GE_SAL_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x10) /* Station addr, low */ +#define BIG_SUR_GE_MGTCR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x14) /* MII mgmt control */ +#define BIG_SUR_GE_MGTDR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x18) /* MII mgmt data */ +#define BIG_SUR_GE_RPLR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x1C) /* Rx packet length */ +#define BIG_SUR_GE_TPLR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x20) /* Tx packet length */ +#define BIG_SUR_GE_TSR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x24) /* Tx status */ +#define BIG_SUR_GE_RMFC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x28) /* Rx missed frames */ +#define BIG_SUR_GE_RCC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x2C) /* Rx collisions */ +#define BIG_SUR_GE_RFCSEC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x30) /* Rx FCS errors */ +#define BIG_SUR_GE_RAEC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x34) /* Rx alignment errors */ +#define BIG_SUR_GE_TEDC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x38) /* Transmit excess + * deferral cnt */ +/* + * Register offsets for the IPIF components + */ +#define BIG_SUR_GE_ISR_OFFSET 0x20UL /* Interrupt status */ + +#define BIG_SUR_GE_DMA_OFFSET 0x2300UL +#define BIG_SUR_GE_DMA_SEND_OFFSET (BIG_SUR_GE_DMA_OFFSET + 0x0) /* DMA send channel */ +#define BIG_SUR_GE_DMA_RECV_OFFSET (BIG_SUR_GE_DMA_OFFSET + 0x40) /* DMA recv channel */ + +#define BIG_SUR_GE_PFIFO_OFFSET 0x2000UL +#define BIG_SUR_GE_PFIFO_TXREG_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x0) /* Tx registers */ +#define BIG_SUR_GE_PFIFO_RXREG_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x10) /* Rx registers */ +#define BIG_SUR_GE_PFIFO_TXDATA_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x100) /* Tx keyhole */ +#define BIG_SUR_GE_PFIFO_RXDATA_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x200) /* Rx keyhole */ + +/* + * EMAC Module Identification Register (EMIR) + */ +#define BIG_SUR_GE_EMIR_VERSION_MASK 0xFFFF0000UL /* Device version */ +#define BIG_SUR_GE_EMIR_TYPE_MASK 0x0000FF00UL /* Device type */ + +/* + * EMAC Control Register (ECR) + */ +#define BIG_SUR_GE_ECR_FULL_DUPLEX_MASK 0x80000000 /* Full duplex mode */ +#define BIG_SUR_GE_ECR_XMIT_RESET_MASK 0x40000000 /* Reset transmitter */ +#define BIG_SUR_GE_ECR_XMIT_ENABLE_MASK 0x20000000 /* Enable transmitter */ +#define BIG_SUR_GE_ECR_RECV_RESET_MASK 0x10000000 /* Reset receiver */ +#define BIG_SUR_GE_ECR_RECV_ENABLE_MASK 0x08000000 /* Enable receiver */ +#define BIG_SUR_GE_ECR_PHY_ENABLE_MASK 0x04000000 /* Enable PHY */ +#define BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK 0x02000000 /* Enable xmit pad insert */ +#define BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK 0x01000000 /* Enable xmit FCS insert */ +#define BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK 0x00800000 /* Enable xmit source addr insertion */ +#define BIG_SUR_GE_ECR_XMIT_ERROR_INSERT_MASK 0x00400000 /* Insert xmit error */ +#define BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK 0x00200000 /* Enable xmit source addr overwrite */ +#define BIG_SUR_GE_ECR_LOOPBACK_MASK 0x00100000 /* Enable internal loopback */ +#define BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK 0x00080000 /* Enable recv pad strip */ +#define BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK 0x00040000 /* Enable recv FCS strip */ +#define BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK 0x00080000 /* Enable recv pad/fcs strip */ +#define BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK 0x00020000 /* Enable unicast addr */ +#define BIG_SUR_GE_ECR_MULTI_ENABLE_MASK 0x00010000 /* Enable multicast addr */ +#define BIG_SUR_GE_ECR_BROAD_ENABLE_MASK 0x00008000 /* Enable broadcast addr */ +#define BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK 0x00004000 /* Enable promiscuous mode */ +#define BIG_SUR_GE_ECR_RECV_ALL_MASK 0x00002000 /* Receive all frames */ +#define BIG_SUR_GE_ECR_RESERVED2_MASK 0x00001000 /* Reserved */ +#define BIG_SUR_GE_ECR_MULTI_HASH_ENABLE_MASK 0x00000800 /* Enable multicast hash */ +#define BIG_SUR_GE_ECR_PAUSE_FRAME_MASK 0x00000400 /* Interpret pause frames */ +#define BIG_SUR_GE_ECR_CLEAR_HASH_MASK 0x00000200 /* Clear hash table */ +#define BIG_SUR_GE_ECR_ADD_HASH_ADDR_MASK 0x00000100 /* Add hash table address */ + +/* + * Interframe Gap Register (IFGR) + */ +#define BIG_SUR_GE_IFGP_PART1_MASK 0xF8000000 /* Interframe Gap Part1 */ +#define BIG_SUR_GE_IFGP_PART1_SHIFT 27 +#define BIG_SUR_GE_IFGP_PART2_MASK 0x07C00000 /* Interframe Gap Part2 */ +#define BIG_SUR_GE_IFGP_PART2_SHIFT 22 + +/* + * Station Address High Register (SAH) + */ +#define BIG_SUR_GE_SAH_ADDR_MASK 0x0000FFFF /* Station address high bytes */ + +/* + * Station Address Low Register (SAL) + */ +#define BIG_SUR_GE_SAL_ADDR_MASK 0xFFFFFFFF /* Station address low bytes */ + +/* + * MII Management Control Register (MGTCR) + */ +#define BIG_SUR_GE_MGTCR_START_MASK 0x80000000 /* Start/Busy */ +#define BIG_SUR_GE_MGTCR_RW_NOT_MASK 0x40000000 /* Read/Write Not (direction) */ +#define BIG_SUR_GE_MGTCR_PHY_ADDR_MASK 0x3E000000 /* PHY address */ +#define BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT 25 /* PHY address shift */ +#define BIG_SUR_GE_MGTCR_REG_ADDR_MASK 0x01F00000 /* Register address */ +#define BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT 20 /* Register addr shift */ +#define BIG_SUR_GE_MGTCR_MII_ENABLE_MASK 0x00080000 /* Enable MII from EMAC */ +#define BIG_SUR_GE_MGTCR_RD_ERROR_MASK 0x00040000 /* MII mgmt read error */ + +/* + * MII Management Data Register (MGTDR) + */ +#define BIG_SUR_GE_MGTDR_DATA_MASK 0x0000FFFF /* MII data */ + +/* + * Receive Packet Length Register (RPLR) + */ +#define BIG_SUR_GE_RPLR_LENGTH_MASK 0x0000FFFF /* Receive packet length */ + +/* + * Transmit Packet Length Register (TPLR) + */ +#define BIG_SUR_GE_TPLR_LENGTH_MASK 0x0000FFFF /* Transmit packet length */ + +/* + * Transmit Status Register (TSR) + */ +#define BIG_SUR_GE_TSR_EXCESS_DEFERRAL_MASK 0x80000000 /* Transmit excess deferral */ +#define BIG_SUR_GE_TSR_FIFO_UNDERRUN_MASK 0x40000000 /* Packet FIFO underrun */ +#define BIG_SUR_GE_TSR_ATTEMPTS_MASK 0x3E000000 /* Transmission attempts */ +#define BIG_SUR_GE_TSR_LATE_COLLISION_MASK 0x01000000 /* Transmit late collision */ + +/* + * Receive Missed Frame Count (RMFC) + */ +#define BIG_SUR_GE_RMFC_DATA_MASK 0x0000FFFF + +/* + * Receive Collision Count (RCC) + */ +#define BIG_SUR_GE_RCC_DATA_MASK 0x0000FFFF +/* + * Receive FCS Error Count (RFCSEC) + */ +#define BIG_SUR_GE_RFCSEC_DATA_MASK 0x0000FFFF + +/* + * Receive Alignment Error Count (RALN) + */ +#define BIG_SUR_GE_RAEC_DATA_MASK 0x0000FFFF + +/* + * Transmit Excess Deferral Count (TEDC) + */ +#define BIG_SUR_GE_TEDC_DATA_MASK 0x0000FFFF + +/* + * EMAC Interrupt Registers (Status and Enable) masks. These registers are + * part of the IPIF IP Interrupt registers + */ +#define BIG_SUR_GE_EIR_XMIT_DONE_MASK 0x00000001 /* Xmit complete */ +#define BIG_SUR_GE_EIR_RECV_DONE_MASK 0x00000002 /* Recv complete */ +#define BIG_SUR_GE_EIR_XMIT_ERROR_MASK 0x00000004 /* Xmit error */ +#define BIG_SUR_GE_EIR_RECV_ERROR_MASK 0x00000008 /* Recv error */ +#define BIG_SUR_GE_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010 /* Xmit status fifo empty */ +#define BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020 /* Recv length fifo empty */ +#define BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK 0x00000040 /* Xmit length fifo full */ +#define BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK 0x00000080 /* Recv length fifo overrun */ +#define BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK 0x00000100 /* Recv length fifo underrun */ +#define BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK 0x00000200 /* Xmit status fifo overrun */ +#define BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400 /* Transmit status fifo underrun */ +#define BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK 0x00000800 /* Transmit length fifo overrun */ +#define BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000 /* Transmit length fifo underrun */ +#define BIG_SUR_GE_EIR_XMIT_PAUSE_MASK 0x00002000 /* Transmit pause pkt received */ +#define BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK 0x00004000 /* Receive data fifo overrun */ +#define BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK 0x00008000 /* Receive missed frame error */ +#define BIG_SUR_GE_EIR_RECV_COLLISION_MASK 0x00010000 /* Receive collision error */ +#define BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK 0x00020000 /* Receive FCS error */ +#define BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK 0x00040000 /* Receive length field error */ +#define BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK 0x00080000 /* Receive short frame error */ +#define BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK 0x00100000 /* Receive long frame error */ +#define BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK 0x00200000 /* Receive alignment error */ + +#define BIG_SUR_GE_READ_REG(base_addr, reg_offset) \ + BIG_SUR_GE_READ(base_addr + reg_offset) + +#define BIG_SUR_GE_WRITE_REG(base_addr, reg_offset, data) \ + BIG_SUR_GE_WRITE(base_addr + reg_offset, data) + +#define BIG_SUR_GE_CONTROL_REG(base_addr, mask) \ + BIG_SUR_GE_WRITE(base_addr + BIG_SUR_GE_ECR_OFFSET, mask) + +/* Set the MAC Address */ +#define big_sur_ge_set_mac(base_addr, address) \ +{ \ + u32 mac_addr; \ + \ + mac_addr = ((address[0] << 8) | (address[1]); \ + BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_SAH_OFFSET, mac_address); \ + \ + mac_addr = ((address[2] << 24) | (address[3] << 16) | \ + (address[4] << 8) | address[5]); \ + \ + BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_SAL_OFFSET, mac_address); \ + \ +} + +/* Enable the MAC unit */ +#define big_sur_ge_mac_enable(base_address) \ +{ \ + u32 control; \ + control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET); \ + control &= ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK | BIG_SUR_GE_ECR_RECV_RESET_MASK); \ + control |= (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK); \ + BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \ +} + +/* Disable the MAC unit */ +#define big_sur_ge_mac_disable(base_address) \ +{ \ + u32 control; \ + control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET); \ + control &= ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK); \ + BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \ +} + +/* Check if the Tx is done */ +#define big_sur_ge_tx_done(base_address) \ + (BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) & BIG_SUR_GE_EIR_XMIT_DONE_MASK) + + +/* Check if Rx FIFO is empty */ +#define big_sur_ge_rx_empty(base_address) \ + (!(BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) & BIG_SUR_GE_EIR_RECV_DONE_MASK)) + +/* Reset the MAC PHY */ +#define big_sur_ge_reset_phy(base_address) \ +{ \ + u32 control; \ + control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET); \ + control &= ~(BIG_SUR_GE_ECR_PHY_ENABLE_MASK); \ + BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \ + control |= BIG_SUR_GE_ECR_PHY_ENABLE_MASK; \ + BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \ +} + +/* DMA SG defines */ +#define BIG_SUR_GE_CONTROL_LAST_BD_MASK 0x02000000 +#define BIG_SUR_GE_STATUS_LAST_BD_MASK 0x10000000 +#define BIG_SUR_GE_RST_REG_OFFSET 0 /* reset register */ +#define BIG_SUR_GE_MI_REG_OFFSET 0 /* module information register */ +#define BIG_SUR_GE_DMAC_REG_OFFSET 4 /* DMA control register */ +#define BIG_SUR_GE_SA_REG_OFFSET 8 /* source address register */ +#define BIG_SUR_GE_DA_REG_OFFSET 12 /* destination address register */ +#define BIG_SUR_GE_LEN_REG_OFFSET 16 /* length register */ +#define BIG_SUR_GE_DMAS_REG_OFFSET 20 /* DMA status register */ +#define BIG_SUR_GE_BDA_REG_OFFSET 24 /* buffer descriptor address register */ +#define BIG_SUR_GE_SWCR_REG_OFFSET 28 /* software control register */ +#define BIG_SUR_GE_UPC_REG_OFFSET 32 /* unserviced packet count register */ +#define BIG_SUR_GE_PCT_REG_OFFSET 36 /* packet count threshold register */ +#define BIG_SUR_GE_PWB_REG_OFFSET 40 /* packet wait bound register */ +#define BIG_SUR_GE_IS_REG_OFFSET 44 /* interrupt status register */ +#define BIG_SUR_GE_IE_REG_OFFSET 48 /* interrupt enable register */ + +#define BIG_SUR_GE_RESET_MASK 0x0000000A + +/* Buffer Descriptor Control */ + +#define BIG_SUR_GE_DEVICE_STATUS_OFFSET 0 +#define BIG_SUR_GE_CONTROL_OFFSET 1 +#define BIG_SUR_GE_SOURCE_OFFSET 2 +#define BIG_SUR_GE_DESTINATION_OFFSET 3 +#define BIG_SUR_GE_LENGTH_OFFSET 4 +#define BIG_SUR_GE_STATUS_OFFSET 5 +#define BIG_SUR_GE_NEXT_PTR_OFFSET 6 +#define BIG_SUR_GE_ID_OFFSET 7 +#define BIG_SUR_GE_FLAGS_OFFSET 8 +#define BIG_SUR_GE_RQSTED_LENGTH_OFFSET 9 + +#define BIG_SUR_GE_FLAGS_LOCKED_MASK 1 + +#define xbuf_descriptor_init(base) \ +{ \ + (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) = 0); \ + (*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET) = 0); \ + (*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET) = 0); \ + (*((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET) = 0); \ + (*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) = 0); \ + (*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET) = 0); \ + (*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET) = 0); \ + (*((u32 *)base + BIG_SUR_GE_ID_OFFSET) = 0); \ + (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) = 0); \ + (*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) = 0); \ +} + +#define xbuf_descriptor_GetControl(base) \ + (u32)(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET)) + +#define xbuf_descriptor_SetControl(base, Control) \ + (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) = (u32)Control) + +#define xbuf_descriptor_IsLastControl(base) \ + (u32)(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) & \ + BIG_SUR_GE_CONTROL_LAST_BD_MASK) + +#define xbuf_descriptor_SetLast(base) \ + (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) |= BIG_SUR_GECONTROL_LAST_BD_MASK) + +#define xbuf_descriptor_GetSrcAddress(base) \ + ((u32 *)(*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET))) + +#define xbuf_descriptor_SetSrcAddress(base, Source) \ + (*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET) = (u32)Source) + +#define xbuf_descriptor_GetDestAddress(base) \ + ((u32 *)(*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET))) + +#define xbuf_descriptor_SetDestAddress(base, Destination) \ + (*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET) = (u32)Destination) + +#define xbuf_descriptor_GetLength(base) \ + (u32)(*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) - \ + *((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET)) + +#define xbuf_descriptor_SetLength(base, Length) \ +{ \ + (*((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET) = (u32)(Length)); \ + (*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) = (u32)(Length));\ +} + +#define xbuf_descriptor_GetStatus(base) \ + (u32)(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET)) + +#define xbuf_descriptor_SetStatus(base, Status) \ + (*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) = (u32)Status) + +#define xbuf_descriptor_IsLastStatus(base) \ + (u32)(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) & \ + BIG_SUR_GE_STATUS_LAST_BD_MASK) + +#define xbuf_descriptor_GetDeviceStatus(base) \ + ((u32)(*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET))) + +#define xbuf_descriptor_SetDeviceStatus(base, Status) \ + (*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET) = (u32)Status) + +#define xbuf_descriptor_GetNextPtr(base) \ + (xbuf_descriptor *)(*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET)) + +#define xbuf_descriptor_SetNextPtr(base, NextPtr) \ + (*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET) = (u32)NextPtr) + +#define xbuf_descriptor_GetId(base) \ + (u32)(*((u32 *)base + BIG_SUR_GE_ID_OFFSET)) + +#define xbuf_descriptor_SetId(base, Id) \ + (*((u32 *)base + BIG_SUR_GE_ID_OFFSET) = (u32)Id) + +#define xbuf_descriptor_GetFlags(base) \ + (u32)(*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET)) + +#define xbuf_descriptor_SetFlags(base, Flags) \ + (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) = (u32)Flags) + +#define xbuf_descriptor_Lock(base) \ + (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) |= BIG_SUR_GE_FLAGS_LOCKED_MASK) + +#define xbuf_descriptor_Unlock(base) \ + (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) &= ~BIG_SUR_GE_FLAGS_LOCKED_MASK) + +#define xbuf_descriptor_IsLocked(base) \ + (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) & BIG_SUR_GE_FLAGS_LOCKED_MASK) + +#define BIG_SUR_GE_DMACR_SOURCE_INCR_MASK 0x80000000UL /* increment source address */ +#define BIG_SUR_GE_DMACR_DEST_INCR_MASK 0x40000000UL /* increment dest address */ +#define BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK 0x20000000UL /* local source address */ +#define BIG_SUR_GE_DMACR_DEST_LOCAL_MASK 0x10000000UL /* local dest address */ +#define BIG_SUR_GE_DMACR_SG_DISABLE_MASK 0x08000000UL /* scatter gather disable */ +#define BIG_SUR_GE_DMACR_GEN_BD_INTR_MASK 0x04000000UL /* descriptor interrupt */ +#define BIG_SUR_GE_DMACR_LAST_BD_MASK BIG_SUR_GE_CONTROL_LAST_BD_MASK /* last buffer */ +#define BIG_SUR_GE_DMASR_BUSY_MASK 0x80000000UL /* channel is busy */ +#define BIG_SUR_GE_DMASR_BUS_ERROR_MASK 0x40000000UL /* bus error occurred */ +#define BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK 0x20000000UL /* bus timeout occurred */ +#define BIG_SUR_GE_DMASR_LAST_BD_MASK BIG_SUR_GE_STATUS_LAST_BD_MASK /* last buffer */ +#define BIG_SUR_GE_DMASR_SG_BUSY_MASK 0x08000000UL /* scatter gather is busy */ +#define BIG_SUR_GE_IXR_DMA_DONE_MASK 0x1UL /* dma operation done */ +#define BIG_SUR_GE_IXR_DMA_ERROR_MASK 0x2UL /* dma operation error */ +#define BIG_SUR_GE_IXR_PKT_DONE_MASK 0x4UL /* packet done */ +#define BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK 0x8UL /* packet count threshold */ +#define BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK 0x10UL /* packet wait bound reached */ +#define BIG_SUR_GE_IXR_SG_DISABLE_ACK_MASK 0x20UL /* scatter gather disable + acknowledge occurred */ +#define BIG_SUR_GEIXR_SG_END_MASK 0x40UL /* last buffer descriptor + disabled scatter gather */ +#define BIG_SUR_GEIXR_BD_MASK 0x80UL /* buffer descriptor done */ + +/* BD control */ +#define BIG_SUR_GE_DFT_SEND_BD_MASK (BIG_SUR_GEDMACR_SOURCE_INCR_MASK | \ + BIG_SUR_GEDMACR_DEST_LOCAL_MASK) +#define BIG_SUR_GE_DFT_RECV_BD_MASK (BIG_SUR_GEDMACR_DEST_INCR_MASK | \ + BIG_SUR_GEDMACR_SOURCE_LOCAL_MASK) + +/* Interrupts */ +#define BIG_SUR_GE_IPIF_EMAC_MASK 0x00000004UL /* MAC interrupt */ +#define BIG_SUR_GE_IPIF_SEND_DMA_MASK 0x00000008UL /* Send DMA interrupt */ +#define BIG_SUR_GE_IPIF_RECV_DMA_MASK 0x00000010UL /* Receive DMA interrupt */ +#define BIG_SUR_GE_IPIF_RECV_FIFO_MASK 0x00000020UL /* Receive FIFO interrupt */ +#define BIG_SUR_GE_IPIF_SEND_FIFO_MASK 0x00000040UL /* Send FIFO interrupt */ + +#define BIG_SUR_GE_IPIF_DMA_DFT_MASK (BIG_SUR_GE_IPIF_SEND_DMA_MASK | \ + BIG_SUR_GE_IPIF_RECV_DMA_MASK | \ + BIG_SUR_GE_IPIF_EMAC_MASK | \ + BIG_SUR_GE_IPIF_SEND_FIFO_MASK | \ + BIG_SUR_GE_IPIF_RECV_FIFO_MASK) + +#define BIG_SUR_GE_IPIF_FIFO_DFT_MASK (BIG_SUR_GE_IPIF_EMAC_MASK | \ + BIG_SUR_GE_IPIF_SEND_FIFO_MASK | \ + BIG_SUR_GE_IPIF_RECV_FIFO_MASK) + +#define BIG_SUR_GE_IPIF_DMA_DEV_INTR_COUNT 7 /* Number of interrupt sources */ +#define BIG_SUR_GE_IPIF_FIFO_DEV_INTR_COUNT 5 /* Number of interrupt sources */ +#define BIG_SUR_GE_IPIF_DEVICE_INTR_COUNT 7 /* Number of interrupt sources */ +#define BIG_SUR_GE_IPIF_IP_INTR_COUNT 22 /* Number of MAC interrupts */ + +/* a mask for all transmit interrupts, used in polled mode */ +#define BIG_SUR_GE_EIR_XMIT_ALL_MASK (BIG_SUR_GE_EIR_XMIT_DONE_MASK | \ + BIG_SUR_GE_EIR_XMIT_ERROR_MASK | \ + BIG_SUR_GE_EIR_XMIT_SFIFO_EMPTY_MASK | \ + BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK) + +/* a mask for all receive interrupts, used in polled mode */ +#define BIG_SUR_GE_EIR_RECV_ALL_MASK (BIG_SUR_GE_EIR_RECV_DONE_MASK | \ + BIG_SUR_GE_EIR_RECV_ERROR_MASK | \ + BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK | \ + BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK | \ + BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK | \ + BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK | \ + BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK | \ + BIG_SUR_GE_EIR_RECV_COLLISION_MASK | \ + BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK | \ + BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK | \ + BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK | \ + BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK | \ + BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK) + +/* a default interrupt mask for scatter-gather DMA operation */ +#define BIG_SUR_GE_EIR_DFT_SG_MASK (BIG_SUR_GE_EIR_RECV_ERROR_MASK | \ + BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK | \ + BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK | \ + BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK | \ + BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK | \ + BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK | \ + BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK | \ + BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK | \ + BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK | \ + BIG_SUR_GE_EIR_RECV_COLLISION_MASK | \ + BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK | \ + BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK | \ + BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK | \ + BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK | \ + BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK) + +/* a default interrupt mask for non-DMA operation (direct FIFOs) */ +#define BIG_SUR_GE_EIR_DFT_FIFO_MASK (BIG_SUR_GE_EIR_XMIT_DONE_MASK | \ + BIG_SUR_GE_EIR_RECV_DONE_MASK | \ + BIG_SUR_GE_EIR_DFT_SG_MASK) + +#define BIG_SUR_GE_DMA_SG_INTR_MASK (BIG_SUR_GEIXR_DMA_ERROR_MASK | \ + BIG_SUR_GEIXR_PKT_THRESHOLD_MASK | \ + BIG_SUR_GEIXR_PKT_WAIT_BOUND_MASK | \ + BIG_SUR_GEIXR_SG_END_MASK) + +#endif diff -Naur linux-2.6.12.6.orig/drivers/net/declance.c linux-2.6.12.6/drivers/net/declance.c --- linux-2.6.12.6.orig/drivers/net/declance.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/declance.c 2005-10-02 23:47:38.000000000 +0000 @@ -5,7 +5,7 @@ * * adopted from sunlance.c by Richard van den Berg * - * Copyright (C) 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki * * additional sources: * - PMAD-AA TURBOchannel Ethernet Module Functional Specification, @@ -57,13 +57,15 @@ #include #include +#include + #include #include #include #include #include +#include #include -#include static char version[] __devinitdata = "declance.c: v0.009 by Linux MIPS DECstation task force\n"; @@ -79,10 +81,6 @@ #define PMAD_LANCE 2 #define PMAX_LANCE 3 -#ifndef CONFIG_TC -unsigned long system_base; -unsigned long dmaptr; -#endif #define LE_CSR0 0 #define LE_CSR1 1 @@ -237,7 +235,7 @@ /* * This works *only* for the ring descriptors */ -#define LANCE_ADDR(x) (PHYSADDR(x) >> 1) +#define LANCE_ADDR(x) (CPHYSADDR(x) >> 1) struct lance_private { struct net_device *next; @@ -697,16 +695,17 @@ spin_unlock(&lp->lock); } -static void lance_dma_merr_int(const int irq, void *dev_id, - struct pt_regs *regs) +static irqreturn_t lance_dma_merr_int(const int irq, void *dev_id, + struct pt_regs *regs) { struct net_device *dev = (struct net_device *) dev_id; printk("%s: DMA error\n", dev->name); + return IRQ_HANDLED; } -static irqreturn_t -lance_interrupt(const int irq, void *dev_id, struct pt_regs *regs) +static irqreturn_t lance_interrupt(const int irq, void *dev_id, + struct pt_regs *regs) { struct net_device *dev = (struct net_device *) dev_id; struct lance_private *lp = netdev_priv(dev); @@ -1026,10 +1025,6 @@ unsigned long esar_base; unsigned char *esar; -#ifndef CONFIG_TC - system_base = KN01_LANCE_BASE; -#endif - if (dec_lance_debug && version_printed++ == 0) printk(version); @@ -1062,16 +1057,16 @@ switch (type) { #ifdef CONFIG_TC case ASIC_LANCE: - dev->base_addr = system_base + IOASIC_LANCE; + dev->base_addr = CKSEG1ADDR(dec_kn_slot_base + IOASIC_LANCE); /* buffer space for the on-board LANCE shared memory */ /* * FIXME: ugly hack! */ - dev->mem_start = KSEG1ADDR(0x00020000); + dev->mem_start = CKSEG1ADDR(0x00020000); dev->mem_end = dev->mem_start + 0x00020000; dev->irq = dec_interrupt[DEC_IRQ_LANCE]; - esar_base = system_base + IOASIC_ESAR; + esar_base = CKSEG1ADDR(dec_kn_slot_base + IOASIC_ESAR); /* Workaround crash with booting KN04 2.1k from Disk */ memset((void *)dev->mem_start, 0, @@ -1101,14 +1096,14 @@ /* Setup I/O ASIC LANCE DMA. */ lp->dma_irq = dec_interrupt[DEC_IRQ_LANCE_MERR]; ioasic_write(IO_REG_LANCE_DMA_P, - PHYSADDR(dev->mem_start) << 3); + CPHYSADDR(dev->mem_start) << 3); break; case PMAD_LANCE: claim_tc_card(slot); - dev->mem_start = get_tc_base_addr(slot); + dev->mem_start = CKSEG1ADDR(get_tc_base_addr(slot)); dev->base_addr = dev->mem_start + 0x100000; dev->irq = get_tc_irq_nr(slot); esar_base = dev->mem_start + 0x1c0002; @@ -1137,9 +1132,9 @@ case PMAX_LANCE: dev->irq = dec_interrupt[DEC_IRQ_LANCE]; - dev->base_addr = KN01_LANCE_BASE; - dev->mem_start = KN01_LANCE_BASE + 0x01000000; - esar_base = KN01_RTC_BASE + 1; + dev->base_addr = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE); + dev->mem_start = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE_MEM); + esar_base = CKSEG1ADDR(KN01_SLOT_BASE + KN01_ESAR + 1); lp->dma_irq = -1; /* @@ -1260,7 +1255,7 @@ return 0; err_out_free_dev: - kfree(dev); + free_netdev(dev); err_out: return ret; @@ -1306,6 +1301,7 @@ while (root_lance_dev) { struct net_device *dev = root_lance_dev; struct lance_private *lp = netdev_priv(dev); + unregister_netdev(dev); #ifdef CONFIG_TC if (lp->slot >= 0) diff -Naur linux-2.6.12.6.orig/drivers/net/gt64240eth.c linux-2.6.12.6/drivers/net/gt64240eth.c --- linux-2.6.12.6.orig/drivers/net/gt64240eth.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/net/gt64240eth.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,1672 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2001 Patton Electronics Company + * Copyright (C) 2002 Momentum Computer + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * stevel@mvista.com or support@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Ethernet driver for the MIPS GT96100 Advanced Communication Controller. + * + * Modified for the Gallileo/Marvell GT-64240 Communication Controller. + * + * Support for Rx NAPI, Rx checksum offload, IOCTL and ETHTOOL added + * Manish Lachwani (lachwani@pmc-sierra.com) - 09/16/2003 + * + * Modified for later version of Linux 2.4 kernel + * Manish Lachwani (lachwani@pmc-sierra.com) - 04/29/2004 + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define DESC_DATA_BE 1 + +#include "gt64240eth.h" + +// enable this port (set hash size to 1/2K) +//- #define PORT_CONFIG pcrHS +#define PORT_CONFIG (pcrHS | pcrHD) +//- #define PORT_CONFIG pcrHS |pcrPM |pcrPBF|pcrHDM +//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS); +//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM); +//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM | 1< 2 some warnings such as queue full, ..... + * > 3 lots of change-of-state messages. + * > 4 EXTENSIVE data/descriptor dumps. + */ + +#ifdef GT64240_DEBUG +static int gt64240_debug = GT64240_DEBUG; +#else +static int gt64240_debug = 0; +#endif + +static int debug = -1; + +#define GT64240_MSG_ENABLE (NETIF_MSG_DRV | \ + NETIF_MSG_PROBE | \ + NETIF_MSG_LINK) + + +/********************************************************/ + +// prototypes +static void gt64240_delay(int msec); +static int gt64240_add_hash_entry(struct net_device *dev, + unsigned char *addr); +static void read_mib_counters(struct gt64240_private *gp); +static void dump_MII(struct net_device *dev); +static void dump_tx_desc(struct net_device *dev, int i); +static void dump_rx_desc(struct net_device *dev, int i); +static void dump_hw_addr(unsigned char *addr_str); +static void update_stats(struct gt64240_private *gp); +static void abort(struct net_device *dev, u32 abort_bits); +static void hard_stop(struct net_device *dev); +static void enable_ether_irq(struct net_device *dev); +static void disable_ether_irq(struct net_device *dev); +static int __init gt64240_probe1(unsigned long ioaddr, int irq, int port_num); +static void reset_tx(struct net_device *dev); +static void reset_rx(struct net_device *dev); +static int gt64240_init(struct net_device *dev); +static int gt64240_open(struct net_device *dev); +static int gt64240_close(struct net_device *dev); +static int gt64240_tx(struct sk_buff *skb, struct net_device *dev); +#ifdef GT64240_NAPI +static int gt64240_poll(struct net_device *dev, int *budget); +static int gt64240_rx(struct net_device *dev, u32 status, int budget); +#else +static int gt64240_rx(struct net_device *dev, u32 status); +#endif +static void gt64240_tx_timeout(struct net_device *dev); +static void gt64240_set_rx_mode(struct net_device *dev); +static struct net_device_stats *gt64240_get_stats(struct net_device *dev); + +extern char *__init prom_getcmdline(void); +extern int prom_get_mac_addrs(unsigned char + station_addr[NUM_INTERFACES][6]); + +static char version[] __devinitdata = + "gt64240eth.o: version 0.1, \n"; + +// PHY device addresses +static u32 gt64240_phy_addr[NUM_INTERFACES] __devinitdata = { 0x8, 0x1, 0xa }; + +// Need real Ethernet addresses -- in parse_mac_addr_options(), +// these will be replaced by prom_get_mac_addrs() and/or prom_getcmdline(). +static unsigned char gt64240_station_addr[NUM_INTERFACES][6] = { + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05}, + {0x01, 0x02, 0x03, 0x04, 0x05, 0x06}, + {0x02, 0x03, 0x04, 0x05, 0x06, 0x07} +}; + +static int max_interrupt_work = 32; + +/* + * Base address and interupt of the GT64240 ethernet controllers + */ +static struct { + unsigned int port; + int irq; +} gt64240_iflist[NUM_INTERFACES] = { + { + GT64240_ETH0_BASE, 8}, { + GT64240_ETH1_BASE, 8}, { + GT64240_ETH2_BASE, 8} +}; + +static void gt64240_delay(int ms) +{ + if (in_interrupt()) + return; + else { + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(ms * HZ / 1000); + } +} + +unsigned char prom_mac_addr_base[6]; + +int prom_get_mac_addrs(unsigned char station_addr[NUM_INTERFACES][6]) +{ + memcpy(station_addr[0], prom_mac_addr_base, 6); + memcpy(station_addr[1], prom_mac_addr_base, 6); + memcpy(station_addr[2], prom_mac_addr_base, 6); + + station_addr[1][5] += 1; + station_addr[2][5] += 2; + + return 0; +} + +void parse_mac_addr_options(void) +{ + prom_get_mac_addrs(gt64240_station_addr); +} + +static int read_MII(struct net_device *dev, int phy, int reg) +{ + int timedout = 20; + u32 smir = smirOpCode | (phy << smirPhyAdBit) | + (reg << smirRegAdBit); + + // wait for last operation to complete + while ((GT64240_READ(GT64240_ETH_SMI_REG)) & smirBusy) { + // snooze for 1 msec and check again + gt64240_delay(1); + + if (--timedout == 0) { + printk("%s: read_MII busy timeout!!\n", dev->name); + return -1; + } + } + + GT64240_WRITE(GT64240_ETH_SMI_REG, smir); + + timedout = 20; + // wait for read to complete + while (! + ((smir = + GT64240_READ(GT64240_ETH_SMI_REG)) & smirReadValid)) { + // snooze for 1 msec and check again + gt64240_delay(1); + + if (--timedout == 0) { + printk("%s: read_MII timeout!!\n", dev->name); + return -1; + } + } + + return (int) (smir & smirDataMask); +} + +static void gp_get_drvinfo (struct net_device *dev, + struct ethtool_drvinfo *info) +{ + strcpy(info->driver, "gt64260"); + strcpy(info->version, version); +} + +static int gp_get_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct gt64240_private *gp = netdev_priv(dev); + int rc; + + spin_lock_irq(&gp->lock); + rc = mii_ethtool_gset(&gp->mii_if, cmd); + spin_unlock_irq(&gp->lock); + return rc; +} + +static int gp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct gt64240_private *gp = netdev_priv(dev); + int rc; + + spin_lock_irq(&gp->lock); + rc = mii_ethtool_sset(&gp->mii_if, cmd); + spin_unlock_irq(&gp->lock); + return rc; +} + +static int gp_nway_reset(struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + return mii_nway_restart(&gp->mii_if); +} + +static u32 gp_get_link(struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + return mii_link_ok(&gp->mii_if); +} + +static u32 gp_get_msglevel(struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + return gp->msg_enable; +} + +static void gp_set_msglevel(struct net_device *dev, u32 value) +{ + struct gt64240_private *gp = netdev_priv(dev); + gp->msg_enable = value; +} + +static struct ethtool_ops gp_ethtool_ops = { + .get_drvinfo = gp_get_drvinfo, + .get_settings = gp_get_settings, + .set_settings = gp_set_settings, + .nway_reset = gp_nway_reset, + .get_link = gp_get_link, + .get_msglevel = gp_get_msglevel, + .set_msglevel = gp_set_msglevel, +}; + +static int gt64240_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + struct gt64240_private *gp = netdev_priv(dev); + struct mii_ioctl_data *data = + (struct mii_ioctl_data *) &rq->ifr_data; + int retval; + + if (!netif_running(dev)) + return -EINVAL; + + spin_lock_irq(&gp->lock); + retval = generic_mii_ioctl(&gp->mii_if, data, cmd, NULL); + spin_unlock_irq(&gp->lock); + + return retval; +} + +static void dump_tx_desc(struct net_device *dev, int i) +{ + struct gt64240_private *gp = netdev_priv(dev); + gt64240_td_t *td = &gp->tx_ring[i]; + + printk("%s:tx[%d]: self=%p cmd=%08x, cnt=%4d. bufp=%08x, next=%08x\n", + dev->name, i, td, td->cmdstat, td->byte_cnt, td->buff_ptr, + td->next); +} + +static void dump_rx_desc(struct net_device *dev, int i) +{ + struct gt64240_private *gp = netdev_priv(dev); + gt64240_rd_t *rd = &gp->rx_ring[i]; + + printk("%s:rx_dsc[%d]: self=%p cst=%08x,size=%4d. cnt=%4d. " + "bufp=%08x, next=%08x\n", + dev->name, i, rd, rd->cmdstat, rd->buff_sz, rd->byte_cnt, + rd->buff_ptr, rd->next); +} + +// These routines work, just disabled to avoid compile warnings +static void write_MII(struct net_device *dev, int phy, int reg, int data) +{ + u32 smir = (phy << smirPhyAdBit) | (reg << smirRegAdBit) | data; + int timedout = 20; + + // wait for last operation to complete + while (GT64240_READ(GT64240_ETH_SMI_REG) & smirBusy) { + // snooze for 1 msec and check again + gt64240_delay(1); + + if (--timedout == 0) { + printk("%s: write_MII busy timeout!!\n", + dev->name); + return; + } + } + + GT64240_WRITE(GT64240_ETH_SMI_REG, smir); +} + +static void dump_MII(struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + int i, val; + + for (i = 0; i < 7; i++) { + if ((val = read_MII(dev, gp->phy_addr, i)) >= 0) + printk("%s: MII Reg %d=%x\n", dev->name, i, val); + } + for (i = 16; i < 21; i++) { + if ((val = read_MII(dev, gp->phy_addr, i)) >= 0) + printk("%s: MII Reg %d=%x\n", dev->name, i, val); + } +} + + +static void dump_hw_addr(unsigned char *addr_str) +{ + int i; + for (i = 0; i < 6; i++) { + printk("%2.2x", addr_str[i]); + printk(i < 5 ? ":" : "\n"); + } +} + +static int gt64240_add_hash_entry(struct net_device *dev, + unsigned char *addr) +{ + static unsigned char swapped[256]; + struct gt64240_private *gp; + u32 value1, value0, *entry; + unsigned char hash_ea[6]; + static int flag = 0; + u16 hashResult; + int i; + + if (flag == 0) { /* Create table to swap bits in a byte */ + flag = 1; + for (i = 0; i < 256; i++) { + swapped[i] = (i & 0x01) << 7; + swapped[i] |= (i & 0x02) << 5; + swapped[i] |= (i & 0x04) << 3; + swapped[i] |= (i & 0x08) << 1; + swapped[i] |= (i & 0x10) >> 1; + swapped[i] |= (i & 0x20) >> 3; + swapped[i] |= (i & 0x40) >> 5; + swapped[i] |= (i & 0x80) >> 7; + } + } + + for (i = 0; i < 6; i++) { /* swap bits from mac to create hash mac */ + hash_ea[i] = swapped[addr[i]]; + } + + gp = netdev_priv(dev); + + /* create hash entry address */ + hashResult = (((hash_ea[5] >> 2) & 0x3F) << 9) & 0x7E00; + hashResult |= ((hash_ea[4] & 0x7F) << 2) | (hash_ea[5] & 0x03); + hashResult ^= + ((hash_ea[3] & 0xFF) << 1) | ((hash_ea[4] >> 7) & 0x01); + hashResult ^= ((hash_ea[1] & 0x01) << 8) | (hash_ea[2] & 0xFF); + + value0 = hteValid | hteRD; /* Create hash table entry value */ + value0 |= (u32) addr[0] << 3; + value0 |= (u32) addr[1] << 11; + value0 |= (u32) addr[2] << 19; + value0 |= ((u32) addr[3] & 0x1f) << 27; + + value1 = ((u32) addr[3] >> 5) & 0x07; + value1 |= (u32) addr[4] << 3; + value1 |= (u32) addr[5] << 11; + + /* Inset entry value into hash table */ + for (i = 0; i < HASH_HOP_NUMBER; i++) { + entry = (u32 *) ((u32) gp->hash_table + + (((u32) hashResult & 0x07ff) << 3)); + if ((*entry & hteValid) && !(*entry & hteSkip)) { + hashResult += 2; /* oops, occupied, go to next entry */ + } else { +#ifdef __LITTLE_ENDIAN + entry[1] = value1; + entry[0] = value0; +#else + entry[0] = value1; + entry[1] = value0; +#endif + break; + } + } + if (i >= HASH_HOP_NUMBER) { + printk("%s: gt64240_add_hash_entry expired!\n", dev->name); + return (-1); + } + return (0); +} + + +static void read_mib_counters(struct gt64240_private *gp) +{ + u32 *mib_regs = (u32 *) & gp->mib; + int i; + + for (i = 0; i < sizeof(mib_counters_t) / sizeof(u32); i++) + mib_regs[i] = + GT64240ETH_READ(gp, + GT64240_ETH_MIB_COUNT_BASE + + i * sizeof(u32)); +} + + +static void update_stats(struct gt64240_private *gp) +{ + mib_counters_t *mib = &gp->mib; + struct net_device_stats *stats = &gp->stats; + + read_mib_counters(gp); + + stats->rx_packets = mib->totalFramesReceived; + stats->tx_packets = mib->framesSent; + stats->rx_bytes = mib->totalByteReceived; + stats->tx_bytes = mib->byteSent; + stats->rx_errors = mib->totalFramesReceived - mib->framesReceived; + //the tx error counters are incremented by the ISR + //rx_dropped incremented by gt64240_rx + //tx_dropped incremented by gt64240_tx + stats->multicast = mib->multicastFramesReceived; + // collisions incremented by gt64240_tx_complete + stats->rx_length_errors = mib->oversizeFrames + mib->fragments; + // The RxError condition means the Rx DMA encountered a + // CPU owned descriptor, which, if things are working as + // they should, means the Rx ring has overflowed. + stats->rx_over_errors = mib->macRxError; + stats->rx_crc_errors = mib->cRCError; +} + +static void abort(struct net_device *dev, u32 abort_bits) +{ + struct gt64240_private *gp = netdev_priv(dev); + int timedout = 100; // wait up to 100 msec for hard stop to complete + + if (gt64240_debug > 3) + printk("%s: abort\n", dev->name); + + // Return if neither Rx or Tx abort bits are set + if (!(abort_bits & (sdcmrAR | sdcmrAT))) + return; + + // make sure only the Rx/Tx abort bits are set + abort_bits &= (sdcmrAR | sdcmrAT); + + spin_lock(&gp->lock); + + // abort any Rx/Tx DMA immediately + GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, abort_bits); + + if (gt64240_debug > 3) + printk("%s: abort: SDMA cmd = %x/%x\n", + dev->name, abort_bits, GT64240ETH_READ(gp, + GT64240_ETH_SDMA_COMM)); + + // wait for abort to complete + while ((GT64240ETH_READ(gp, GT64240_ETH_SDMA_COMM)) & abort_bits) { + // snooze for 20 msec and check again + gt64240_delay(1); + + if (--timedout == 0) { + printk("%s: abort timeout!!\n", dev->name); + break; + } + } + + spin_unlock(&gp->lock); +} + + +static void hard_stop(struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + + if (gt64240_debug > 3) + printk("%s: hard stop\n", dev->name); + + disable_ether_irq(dev); + + abort(dev, sdcmrAR | sdcmrAT); + + // disable port + GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, 0); + if (gt64240_debug > 3) + printk("%s: gt64240_hard_stop: Port Config=%x\n", + dev->name, GT64240ETH_READ(gp, + GT64240_ETH_PORT_CONFIG)); + +} + +static void gt64240_tx_complete(struct net_device *dev, u32 status) +{ + struct gt64240_private *gp = netdev_priv(dev); + int nextOut, cdp; + gt64240_td_t *td; + u32 cmdstat; + + cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_TX_DESC_PTR0) + - gp->tx_ring_dma) / sizeof(gt64240_td_t); + + if (gt64240_debug > 3) { /*+prk17aug01 */ + nextOut = gp->tx_next_out; + printk + ("%s: tx_complete: TX_PTR0=0x%08x, cdp=%d. nextOut=%d.\n", + dev->name, GT64240ETH_READ(gp, + GT64240_ETH_CURR_TX_DESC_PTR0), + cdp, nextOut); + td = &gp->tx_ring[nextOut]; + } + +/*** NEED to check and CLEAR these errors every time thru here: ***/ + if (gt64240_debug > 2) { + if (GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE)) + printk + ("%s: gt64240_tx_complete: CIU Cause=%08x, Mask=%08x, EAddr=%08x\n", + dev->name, + GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE), + GT64240_READ(COMM_UNIT_INTERRUPT_MASK), + GT64240_READ(COMM_UNIT_ERROR_ADDRESS)); + GT64240_WRITE(COMM_UNIT_INTERRUPT_CAUSE, 0); + } + // Continue until we reach the current descriptor pointer + for (nextOut = gp->tx_next_out; nextOut != cdp; + nextOut = (nextOut + 1) % TX_RING_SIZE) { + + if (--gp->intr_work_done == 0) + break; + + td = &gp->tx_ring[nextOut]; + cmdstat = td->cmdstat; + + if (cmdstat & (u32) txOwn) { + // DMA is not finished writing descriptor??? + // Leave and come back later to pick-up where we left off. + break; + } + // increment Tx error stats + if (cmdstat & (u32) txErrorSummary) { + if (gt64240_debug > 2) + printk + ("%s: tx_complete: Tx error, cmdstat = %x\n", + dev->name, cmdstat); + gp->stats.tx_errors++; + if (cmdstat & (u32) txReTxLimit) + gp->stats.tx_aborted_errors++; + if (cmdstat & (u32) txUnderrun) + gp->stats.tx_fifo_errors++; + if (cmdstat & (u32) txLateCollision) + gp->stats.tx_window_errors++; + } + + if (cmdstat & (u32) txCollision) + gp->stats.collisions += + (unsigned long) ((cmdstat & txReTxCntMask) >> + txReTxCntBit); + + // Wake the queue if the ring was full + if (gp->tx_full) { + gp->tx_full = 0; + if (gp->last_psr & psrLink) { + netif_wake_queue(dev); + } + } + // decrement tx ring buffer count + if (gp->tx_count) + gp->tx_count--; + + // free the skb + if (gp->tx_skbuff[nextOut]) { + if (gt64240_debug > 3) + printk + ("%s: tx_complete: good Tx, skb=%p\n", + dev->name, gp->tx_skbuff[nextOut]); + dev_kfree_skb_irq(gp->tx_skbuff[nextOut]); + gp->tx_skbuff[nextOut] = NULL; + } else { + printk("%s: tx_complete: no skb!\n", dev->name); + } + } + + gp->tx_next_out = nextOut; + + if ((status & icrTxEndLow) && gp->tx_count != 0) { + // we must restart the DMA + GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, + sdcmrERD | sdcmrTXDL); + } +} + +static irqreturn_t gt64240_interrupt(int irq, void *dev_id, + struct pt_regs *regs) +{ + struct net_device *dev = (struct net_device *) dev_id; + struct gt64240_private *gp = netdev_priv(dev); + u32 status; + + if (dev == NULL) { + printk("%s: isr: null dev ptr\n", dev->name); + return IRQ_NONE; + } + + spin_lock(&gp->lock); + + if (gt64240_debug > 3) + printk("%s: isr: entry\n", dev->name); + + gp->intr_work_done = max_interrupt_work; + + while (gp->intr_work_done > 0) { + + status = GT64240ETH_READ(gp, GT64240_ETH_INT_CAUSE); +#ifdef GT64240_NAPI + /* dont ack Rx interrupts */ + if (!(status & icrRxBuffer)) + GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0); +#else + // ACK interrupts + GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0); +#endif + + if (gt64240_debug > 3) + printk("%s: isr: work=%d., icr=%x\n", dev->name, + gp->intr_work_done, status); + + if ((status & icrEtherIntSum) == 0) { + if (!(status & + (icrTxBufferLow | icrTxBufferHigh | + icrRxBuffer))) { + /* exit from the while() loop */ + break; + } + } + + if (status & icrMIIPhySTC) { + u32 psr = + GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS); + if (gp->last_psr != psr) { + printk("%s: port status: 0x%08x\n", + dev->name, psr); + printk + ("%s: %s MBit/s, %s-duplex, flow-control %s, link is %s,\n", + dev->name, + psr & psrSpeed ? "100" : "10", + psr & psrDuplex ? "full" : "half", + psr & psrFctl ? "disabled" : + "enabled", + psr & psrLink ? "up" : "down"); + printk + ("%s: TxLowQ is %s, TxHighQ is %s, Transmitter is %s\n", + dev->name, + psr & psrTxLow ? "running" : + "stopped", + psr & psrTxHigh ? "running" : + "stopped", + psr & psrTxInProg ? "on" : "off"); + + if ((psr & psrLink) && !gp->tx_full && + netif_queue_stopped(dev)) { + printk + ("%s: isr: Link up, waking queue.\n", + dev->name); + netif_wake_queue(dev); + } else if (!(psr & psrLink) + && !netif_queue_stopped(dev)) { + printk + ("%s: isr: Link down, stopping queue.\n", + dev->name); + netif_stop_queue(dev); + } + + gp->last_psr = psr; + } + } + + if (status & (icrTxBufferLow | icrTxEndLow)) + gt64240_tx_complete(dev, status); + + if (status & icrRxBuffer) { +#ifdef GT64240_NAPI + if (netif_rx_schedule_prep(dev)) { + disable_ether_irq(dev); + __netif_rx_schedule(dev); + } +#else + gt64240_rx(dev, status); +#endif + } + // Now check TX errors (RX errors were handled in gt64240_rx) + if (status & icrTxErrorLow) { + printk("%s: isr: Tx resource error\n", dev->name); + } + + if (status & icrTxUdr) { + printk("%s: isr: Tx underrun error\n", dev->name); + } + } + + if (gp->intr_work_done == 0) { + // ACK any remaining pending interrupts + GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0); + if (gt64240_debug > 3) + printk("%s: isr: hit max work\n", dev->name); + } + + if (gt64240_debug > 3) + printk("%s: isr: exit, icr=%x\n", + dev->name, GT64240ETH_READ(gp, + GT64240_ETH_INT_CAUSE)); + + spin_unlock(&gp->lock); + + return IRQ_HANDLED; +} + +static void enable_ether_irq(struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + u32 intMask; + + intMask = + icrTxBufferLow | icrTxEndLow | icrTxErrorLow | + icrTxBufferHigh | icrTxEndHigh | icrTxErrorHigh | icrTxUdr | + icrRxBuffer | icrRxOVR | icrRxError | icrMIIPhySTC | + icrEtherIntSum; + + +//- GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0); /* CLEAR existing ints */ + // unmask device interrupts: + GT64240ETH_WRITE(gp, GT64240_ETH_INT_MASK, intMask); + + // now route ethernet interrupts to GT PCI1 (eth0 and eth1 will be + // sharing it). + intMask = MV_READ(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH); + intMask |= 1 << gp->port_num; + MV_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, intMask); +} + +static void disable_ether_irq(struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + u32 intMask; + + intMask = MV_READ(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH); + intMask &= ~(1 << gp->port_num); + MV_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, intMask); + + // mask all device interrupts: + GT64240ETH_WRITE(gp, GT64240_ETH_INT_MASK, 0); +} + +/* + * Probe for a GT64240 ethernet controller. + */ +static int __init gt64240_probe(void) +{ + int found = 0; + int i; + + parse_mac_addr_options(); + + for (i = 0; i < NUM_INTERFACES; i++) { + unsigned long base_addr = gt64240_iflist[i].port; + + if (check_region(base_addr, GT64240_ETH_IO_SIZE)) { + printk("gt64240_probe: ioaddr 0x%lx taken?\n", + base_addr); + continue; + } + + if (gt64240_probe1(base_addr, gt64240_iflist[i].irq, i) == 0) { + /* + * Does not seem to be the "traditional" way folks do + * this, but I want to init both eth ports if at all + * possible! + * + * So, until I find out the "correct" way to do this: + */ + if (++found == NUM_INTERFACES) /* That's all of them */ + return 0; + } + } + + if (found) + return 0; /* as long as we found at least one! */ + + return -ENODEV; +} + +module_init(gt64240_probe); + +static int __init gt64240_probe1(unsigned long ioaddr, int irq, int port_num) +{ + struct net_device *dev = NULL; + static unsigned version_printed = 0; + struct gt64240_private *gp = NULL; + int retval; + u32 cpuConfig; + + dev = alloc_etherdev(sizeof(struct gt64240_private)); + if (!dev) + return -ENOMEM; + + if (irq < 0) { + printk + ("gt64240_probe1: irq unknown - probing not supported\n"); + return -ENODEV; + } +#if 1 /* KLUDGE Alert: no check on return value: */ + if (!request_region(ioaddr, GT64240_ETH_IO_SIZE, "gt64240eth")) + printk("*** request_region() failed!\n"); +#endif + + cpuConfig = GT64240_READ(CPU_CONFIGURATION); + printk("gt64240_probe1: cpu in %s-endian mode\n", + (cpuConfig & (1 << 12)) ? "little" : "big"); + + printk("%s: GT64240 found at ioaddr 0x%lx, irq %d.\n", + dev->name, ioaddr, irq); + + if (gt64240_debug && version_printed++ == 0) + printk("%s: %s", dev->name, version); + + /* private struct aligned and zeroed by init_etherdev */ + /* Fill in the 'dev' fields. */ + dev->base_addr = ioaddr; + dev->irq = irq; + memcpy(dev->dev_addr, gt64240_station_addr[port_num], + sizeof(dev->dev_addr)); + + printk("%s: HW Address ", dev->name); + dump_hw_addr(dev->dev_addr); + + gp = dev->priv; + + gp->msg_enable = (debug < 0 ? GT64240_MSG_ENABLE : debug); + gp->port_num = port_num; + gp->io_size = GT64240_ETH_IO_SIZE; + gp->port_offset = port_num * GT64240_ETH_IO_SIZE; + gp->phy_addr = gt64240_phy_addr[port_num]; + + printk("%s: GT64240 ethernet port %d\n", dev->name, gp->port_num); + +#ifdef GT64240_NAPI + printk("Rx NAPI supported \n"); +#endif + +/* MII Initialization */ + gp->mii_if.dev = dev; + gp->mii_if.phy_id = dev->base_addr; + gp->mii_if.mdio_read = read_MII; + gp->mii_if.mdio_write = write_MII; + gp->mii_if.advertising = read_MII(dev, gp->phy_addr, MII_ADVERTISE); + + // Allocate Rx and Tx descriptor rings + if (gp->rx_ring == NULL) { + // All descriptors in ring must be 16-byte aligned + gp->rx_ring = dma_alloc_noncoherent(NULL, + sizeof(gt64240_rd_t) * RX_RING_SIZE + + sizeof(gt64240_td_t) * TX_RING_SIZE, + &gp->rx_ring_dma, GFP_KERNEL); + if (gp->rx_ring == NULL) { + retval = -ENOMEM; + goto free_region; + } + + gp->tx_ring = (gt64240_td_t *) (gp->rx_ring + RX_RING_SIZE); + gp->tx_ring_dma = + gp->rx_ring_dma + sizeof(gt64240_rd_t) * RX_RING_SIZE; + } + // Allocate the Rx Data Buffers + if (gp->rx_buff == NULL) { + gp->rx_buff = dma_alloc_coherent(NULL, + PKT_BUF_SZ * RX_RING_SIZE, &gp->rx_buff_dma, + GFP_KERNEL); + if (gp->rx_buff == NULL) { + dma_free_noncoherent(NULL, + sizeof(gt64240_rd_t) * RX_RING_SIZE + + sizeof(gt64240_td_t) * TX_RING_SIZE, + gp->rx_ring, gp->rx_ring_dma); + retval = -ENOMEM; + goto free_region; + } + } + + if (gt64240_debug > 3) + printk("%s: gt64240_probe1, rx_ring=%p, tx_ring=%p\n", + dev->name, gp->rx_ring, gp->tx_ring); + + // Allocate Rx Hash Table + if (gp->hash_table == NULL) { + gp->hash_table = dma_alloc_coherent(NULL, + RX_HASH_TABLE_SIZE, &gp->hash_table_dma, + GFP_KERNEL); + if (gp->hash_table == NULL) { + dma_free_noncoherent(NULL, + sizeof(gt64240_rd_t) * RX_RING_SIZE + + sizeof(gt64240_td_t) * TX_RING_SIZE, + gp->rx_ring, gp->rx_ring_dma); + dma_free_noncoherent(NULL, PKT_BUF_SZ * RX_RING_SIZE, + gp->rx_buff, gp->rx_buff_dma); + retval = -ENOMEM; + goto free_region; + } + } + + if (gt64240_debug > 3) + printk("%s: gt64240_probe1, hash=%p\n", + dev->name, gp->hash_table); + + spin_lock_init(&gp->lock); + + dev->open = gt64240_open; + dev->hard_start_xmit = gt64240_tx; + dev->stop = gt64240_close; + dev->get_stats = gt64240_get_stats; + dev->do_ioctl = gt64240_ioctl; + dev->set_multicast_list = gt64240_set_rx_mode; + dev->tx_timeout = gt64240_tx_timeout; + dev->watchdog_timeo = GT64240ETH_TX_TIMEOUT; + +#ifdef GT64240_NAPI + dev->poll = gt64240_poll; + dev->weight = 64; +#endif + dev->ethtool_ops = &gp_ethtool_ops; + + /* Fill in the fields of the device structure with ethernet values. */ + return 0; + +free_region: + release_region(ioaddr, gp->io_size); + unregister_netdev(dev); + free_netdev(dev); + printk("%s: gt64240_probe1 failed. Returns %d\n", + dev->name, retval); + return retval; +} + + +static void reset_tx(struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + int i; + + abort(dev, sdcmrAT); + + for (i = 0; i < TX_RING_SIZE; i++) { + if (gp->tx_skbuff[i]) { + if (in_interrupt()) + dev_kfree_skb_irq(gp->tx_skbuff[i]); + else + dev_kfree_skb(gp->tx_skbuff[i]); + gp->tx_skbuff[i] = NULL; + } +//- gp->tx_ring[i].cmdstat = 0; // CPU owns + gp->tx_ring[i].cmdstat = + (u32) (txGenCRC | txEI | txPad | txFirst | txLast); + gp->tx_ring[i].byte_cnt = 0; + gp->tx_ring[i].buff_ptr = 0; + gp->tx_ring[i].next = + gp->tx_ring_dma + sizeof(gt64240_td_t) * (i + 1); + if (gt64240_debug > 4) + dump_tx_desc(dev, i); + } + /* Wrap the ring. */ + gp->tx_ring[i - 1].next = gp->tx_ring_dma; + if (gt64240_debug > 4) + dump_tx_desc(dev, i - 1); + + // setup only the lowest priority TxCDP reg + GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0, + gp->tx_ring_dma); +//- GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0, 0); /* ROLLINS */ +//- GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,virt_to_phys(&gp->tx_ring[0])); /* ROLLINS */ + + GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR1, 0); + + // init Tx indeces and pkt counter + gp->tx_next_in = gp->tx_next_out = 0; + gp->tx_count = 0; +} + +static void reset_rx(struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + int i; + + abort(dev, sdcmrAR); + + for (i = 0; i < RX_RING_SIZE; i++) { + gp->rx_ring[i].next = + gp->rx_ring_dma + sizeof(gt64240_rd_t) * (i + 1); + gp->rx_ring[i].buff_ptr = gp->rx_buff_dma + i * PKT_BUF_SZ; + gp->rx_ring[i].buff_sz = PKT_BUF_SZ; + gp->rx_ring[i].byte_cnt = 0; /* just for debug printk's */ + // Give ownership to device, set first and last, enable interrupt + gp->rx_ring[i].cmdstat = + (uint32_t) (rxFirst | rxLast | rxOwn | rxEI); + if (gt64240_debug > 4) + dump_rx_desc(dev, i); + } + /* Wrap the ring. */ + gp->rx_ring[i - 1].next = gp->rx_ring_dma; + if (gt64240_debug > 4) + dump_rx_desc(dev, i - 1); + + // Setup only the lowest priority RxFDP and RxCDP regs + for (i = 0; i < 4; i++) { + if (i == 0) { + GT64240ETH_WRITE(gp, GT64240_ETH_1ST_RX_DESC_PTR0, + gp->rx_ring_dma); + GT64240ETH_WRITE(gp, GT64240_ETH_CURR_RX_DESC_PTR0, + gp->rx_ring_dma); + } else { + GT64240ETH_WRITE(gp, + GT64240_ETH_1ST_RX_DESC_PTR0 + + i * 4, 0); + GT64240ETH_WRITE(gp, + GT64240_ETH_CURR_RX_DESC_PTR0 + + i * 4, 0); + } + } + + // init Rx NextOut index + gp->rx_next_out = 0; +} + + +static int gt64240_init(struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + + if (gt64240_debug > 3) { + printk("%s: gt64240_init: dev=%p\n", dev->name, dev); + printk("%s: gt64240_init: scs0_lo=%04x, scs0_hi=%04x\n", + dev->name, GT64240_READ(0x008), + GT64240_READ(0x010)); + printk("%s: gt64240_init: scs1_lo=%04x, scs1_hi=%04x\n", + dev->name, GT64240_READ(0x208), + GT64240_READ(0x210)); + printk("%s: gt64240_init: scs2_lo=%04x, scs2_hi=%04x\n", + dev->name, GT64240_READ(0x018), + GT64240_READ(0x020)); + printk("%s: gt64240_init: scs3_lo=%04x, scs3_hi=%04x\n", + dev->name, GT64240_READ(0x218), + GT64240_READ(0x220)); + } + // Stop and disable Port + hard_stop(dev); + + GT64240_WRITE(COMM_UNIT_INTERRUPT_MASK, 0x07070777); /*+prk21aug01 */ + if (gt64240_debug > 2) + printk + ("%s: gt64240_init: CIU Cause=%08x, Mask=%08x, EAddr=%08x\n", + dev->name, GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE), + GT64240_READ(COMM_UNIT_INTERRUPT_MASK), + GT64240_READ(COMM_UNIT_ERROR_ADDRESS)); + + // Set-up hash table + memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear it + gp->hash_mode = 0; + // Add a single entry to hash table - our ethernet address + gt64240_add_hash_entry(dev, dev->dev_addr); + // Set-up DMA ptr to hash table + GT64240ETH_WRITE(gp, GT64240_ETH_HASH_TBL_PTR, gp->hash_table_dma); + if (gt64240_debug > 3) + printk("%s: gt64240_init: Hash Tbl Ptr=%x\n", dev->name, + GT64240ETH_READ(gp, GT64240_ETH_HASH_TBL_PTR)); + + // Setup Tx + reset_tx(dev); + + if (gt64240_debug > 3) + printk("%s: gt64240_init: Curr Tx Desc Ptr0=%x\n", + dev->name, GT64240ETH_READ(gp, + GT64240_ETH_CURR_TX_DESC_PTR0)); + + // Setup Rx + reset_rx(dev); + + if (gt64240_debug > 3) + printk("%s: gt64240_init: 1st/Curr Rx Desc Ptr0=%x/%x\n", + dev->name, GT64240ETH_READ(gp, + GT64240_ETH_1ST_RX_DESC_PTR0), + GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0)); + + if (gt64240_debug > 3) + dump_MII(dev); + + /* force a PHY reset -- self-clearing! */ + write_MII(dev, gp->phy_addr, 0, 0x8000); + + if (gt64240_debug > 3) + printk("%s: gt64240_init: PhyAD=%x\n", dev->name, + GT64240_READ(GT64240_ETH_PHY_ADDR_REG)); + + // setup DMA + // We want the Rx/Tx DMA to write/read data to/from memory in + // Big Endian mode. Also set DMA Burst Size to 8 64Bit words. +#ifdef DESC_DATA_BE + GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_CONFIG, + (0xf << sdcrRCBit) | sdcrRIFB | (3 << + sdcrBSZBit)); +#else + GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_CONFIG, sdcrBLMR | sdcrBLMT | +//- (0xf< 3) + printk("%s: gt64240_init: SDMA Config=%x\n", dev->name, + GT64240ETH_READ(gp, GT64240_ETH_SDMA_CONFIG)); + +#if 0 + // start Rx DMA + GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD); +#endif + + if (gt64240_debug > 3) + printk("%s: gt64240_init: SDMA Cmd =%x\n", dev->name, + GT64240ETH_READ(gp, GT64240_ETH_SDMA_COMM)); + +#if 1 + GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, PORT_CONFIG); +#endif + + if (gt64240_debug > 3) + printk("%s: gt64240_init: Port Config=%x\n", dev->name, + GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG)); + + /* + * Disable all Type-of-Service queueing. All Rx packets will be + * treated normally and will be sent to the lowest priority + * queue. + * + * Disable flow-control for now. FIX! support flow control? + */ + +#if 1 + // clear all the MIB ctr regs + GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG_EXT, + EXT_CONFIG_CLEAR); + read_mib_counters(gp); + GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG_EXT, + EXT_CONFIG_CLEAR | pcxrMIBclrMode); + +#endif + if (gt64240_debug > 3) + printk("%s: gt64240_init: Port Config Ext=%x\n", dev->name, + GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG_EXT)); + + if (gt64240_debug > 3) + printk("%s: gt64240_init: Port Command=%x\n", dev->name, + GT64240ETH_READ(gp, GT64240_ETH_PORT_COMMAND)); + GT64240ETH_WRITE(gp, GT64240_ETH_PORT_COMMAND, 0x0); + + netif_start_queue(dev); + + /* enable the port */ + GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, + (PORT_CONFIG | pcrEN)); + if (gt64240_debug > 3) + printk("%s: gt64240_init: Port Config=%x\n", dev->name, + GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG)); +#if 1 + // start Rx DMA + GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD); +#endif + + + // enable interrupts + enable_ether_irq(dev); + +//--- gp->last_psr |= psrLink; /* KLUDGE ALERT */ + + // we should now be receiving frames + return 0; +} + + +static int gt64240_open(struct net_device *dev) +{ + int retval; + + if (gt64240_debug > 3) + printk("%s: gt64240_open: dev=%p\n", dev->name, dev); + + if ((retval = request_irq(dev->irq, >64240_interrupt, + SA_SHIRQ, dev->name, dev))) { + printk("%s: unable to get IRQ %d\n", dev->name, dev->irq); + + return retval; + } + // Initialize and startup the GT-64240 ethernet port + if ((retval = gt64240_init(dev))) { + printk("%s: error in gt64240_open\n", dev->name); + free_irq(dev->irq, dev); + + return retval; + } + + if (gt64240_debug > 3) + printk("%s: gt64240_open: Initialization done.\n", + dev->name); + + return 0; +} + +static int gt64240_close(struct net_device *dev) +{ + if (gt64240_debug > 3) + printk("%s: gt64240_close: dev=%p\n", dev->name, dev); + + // stop the device + if (netif_device_present(dev)) { + netif_stop_queue(dev); + hard_stop(dev); + } + + free_irq(dev->irq, dev); + + return 0; +} + +#ifdef GT64240_NAPI +/* + * Function will release Tx skbs which are now complete + */ +static void gt64240_tx_fill(struct net_device *dev, u32 status) +{ + struct gt64240_private *gp = netdev_priv(dev); + int nextOut, cdp; + gt64240_td_t *td; + u32 cmdstat; + + cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_TX_DESC_PTR0) + - gp->tx_ring_dma) / sizeof(gt64240_td_t); + + for (nextOut = gp->tx_next_out; nextOut != cdp; + nextOut = (nextOut + 1) % TX_RING_SIZE) { + if (--gp->intr_work_done == 0) + break; + + td = &gp->tx_ring[nextOut]; + cmdstat = td->cmdstat; + + if (cmdstat & (u32) txOwn) + break; + + if (gp->tx_full) { + gp->tx_full = 0; + if (gp->last_psr & psrLink) { + netif_wake_queue(dev); + } + } + // decrement tx ring buffer count + if (gp->tx_count) + gp->tx_count--; + + // free the skb + if (gp->tx_skbuff[nextOut]) { + dev_kfree_skb_irq(gp->tx_skbuff[nextOut]); + gp->tx_skbuff[nextOut] = NULL; + } + } + + gp->tx_next_out = nextOut; + + if ((status & icrTxEndLow) && gp->tx_count != 0) + // we must restart the DMA + GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, + sdcmrERD | sdcmrTXDL); +} + +/* + * Main function for NAPI + */ +static int gt64240_poll(struct net_device *dev, int *budget) +{ + struct gt64240_private *gp = netdev_priv(dev); + unsigned long flags; + int done = 1, orig_budget, work_done; + u32 status = GT64240ETH_READ(gp, GT64240_ETH_INT_CAUSE); + + spin_lock_irqsave(&gp->lock, flags); + gt64240_tx_fill(dev, status); + + if (GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0) != + gp->rx_next_out) { + orig_budget = *budget; + if (orig_budget > dev->quota) + orig_budget = dev->quota; + + work_done = gt64240_rx(dev, status, orig_budget); + *budget -= work_done; + dev->quota -= work_done; + if (work_done >= orig_budget) + done = 0; + if (done) { + __netif_rx_complete(dev); + enable_ether_irq(dev); + } + } + + spin_unlock_irqrestore(&gp->lock, flags); + + return (done ? 0 : 1); +} +#endif + +static int gt64240_tx(struct sk_buff *skb, struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + unsigned long flags; + int nextIn; + + spin_lock_irqsave(&gp->lock, flags); + + nextIn = gp->tx_next_in; + + if (gt64240_debug > 3) { + printk("%s: gt64240_tx: nextIn=%d.\n", dev->name, nextIn); + } + + if (gp->tx_count >= TX_RING_SIZE) { + printk("%s: Tx Ring full, pkt dropped.\n", dev->name); + gp->stats.tx_dropped++; + spin_unlock_irqrestore(&gp->lock, flags); + return 1; + } + + if (!(gp->last_psr & psrLink)) { + printk("%s: gt64240_tx: Link down, pkt dropped.\n", + dev->name); + gp->stats.tx_dropped++; + spin_unlock_irqrestore(&gp->lock, flags); +//--- dump_MII(dev); /* KLUDGE ALERT !!! */ + return 1; + } + + if (gp->tx_ring[nextIn].cmdstat & txOwn) { + printk + ("%s: gt64240_tx: device owns descriptor, pkt dropped.\n", + dev->name); + gp->stats.tx_dropped++; + // stop the queue, so Tx timeout can fix it + netif_stop_queue(dev); + spin_unlock_irqrestore(&gp->lock, flags); + return 1; + } + // Prepare the Descriptor at tx_next_in + gp->tx_skbuff[nextIn] = skb; + gp->tx_ring[nextIn].byte_cnt = skb->len; + gp->tx_ring[nextIn].buff_ptr = virt_to_phys(skb->data); + + // make sure packet gets written back to memory + dma_cache_wback_inv((unsigned long) (skb->data), skb->len); + mb(); + + // Give ownership to device, set first and last desc, enable interrupt + // Setting of ownership bit must be *last*! + gp->tx_ring[nextIn].cmdstat = + txOwn | txGenCRC | txEI | txPad | txFirst | txLast; + + if (gt64240_debug > 5) { + dump_tx_desc(dev, nextIn); + } + // increment tx_next_in with wrap + gp->tx_next_in = (nextIn + 1) % TX_RING_SIZE; + +//+prk20aug01: + if (0) { /* ROLLINS */ + GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0, + virt_to_phys(&gp->tx_ring[nextIn])); + } + + if (gt64240_debug > 3) { /*+prk17aug01 */ + printk + ("%s: gt64240_tx: TX_PTR0=0x%08x, EthPortStatus=0x%08x\n", + dev->name, GT64240ETH_READ(gp, + GT64240_ETH_CURR_TX_DESC_PTR0), + GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS)); + } + // If DMA is stopped, restart + if (!((GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS)) & psrTxLow)) { + GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, + sdcmrERD | sdcmrTXDL); + } + + if (gt64240_debug > 3) { /*+prk17aug01 */ + printk + ("%s: gt64240_tx: TX_PTR0=0x%08x, EthPortStatus=0x%08x\n", + dev->name, GT64240ETH_READ(gp, + GT64240_ETH_CURR_TX_DESC_PTR0), + GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS)); + } + // increment count and stop queue if full + if (++gp->tx_count >= TX_RING_SIZE) { + gp->tx_full = 1; + netif_stop_queue(dev); + } + + dev->trans_start = jiffies; + spin_unlock_irqrestore(&gp->lock, flags); + + return 0; +} + + +static int +#ifdef GT64240_NAPI +gt64240_rx(struct net_device *dev, u32 status, int budget) +#else +gt64240_rx(struct net_device *dev, u32 status) +#endif +{ + struct gt64240_private *gp = netdev_priv(dev); + struct sk_buff *skb; + int pkt_len, nextOut, cdp; + gt64240_rd_t *rd; + u32 cmdstat; + + if (gt64240_debug > 3) + printk("%s: gt64240_rx: dev=%p, status=%x\n", + dev->name, dev, status); + + cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0) + - gp->rx_ring_dma) / sizeof(gt64240_rd_t); + + // Continue until we reach the current descriptor pointer + for (nextOut = gp->rx_next_out; nextOut != cdp; + nextOut = (nextOut + 1) % RX_RING_SIZE) { + +#ifdef GT64240_NAPI + if (budget <= 0) + break; + + budget--; +#endif + + if (--gp->intr_work_done == 0) + break; + + if (gt64240_debug > 4) + dump_rx_desc(dev, nextOut); + + rd = &gp->rx_ring[nextOut]; + cmdstat = rd->cmdstat; + + if (gt64240_debug > 3) + printk("%s: isr: Rx desc cmdstat=%x, nextOut=%d\n", + dev->name, cmdstat, nextOut); + + if (cmdstat & (u32) rxOwn) { + if (gt64240_debug > 2) + printk + ("%s: gt64240_rx: device owns descriptor!\n", + dev->name); + // DMA is not finished updating descriptor??? + // Leave and come back later to pick-up where we left off. + break; + } + // must be first and last (ie only) buffer of packet + if (!(cmdstat & (u32) rxFirst) + || !(cmdstat & (u32) rxLast)) { + printk + ("%s: gt64240_rx: desc not first and last!\n", + dev->name); + cmdstat |= (u32) rxOwn; + rd->cmdstat = cmdstat; + continue; + } + // Drop this received pkt if there were any errors + if ((cmdstat & (u32) rxErrorSummary) + || (status & icrRxError)) { + // update the detailed rx error counters that are not covered + // by the MIB counters. + if (cmdstat & (u32) rxOverrun) + gp->stats.rx_fifo_errors++; + cmdstat |= (u32) rxOwn; + rd->cmdstat = cmdstat; + continue; + } + + pkt_len = rd->byte_cnt; + + /* Create new skb. */ +// skb = dev_alloc_skb(pkt_len+2); + skb = dev_alloc_skb(1538); + if (skb == NULL) { + printk("%s: Memory squeeze, dropping packet.\n", + dev->name); + gp->stats.rx_dropped++; + cmdstat |= (u32) rxOwn; + rd->cmdstat = cmdstat; + continue; + } + skb->dev = dev; + skb_reserve(skb, 2); /* 16 byte IP header align */ + memcpy(skb_put(skb, pkt_len), + &gp->rx_buff[nextOut * PKT_BUF_SZ], pkt_len); + skb->protocol = eth_type_trans(skb, dev); + + /* NIC performed some checksum computation */ + skb->ip_summed = CHECKSUM_UNNECESSARY; +#ifdef GT64240_NAPI + netif_receive_skb(skb); +#else + netif_rx(skb); /* pass the packet to upper layers */ +#endif + + // now we can release ownership of this desc back to device + cmdstat |= (u32) rxOwn; + rd->cmdstat = cmdstat; + + dev->last_rx = jiffies; + } + + if (gt64240_debug > 3 && nextOut == gp->rx_next_out) + printk("%s: gt64240_rx: RxCDP did not increment?\n", + dev->name); + + gp->rx_next_out = nextOut; + return 0; +} + + +static void gt64240_tx_timeout(struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&gp->lock, flags); + + + if (!(gp->last_psr & psrLink)) { + spin_unlock_irqrestore(&gp->lock, flags); + } else { + printk("======------> gt64240_tx_timeout: %d jiffies \n", + GT64240ETH_TX_TIMEOUT); + + disable_ether_irq(dev); + spin_unlock_irqrestore(&gp->lock, flags); + reset_tx(dev); + enable_ether_irq(dev); + + netif_wake_queue(dev); + } +} + + +static void gt64240_set_rx_mode(struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + unsigned long flags; + struct dev_mc_list *mcptr; + + if (gt64240_debug > 3) + printk("%s: gt64240_set_rx_mode: dev=%p, flags=%x\n", + dev->name, dev, dev->flags); + + // stop the Receiver DMA + abort(dev, sdcmrAR); + + spin_lock_irqsave(&gp->lock, flags); + + if (dev->flags & IFF_PROMISC) + GT64240ETH_SETBIT(gp, GT64240_ETH_PORT_CONFIG, pcrPM); + else + GT64240ETH_CLRBIT(gp, GT64240_ETH_PORT_CONFIG, pcrPM); +/* + GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, + (PORT_CONFIG | pcrPM | pcrEN)); +*/ + + memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear hash table + // Add our ethernet address + gt64240_add_hash_entry(dev, dev->dev_addr); + if (dev->mc_count) { + for (mcptr = dev->mc_list; mcptr; mcptr = mcptr->next) { + if (gt64240_debug > 2) { + printk("%s: gt64240_set_rx_mode: addr=\n", + dev->name); + dump_hw_addr(mcptr->dmi_addr); + } + gt64240_add_hash_entry(dev, mcptr->dmi_addr); + } + } + + if (gt64240_debug > 3) + printk("%s: gt64240_set_rx: Port Config=%x\n", dev->name, + GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG)); + + // restart Rx DMA + GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD); + + spin_unlock_irqrestore(&gp->lock, flags); +} + +static struct net_device_stats *gt64240_get_stats(struct net_device *dev) +{ + struct gt64240_private *gp = netdev_priv(dev); + unsigned long flags; + + if (gt64240_debug > 3) + printk("%s: gt64240_get_stats: dev=%p\n", dev->name, dev); + + if (netif_device_present(dev)) { + spin_lock_irqsave(&gp->lock, flags); + update_stats(gp); + spin_unlock_irqrestore(&gp->lock, flags); + } + + return &gp->stats; +} diff -Naur linux-2.6.12.6.orig/drivers/net/gt64240eth.h linux-2.6.12.6/drivers/net/gt64240eth.h --- linux-2.6.12.6.orig/drivers/net/gt64240eth.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/gt64240eth.h 2005-10-02 23:47:38.000000000 +0000 @@ -9,6 +9,7 @@ * Copyright 2000 MontaVista Software Inc. * Author: MontaVista Software, Inc. * stevel@mvista.com or support@mvista.com + * Copyright 2004, 05 Ralf Baechle (ralf@linux-mips.org) * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -31,6 +32,7 @@ #ifndef _GT64240ETH_H #define _GT64240ETH_H +#include #include #define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400 @@ -108,10 +110,10 @@ #define REV_GT64240A 0x10 #define GT64240ETH_READ(gp, offset) \ - GT_READ((gp)->port_offset + (offset)) + MV_READ((gp)->port_offset + (offset)) #define GT64240ETH_WRITE(gp, offset, data) \ - GT_WRITE((gp)->port_offset + (offset), (data)) + MV_WRITE((gp)->port_offset + (offset), (data)) #define GT64240ETH_SETBIT(gp, offset, bits) \ GT64240ETH_WRITE((gp), (offset), \ @@ -121,8 +123,8 @@ GT64240ETH_WRITE((gp), (offset), \ GT64240ETH_READ((gp), (offset)) & ~(bits)) -#define GT64240_READ(ofs) GT_READ(ofs) -#define GT64240_WRITE(ofs, data) GT_WRITE((ofs), (data)) +#define GT64240_READ(ofs) MV_READ(ofs) +#define GT64240_WRITE(ofs, data) MV_WRITE((ofs), (data)) /* Bit definitions of the SMI Reg */ enum { diff -Naur linux-2.6.12.6.orig/drivers/net/ioc3-eth.c linux-2.6.12.6/drivers/net/ioc3-eth.c --- linux-2.6.12.6.orig/drivers/net/ioc3-eth.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/ioc3-eth.c 2005-10-02 23:47:38.000000000 +0000 @@ -499,7 +499,7 @@ ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG); while (ioc3_r_micr() & MICR_BUSY); - return ioc3_r_micr() & MIDR_DATA_MASK; + return ioc3_r_midr_r() & MIDR_DATA_MASK; } static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data) @@ -1291,7 +1291,6 @@ dev->features = NETIF_F_IP_CSUM; #endif - ioc3_setup_duplex(ip); sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1); sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2); @@ -1300,6 +1299,7 @@ goto out_stop; mii_check_media(&ip->mii, 1, 1); + ioc3_setup_duplex(ip); vendor = (sw_physid1 << 12) | (sw_physid2 >> 4); model = (sw_physid2 >> 4) & 0x3f; diff -Naur linux-2.6.12.6.orig/drivers/net/saa9730.c linux-2.6.12.6/drivers/net/saa9730.c --- linux-2.6.12.6.orig/drivers/net/saa9730.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/saa9730.c 2005-10-02 23:47:38.000000000 +0000 @@ -1,8 +1,7 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## + * Copyright (C) 2000, 2005 MIPS Technologies, Inc. All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -17,15 +16,13 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * ######################################################################## - * * SAA9730 ethernet driver. * * Changes: - * Angelo Dell'Aera : Conversion to the new PCI API (pci_driver). - * Conversion to spinlocks. - * Error handling fixes. - * + * Angelo Dell'Aera : Conversion to the new PCI API + * (pci_driver). + * Conversion to spinlocks. + * Error handling fixes. */ #include @@ -36,8 +33,11 @@ #include #include #include +#include #include +#include + #include #include "saa9730.h" @@ -51,8 +51,8 @@ #define DRV_MODULE_NAME "saa9730" static struct pci_device_id saa9730_pci_tbl[] = { - { PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9370, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9730, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, { 0, } }; @@ -61,8 +61,8 @@ /* Non-zero only if the current card is a PCI with BIOS-set IRQ. */ static unsigned int pci_irq_line; -#define INL(a) inl((unsigned long)a) -#define OUTL(x,a) outl(x,(unsigned long)a) +#define INL(a) readl(a) +#define OUTL(x, a) writel(x, a) static void evm_saa9730_enable_lan_int(struct lan_saa9730_private *lp) { @@ -98,13 +98,13 @@ &lp->evm_saa9730_regs->InterruptBlock1); } -static void show_saa9730_regs(struct lan_saa9730_private *lp) +static void __attribute_used__ show_saa9730_regs(struct lan_saa9730_private *lp) { int i, j; - printk("TxmBufferA = %x\n", lp->TxmBuffer[0][0]); - printk("TxmBufferB = %x\n", lp->TxmBuffer[1][0]); - printk("RcvBufferA = %x\n", lp->RcvBuffer[0][0]); - printk("RcvBufferB = %x\n", lp->RcvBuffer[1][0]); + printk("TxmBufferA = %p\n", lp->TxmBuffer[0][0]); + printk("TxmBufferB = %p\n", lp->TxmBuffer[1][0]); + printk("RcvBufferA = %p\n", lp->RcvBuffer[0][0]); + printk("RcvBufferB = %p\n", lp->RcvBuffer[1][0]); for (i = 0; i < LAN_SAA9730_BUFFERS; i++) { for (j = 0; j < LAN_SAA9730_TXM_Q_SIZE; j++) { printk("TxmBuffer[%d][%d] = %x\n", i, j, @@ -214,88 +214,95 @@ } } -static int lan_saa9730_allocate_buffers(struct lan_saa9730_private *lp) +static void lan_saa9730_free_buffers(struct pci_dev *pdev, + struct lan_saa9730_private *lp) { - unsigned int mem_size; - void *Pa; - unsigned int i, j, RcvBufferSize, TxmBufferSize; - unsigned int buffer_start; + pci_free_consistent(pdev, lp->buffer_size, lp->buffer_start, + lp->dma_addr); +} - /* - * Allocate all RX and TX packets in one chunk. - * The Rx and Tx packets must be PACKET_SIZE aligned. - */ - mem_size = ((LAN_SAA9730_RCV_Q_SIZE + LAN_SAA9730_TXM_Q_SIZE) * - LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_BUFFERS) + - LAN_SAA9730_PACKET_SIZE; - buffer_start = - (unsigned int) kmalloc(mem_size, GFP_DMA | GFP_KERNEL); - - if (!buffer_start) - return -ENOMEM; - - /* - * Set DMA buffer to kseg1 (uncached). - * Make sure to flush before using it uncached. - */ - Pa = (void *) KSEG1ADDR((buffer_start + LAN_SAA9730_PACKET_SIZE) & - ~(LAN_SAA9730_PACKET_SIZE - 1)); - dma_cache_wback_inv((unsigned long) Pa, mem_size); +static int lan_saa9730_allocate_buffers(struct pci_dev *pdev, + struct lan_saa9730_private *lp) +{ + void *Pa; + unsigned int i, j, rxoffset, txoffset; + int ret; /* Initialize buffer space */ - RcvBufferSize = LAN_SAA9730_PACKET_SIZE; - TxmBufferSize = LAN_SAA9730_PACKET_SIZE; lp->DmaRcvPackets = LAN_SAA9730_RCV_Q_SIZE; lp->DmaTxmPackets = LAN_SAA9730_TXM_Q_SIZE; + /* Initialize Rx Buffer Index */ + lp->NextRcvPacketIndex = 0; + lp->NextRcvBufferIndex = 0; + + /* Set current buffer index & next available packet index */ + lp->NextTxmPacketIndex = 0; + lp->NextTxmBufferIndex = 0; + lp->PendingTxmPacketIndex = 0; + lp->PendingTxmBufferIndex = 0; + + /* + * Allocate all RX and TX packets in one chunk. + * The Rx and Tx packets must be PACKET_SIZE aligned. + */ + lp->buffer_size = ((LAN_SAA9730_RCV_Q_SIZE + LAN_SAA9730_TXM_Q_SIZE) * + LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_BUFFERS) + + LAN_SAA9730_PACKET_SIZE; + lp->buffer_start = pci_alloc_consistent(pdev, lp->buffer_size, + &lp->dma_addr); + if (!lp->buffer_start) { + ret = -ENOMEM; + goto out; + } + + Pa = (void *)ALIGN((unsigned long)lp->buffer_start, + LAN_SAA9730_PACKET_SIZE); + + rxoffset = Pa - lp->buffer_start; + /* Init RX buffers */ for (i = 0; i < LAN_SAA9730_BUFFERS; i++) { for (j = 0; j < LAN_SAA9730_RCV_Q_SIZE; j++) { *(unsigned int *) Pa = cpu_to_le32(RXSF_READY << RX_STAT_CTL_OWNER_SHF); - lp->RcvBuffer[i][j] = (unsigned int) Pa; - Pa += RcvBufferSize; + lp->RcvBuffer[i][j] = Pa; + Pa += LAN_SAA9730_PACKET_SIZE; } } + txoffset = Pa - lp->buffer_start; + /* Init TX buffers */ for (i = 0; i < LAN_SAA9730_BUFFERS; i++) { for (j = 0; j < LAN_SAA9730_TXM_Q_SIZE; j++) { *(unsigned int *) Pa = cpu_to_le32(TXSF_EMPTY << TX_STAT_CTL_OWNER_SHF); - lp->TxmBuffer[i][j] = (unsigned int) Pa; - Pa += TxmBufferSize; + lp->TxmBuffer[i][j] = Pa; + Pa += LAN_SAA9730_PACKET_SIZE; } } - /* - * Set rx buffer A and rx buffer B to point to the first two buffer + /* + * Set rx buffer A and rx buffer B to point to the first two buffer * spaces. */ - OUTL(PHYSADDR(lp->RcvBuffer[0][0]), + OUTL(lp->dma_addr + rxoffset, &lp->lan_saa9730_regs->RxBuffA); - OUTL(PHYSADDR(lp->RcvBuffer[1][0]), + OUTL(lp->dma_addr + rxoffset + + LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_RCV_Q_SIZE, &lp->lan_saa9730_regs->RxBuffB); - /* Initialize Buffer Index */ - lp->NextRcvPacketIndex = 0; - lp->NextRcvToUseIsA = 1; - - /* Set current buffer index & next availble packet index */ - lp->NextTxmPacketIndex = 0; - lp->NextTxmBufferIndex = 0; - lp->PendingTxmPacketIndex = 0; - lp->PendingTxmBufferIndex = 0; - - /* + /* * Set txm_buf_a and txm_buf_b to point to the first two buffer - * space + * space */ - OUTL(PHYSADDR(lp->TxmBuffer[0][0]), + OUTL(lp->dma_addr + txoffset, &lp->lan_saa9730_regs->TxBuffA); - OUTL(PHYSADDR(lp->TxmBuffer[1][0]), + OUTL(lp->dma_addr + txoffset + + LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_TXM_Q_SIZE, &lp->lan_saa9730_regs->TxBuffB); /* Set packet number */ @@ -306,6 +313,9 @@ &lp->lan_saa9730_regs->PacketCount); return 0; + +out: + return ret; } static int lan_saa9730_cam_load(struct lan_saa9730_private *lp) @@ -328,8 +338,7 @@ static int lan_saa9730_cam_init(struct net_device *dev) { - struct lan_saa9730_private *lp = - (struct lan_saa9730_private *) dev->priv; + struct lan_saa9730_private *lp = netdev_priv(dev); unsigned int i; /* Copy MAC-address into all entries. */ @@ -469,9 +478,9 @@ OUTL(CAM_CONTROL_COMP_EN | CAM_CONTROL_BROAD_ACC, &lp->lan_saa9730_regs->CamCtl); - /* + /* * Initialize CAM enable register, only turn on first entry, should - * contain own addr. + * contain own addr. */ OUTL(0x0001, &lp->lan_saa9730_regs->CamEnable); @@ -501,7 +510,7 @@ OUTL(INL(&lp->lan_saa9730_regs->MacCtl) | MAC_CONTROL_RESET, &lp->lan_saa9730_regs->MacCtl); - /* + /* * Wait for MAC reset to have finished. The reset bit is auto cleared * when the reset is done. */ @@ -536,9 +545,9 @@ /* Initialize Rx Buffer Index */ lp->NextRcvPacketIndex = 0; - lp->NextRcvToUseIsA = 1; + lp->NextRcvBufferIndex = 0; - /* Set current buffer index & next availble packet index */ + /* Set current buffer index & next available packet index */ lp->NextTxmPacketIndex = 0; lp->NextTxmBufferIndex = 0; lp->PendingTxmPacketIndex = 0; @@ -555,9 +564,8 @@ OUTL(INL(&lp->lan_saa9730_regs->RxCtl) | RX_CTL_RX_EN, &lp->lan_saa9730_regs->RxCtl); - /* Set Ok2Use to let hardware owns the buffers */ - OUTL(OK2USE_RX_A | OK2USE_RX_B | OK2USE_TX_A | OK2USE_TX_B, - &lp->lan_saa9730_regs->Ok2Use); + /* Set Ok2Use to let hardware own the buffers. */ + OUTL(OK2USE_RX_A | OK2USE_RX_B, &lp->lan_saa9730_regs->Ok2Use); return 0; } @@ -572,8 +580,7 @@ static int lan_saa9730_tx(struct net_device *dev) { - struct lan_saa9730_private *lp = - (struct lan_saa9730_private *) dev->priv; + struct lan_saa9730_private *lp = netdev_priv(dev); unsigned int *pPacket; unsigned int tx_status; @@ -584,10 +591,8 @@ OUTL(DMA_STATUS_MAC_TX_INT, &lp->lan_saa9730_regs->DmaStatus); while (1) { - pPacket = - (unsigned int *) lp->TxmBuffer[lp-> - PendingTxmBufferIndex] - [lp->PendingTxmPacketIndex]; + pPacket = lp->TxmBuffer[lp->PendingTxmBufferIndex] + [lp->PendingTxmPacketIndex]; /* Get status of first packet transmitted. */ tx_status = le32_to_cpu(*pPacket); @@ -605,23 +610,22 @@ lp->stats.tx_errors++; if (tx_status & (TX_STATUS_EX_COLL << TX_STAT_CTL_STATUS_SHF)) - lp->stats.tx_aborted_errors++; + lp->stats.tx_aborted_errors++; if (tx_status & - (TX_STATUS_LATE_COLL << - TX_STAT_CTL_STATUS_SHF)) lp->stats. - tx_window_errors++; + (TX_STATUS_LATE_COLL << TX_STAT_CTL_STATUS_SHF)) + lp->stats.tx_window_errors++; if (tx_status & (TX_STATUS_L_CARR << TX_STAT_CTL_STATUS_SHF)) - lp->stats.tx_carrier_errors++; + lp->stats.tx_carrier_errors++; if (tx_status & (TX_STATUS_UNDER << TX_STAT_CTL_STATUS_SHF)) - lp->stats.tx_fifo_errors++; + lp->stats.tx_fifo_errors++; if (tx_status & (TX_STATUS_SQ_ERR << TX_STAT_CTL_STATUS_SHF)) - lp->stats.tx_heartbeat_errors++; + lp->stats.tx_heartbeat_errors++; lp->stats.collisions += - tx_status & TX_STATUS_TX_COLL_MSK; + tx_status & TX_STATUS_TX_COLL_MSK; } /* Free buffer. */ @@ -636,21 +640,15 @@ } } - /* Make sure A and B are available to hardware. */ - OUTL(OK2USE_TX_A | OK2USE_TX_B, &lp->lan_saa9730_regs->Ok2Use); - - if (netif_queue_stopped(dev)) { - /* The tx buffer is no longer full. */ - netif_wake_queue(dev); - } + /* The tx buffer is no longer full. */ + netif_wake_queue(dev); return 0; } static int lan_saa9730_rx(struct net_device *dev) { - struct lan_saa9730_private *lp = - (struct lan_saa9730_private *) dev->priv; + struct lan_saa9730_private *lp = netdev_priv(dev); int len = 0; struct sk_buff *skb = 0; unsigned int rx_status; @@ -667,12 +665,9 @@ DMA_STATUS_RX_TO_INT, &lp->lan_saa9730_regs->DmaStatus); /* Address next packet */ - if (lp->NextRcvToUseIsA) - BufferIndex = 0; - else - BufferIndex = 1; + BufferIndex = lp->NextRcvBufferIndex; PacketIndex = lp->NextRcvPacketIndex; - pPacket = (unsigned int *) lp->RcvBuffer[BufferIndex][PacketIndex]; + pPacket = lp->RcvBuffer[BufferIndex][PacketIndex]; rx_status = le32_to_cpu(*pPacket); /* Process each packet. */ @@ -715,51 +710,39 @@ lp->stats.rx_errors++; if (rx_status & (RX_STATUS_CRC_ERR << RX_STAT_CTL_STATUS_SHF)) - lp->stats.rx_crc_errors++; + lp->stats.rx_crc_errors++; if (rx_status & - (RX_STATUS_ALIGN_ERR << - RX_STAT_CTL_STATUS_SHF)) lp->stats. - rx_frame_errors++; + (RX_STATUS_ALIGN_ERR << RX_STAT_CTL_STATUS_SHF)) + lp->stats.rx_frame_errors++; if (rx_status & (RX_STATUS_OVERFLOW << RX_STAT_CTL_STATUS_SHF)) - lp->stats.rx_fifo_errors++; + lp->stats.rx_fifo_errors++; if (rx_status & (RX_STATUS_LONG_ERR << RX_STAT_CTL_STATUS_SHF)) - lp->stats.rx_length_errors++; + lp->stats.rx_length_errors++; } /* Indicate we have processed the buffer. */ - *pPacket = - cpu_to_le32(RXSF_READY << RX_STAT_CTL_OWNER_SHF); + *pPacket = cpu_to_le32(RXSF_READY << RX_STAT_CTL_OWNER_SHF); + + /* Make sure A or B is available to hardware as appropriate. */ + OUTL(BufferIndex ? OK2USE_RX_B : OK2USE_RX_A, + &lp->lan_saa9730_regs->Ok2Use); /* Go to next packet in sequence. */ lp->NextRcvPacketIndex++; if (lp->NextRcvPacketIndex >= LAN_SAA9730_RCV_Q_SIZE) { lp->NextRcvPacketIndex = 0; - if (BufferIndex) { - lp->NextRcvToUseIsA = 1; - } else { - lp->NextRcvToUseIsA = 0; - } + lp->NextRcvBufferIndex ^= 1; } - OUTL(OK2USE_RX_A | OK2USE_RX_B, - &lp->lan_saa9730_regs->Ok2Use); /* Address next packet */ - if (lp->NextRcvToUseIsA) - BufferIndex = 0; - else - BufferIndex = 1; + BufferIndex = lp->NextRcvBufferIndex; PacketIndex = lp->NextRcvPacketIndex; - pPacket = - (unsigned int *) lp-> - RcvBuffer[BufferIndex][PacketIndex]; + pPacket = lp->RcvBuffer[BufferIndex][PacketIndex]; rx_status = le32_to_cpu(*pPacket); } - /* Make sure A and B are available to hardware. */ - OUTL(OK2USE_RX_A | OK2USE_RX_B, &lp->lan_saa9730_regs->Ok2Use); - return 0; } @@ -767,8 +750,7 @@ struct pt_regs *regs) { struct net_device *dev = (struct net_device *) dev_id; - struct lan_saa9730_private *lp = - (struct lan_saa9730_private *) dev->priv; + struct lan_saa9730_private *lp = netdev_priv(dev); if (lan_saa9730_debug > 5) printk("lan_saa9730_interrupt\n"); @@ -794,15 +776,9 @@ return IRQ_HANDLED; } -static int lan_saa9730_open_fail(struct net_device *dev) -{ - return -ENODEV; -} - static int lan_saa9730_open(struct net_device *dev) { - struct lan_saa9730_private *lp = - (struct lan_saa9730_private *) dev->priv; + struct lan_saa9730_private *lp = netdev_priv(dev); /* Associate IRQ with lan_saa9730_interrupt */ if (request_irq(dev->irq, &lan_saa9730_interrupt, 0, "SAA9730 Eth", @@ -834,15 +810,13 @@ int PacketIndex; if (lan_saa9730_debug > 5) - printk("lan_saa9730_write: skb=%08x\n", - (unsigned int) skb); + printk("lan_saa9730_write: skb=%p\n", skb); BufferIndex = lp->NextTxmBufferIndex; PacketIndex = lp->NextTxmPacketIndex; - tx_status = - le32_to_cpu(*(unsigned int *) lp-> - TxmBuffer[BufferIndex][PacketIndex]); + tx_status = le32_to_cpu(*(unsigned int *)lp->TxmBuffer[BufferIndex] + [PacketIndex]); if ((tx_status & TX_STAT_CTL_OWNER_MSK) != (TXSF_EMPTY << TX_STAT_CTL_OWNER_SHF)) { if (lan_saa9730_debug > 4) @@ -858,29 +832,29 @@ lp->NextTxmBufferIndex ^= 1; } - pbPacketData = - (unsigned char *) lp->TxmBuffer[BufferIndex][PacketIndex]; + pbPacketData = lp->TxmBuffer[BufferIndex][PacketIndex]; pbPacketData += 4; /* copy the bits */ memcpy(pbPacketData, pbData, len); /* Set transmit status for hardware */ - *(unsigned int *) lp->TxmBuffer[BufferIndex][PacketIndex] = - cpu_to_le32((TXSF_READY << TX_STAT_CTL_OWNER_SHF) | - (TX_STAT_CTL_INT_AFTER_TX << TX_STAT_CTL_FRAME_SHF) - | (len << TX_STAT_CTL_LENGTH_SHF)); + *(unsigned int *)lp->TxmBuffer[BufferIndex][PacketIndex] = + cpu_to_le32((TXSF_READY << TX_STAT_CTL_OWNER_SHF) | + (TX_STAT_CTL_INT_AFTER_TX << + TX_STAT_CTL_FRAME_SHF) | + (len << TX_STAT_CTL_LENGTH_SHF)); - /* Set hardware tx buffer. */ - OUTL(OK2USE_TX_A | OK2USE_TX_B, &lp->lan_saa9730_regs->Ok2Use); + /* Make sure A or B is available to hardware as appropriate. */ + OUTL(BufferIndex ? OK2USE_TX_B : OK2USE_TX_A, + &lp->lan_saa9730_regs->Ok2Use); return 0; } static void lan_saa9730_tx_timeout(struct net_device *dev) { - struct lan_saa9730_private *lp = - (struct lan_saa9730_private *) dev->priv; + struct lan_saa9730_private *lp = netdev_priv(dev); /* Transmitter timeout, serious problems */ lp->stats.tx_errors++; @@ -889,20 +863,19 @@ lan_saa9730_restart(lp); dev->trans_start = jiffies; - netif_start_queue(dev); + netif_wake_queue(dev); } static int lan_saa9730_start_xmit(struct sk_buff *skb, struct net_device *dev) { - struct lan_saa9730_private *lp = - (struct lan_saa9730_private *) dev->priv; + struct lan_saa9730_private *lp = netdev_priv(dev); unsigned long flags; int skblen; int len; if (lan_saa9730_debug > 4) - printk("Send packet: skb=%08x\n", (unsigned int) skb); + printk("Send packet: skb=%p\n", skb); skblen = skb->len; @@ -912,8 +885,7 @@ if (lan_saa9730_write(lp, skb, skblen)) { spin_unlock_irqrestore(&lp->lock, flags); - printk("Error when writing packet to controller: skb=%08x\n", - (unsigned int) skb); + printk("Error when writing packet to controller: skb=%p\n", skb); netif_stop_queue(dev); return -1; } @@ -922,7 +894,7 @@ lp->stats.tx_packets++; dev->trans_start = jiffies; - netif_start_queue(dev); + netif_wake_queue(dev); dev_kfree_skb(skb); spin_unlock_irqrestore(&lp->lock, flags); @@ -932,8 +904,7 @@ static int lan_saa9730_close(struct net_device *dev) { - struct lan_saa9730_private *lp = - (struct lan_saa9730_private *) dev->priv; + struct lan_saa9730_private *lp = netdev_priv(dev); if (lan_saa9730_debug > 1) printk("lan_saa9730_close:\n"); @@ -955,16 +926,14 @@ static struct net_device_stats *lan_saa9730_get_stats(struct net_device *dev) { - struct lan_saa9730_private *lp = - (struct lan_saa9730_private *) dev->priv; + struct lan_saa9730_private *lp = netdev_priv(dev); return &lp->stats; } static void lan_saa9730_set_multicast(struct net_device *dev) { - struct lan_saa9730_private *lp = - (struct lan_saa9730_private *) dev->priv; + struct lan_saa9730_private *lp = netdev_priv(dev); /* Stop the controller */ lan_saa9730_stop(lp); @@ -981,7 +950,7 @@ CAM_CONTROL_BROAD_ACC, &lp->lan_saa9730_regs->CamCtl); } else { - /* + /* * Will handle the multicast stuff later. -carstenl */ } @@ -993,94 +962,86 @@ static void __devexit saa9730_remove_one(struct pci_dev *pdev) { - struct net_device *dev = pci_get_drvdata(pdev); - - if (dev) { - unregister_netdev(dev); - - if (dev->priv) - kfree(dev->priv); + struct net_device *dev = pci_get_drvdata(pdev); + struct lan_saa9730_private *lp = netdev_priv(dev); - free_netdev(dev); - pci_release_regions(pdev); - pci_disable_device(pdev); - pci_set_drvdata(pdev, NULL); - } + if (dev) { + unregister_netdev(dev); + lan_saa9730_free_buffers(pdev, lp); + iounmap(lp->lan_saa9730_regs); + iounmap(lp->evm_saa9730_regs); + free_netdev(dev); + pci_release_regions(pdev); + pci_disable_device(pdev); + pci_set_drvdata(pdev, NULL); + } } -static int lan_saa9730_init(struct net_device *dev, int ioaddr, int irq) +static int lan_saa9730_init(struct net_device *dev, struct pci_dev *pdev, + unsigned long ioaddr, int irq) { - struct lan_saa9730_private *lp; + struct lan_saa9730_private *lp = netdev_priv(dev); unsigned char ethernet_addr[6]; - int ret = 0; + int ret; - dev->open = lan_saa9730_open_fail; + if (get_ethernet_addr(ethernet_addr)) { + ret = -ENODEV; + goto out; + } - if (get_ethernet_addr(ethernet_addr)) - return -ENODEV; - memcpy(dev->dev_addr, ethernet_addr, 6); dev->base_addr = ioaddr; dev->irq = irq; - - /* - * Make certain the data structures used by the controller are aligned - * and DMAble. - */ - /* - * XXX: that is obviously broken - kfree() won't be happy with us. - */ - lp = (struct lan_saa9730_private *) (((unsigned long) - kmalloc(sizeof(*lp) + 7, - GFP_DMA | GFP_KERNEL) - + 7) & ~7); - if (!lp) - return -ENOMEM; - - dev->priv = lp; - memset(lp, 0, sizeof(*lp)); + lp->pci_dev = pdev; /* Set SAA9730 LAN base address. */ - lp->lan_saa9730_regs = (t_lan_saa9730_regmap *) (ioaddr + - SAA9730_LAN_REGS_ADDR); + lp->lan_saa9730_regs = ioremap(ioaddr + SAA9730_LAN_REGS_ADDR, + SAA9730_LAN_REGS_SIZE); + if (!lp->lan_saa9730_regs) { + ret = -ENOMEM; + goto out; + } /* Set SAA9730 EVM base address. */ - lp->evm_saa9730_regs = (t_evm_saa9730_regmap *) (ioaddr + - SAA9730_EVM_REGS_ADDR); + lp->evm_saa9730_regs = ioremap(ioaddr + SAA9730_EVM_REGS_ADDR, + SAA9730_EVM_REGS_SIZE); + if (!lp->evm_saa9730_regs) { + ret = -ENOMEM; + goto out_iounmap_lan; + } /* Allocate LAN RX/TX frame buffer space. */ - /* FIXME: a leak */ - if ((ret = lan_saa9730_allocate_buffers(lp))) - goto out; + if ((ret = lan_saa9730_allocate_buffers(pdev, lp))) + goto out_iounmap; /* Stop LAN controller. */ - if ((ret = lan_saa9730_stop(lp))) - goto out; - + if ((ret = lan_saa9730_stop(lp))) + goto out_free_consistent; + /* Initialize CAM registers. */ if ((ret = lan_saa9730_cam_init(dev))) - goto out; + goto out_free_consistent; /* Initialize MII registers. */ if ((ret = lan_saa9730_mii_init(lp))) - goto out; + goto out_free_consistent; /* Initialize control registers. */ - if ((ret = lan_saa9730_control_init(lp))) - goto out; - + if ((ret = lan_saa9730_control_init(lp))) + goto out_free_consistent; + /* Load CAM registers. */ - if ((ret = lan_saa9730_cam_load(lp))) - goto out; - + if ((ret = lan_saa9730_cam_load(lp))) + goto out_free_consistent; + /* Initialize DMA context registers. */ if ((ret = lan_saa9730_dma_init(lp))) - goto out; - + goto out_free_consistent; + spin_lock_init(&lp->lock); - + dev->open = lan_saa9730_open; dev->hard_start_xmit = lan_saa9730_start_xmit; dev->stop = lan_saa9730_close; @@ -1089,45 +1050,43 @@ dev->tx_timeout = lan_saa9730_tx_timeout; dev->watchdog_timeo = (HZ >> 1); dev->dma = 0; - - ret = register_netdev(dev); + + ret = register_netdev (dev); if (ret) - goto out; + goto out_free_consistent; + return 0; - out: - if (dev->priv) - kfree(dev->priv); +out_free_consistent: + lan_saa9730_free_buffers(pdev, lp); +out_iounmap: + iounmap(lp->evm_saa9730_regs); +out_iounmap_lan: + iounmap(lp->lan_saa9730_regs); +out: return ret; } static int __devinit saa9730_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { - struct net_device *dev; - unsigned int pci_ioaddr; + struct net_device *dev = NULL; + unsigned long pci_ioaddr; int err; if (lan_saa9730_debug > 1) printk("saa9730.c: PCI bios is present, checking for devices...\n"); - err = -ENOMEM; - dev = alloc_etherdev(0); - if (!dev) - goto out; - - SET_MODULE_OWNER(dev); - err = pci_enable_device(pdev); - if (err) { - printk(KERN_ERR "Cannot enable PCI device, aborting.\n"); - goto out1; - } + if (err) { + printk(KERN_ERR "Cannot enable PCI device, aborting.\n"); + goto out; + } err = pci_request_regions(pdev, DRV_MODULE_NAME); if (err) { printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n"); - goto out2; + goto out_disable_pdev; } pci_irq_line = pdev->irq; @@ -1136,49 +1095,52 @@ pci_ioaddr = pci_resource_start(pdev, 1); pci_set_master(pdev); - printk("Found SAA9730 (PCI) at %#x, irq %d.\n", + printk("Found SAA9730 (PCI) at %lx, irq %d.\n", pci_ioaddr, pci_irq_line); - err = lan_saa9730_init(dev, pci_ioaddr, pci_irq_line); + dev = alloc_etherdev(sizeof(struct lan_saa9730_private)); + if (!dev) + goto out_disable_pdev; + + err = lan_saa9730_init(dev, pdev, pci_ioaddr, pci_irq_line); if (err) { - printk("Lan init failed"); - goto out2; + printk("LAN init failed"); + goto out_free_netdev; } pci_set_drvdata(pdev, dev); SET_NETDEV_DEV(dev, &pdev->dev); return 0; - -out2: - pci_disable_device(pdev); -out1: + +out_free_netdev: free_netdev(dev); +out_disable_pdev: + pci_disable_device(pdev); out: + pci_set_drvdata(pdev, NULL); return err; } static struct pci_driver saa9730_driver = { - .name = DRV_MODULE_NAME, - .id_table = saa9730_pci_tbl, - .probe = saa9730_init_one, - .remove = __devexit_p(saa9730_remove_one), + .name = DRV_MODULE_NAME, + .id_table = saa9730_pci_tbl, + .probe = saa9730_init_one, + .remove = __devexit_p(saa9730_remove_one), }; static int __init saa9730_init(void) { - return pci_module_init(&saa9730_driver); + return pci_module_init(&saa9730_driver); } static void __exit saa9730_cleanup(void) { - pci_unregister_driver(&saa9730_driver); + pci_unregister_driver(&saa9730_driver); } module_init(saa9730_init); module_exit(saa9730_cleanup); - - MODULE_LICENSE("GPL"); diff -Naur linux-2.6.12.6.orig/drivers/net/saa9730.h linux-2.6.12.6/drivers/net/saa9730.h --- linux-2.6.12.6.orig/drivers/net/saa9730.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/saa9730.h 2005-10-02 23:47:38.000000000 +0000 @@ -1,6 +1,7 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2000, 2005 MIPS Technologies, Inc. All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki * * ######################################################################## * @@ -265,6 +266,7 @@ /* The SAA9730 (LAN) controller register map, as seen via the PCI-bus. */ #define SAA9730_LAN_REGS_ADDR 0x20400 +#define SAA9730_LAN_REGS_SIZE 0x00400 struct lan_saa9730_regmap { volatile unsigned int TxBuffA; /* 0x20400 */ @@ -309,6 +311,7 @@ /* The SAA9730 (EVM) controller register map, as seen via the PCI-bus. */ #define SAA9730_EVM_REGS_ADDR 0x02000 +#define SAA9730_EVM_REGS_SIZE 0x00400 struct evm_saa9730_regmap { volatile unsigned int InterruptStatus1; /* 0x2000 */ @@ -329,16 +332,32 @@ struct lan_saa9730_private { + /* + * Rx/Tx packet buffers. + * The Rx and Tx packets must be PACKET_SIZE aligned. + */ + void *buffer_start; + unsigned int buffer_size; + + /* + * DMA address of beginning of this object, returned + * by pci_alloc_consistent(). + */ + dma_addr_t dma_addr; + + /* Pointer to the associated pci device structure */ + struct pci_dev *pci_dev; + /* Pointer for the SAA9730 LAN controller register set. */ t_lan_saa9730_regmap *lan_saa9730_regs; /* Pointer to the SAA9730 EVM register. */ t_evm_saa9730_regmap *evm_saa9730_regs; - /* TRUE if the next buffer to write is RxBuffA, FALSE if RxBuffB. */ - unsigned char NextRcvToUseIsA; /* Rcv buffer Index. */ unsigned char NextRcvPacketIndex; + /* Next buffer index. */ + unsigned char NextRcvBufferIndex; /* Index of next packet to use in that buffer. */ unsigned char NextTxmPacketIndex; @@ -353,13 +372,8 @@ unsigned char DmaRcvPackets; unsigned char DmaTxmPackets; - unsigned char RcvAIndex; /* index into RcvBufferSpace[] for Blk A */ - unsigned char RcvBIndex; /* index into RcvBufferSpace[] for Blk B */ - - unsigned int - TxmBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_TXM_Q_SIZE]; - unsigned int - RcvBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_RCV_Q_SIZE]; + void *TxmBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_TXM_Q_SIZE]; + void *RcvBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_RCV_Q_SIZE]; unsigned int TxBufferFree[LAN_SAA9730_BUFFERS]; unsigned char PhysicalAddress[LAN_SAA9730_CAM_ENTRIES][6]; diff -Naur linux-2.6.12.6.orig/drivers/net/sb1250-mac.c linux-2.6.12.6/drivers/net/sb1250-mac.c --- linux-2.6.12.6.orig/drivers/net/sb1250-mac.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/sb1250-mac.c 2005-10-02 23:47:38.000000000 +0000 @@ -2419,6 +2419,11 @@ if (err) goto out_uninit; + if (sc->rx_hw_checksum == ENABLE) { + printk(KERN_INFO "%s: enabling TCP rcv checksum\n", + sc->sbm_dev->name); + } + if (periph_rev >= 2) { printk(KERN_INFO "%s: enabling TCP rcv checksum\n", sc->sbm_dev->name); diff -Naur linux-2.6.12.6.orig/drivers/net/sgiseeq.c linux-2.6.12.6/drivers/net/sgiseeq.c --- linux-2.6.12.6.orig/drivers/net/sgiseeq.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/sgiseeq.c 2005-10-02 23:47:38.000000000 +0000 @@ -493,11 +493,13 @@ { struct sgiseeq_private *sp = netdev_priv(dev); struct sgiseeq_regs *sregs = sp->sregs; + unsigned int irq = dev->irq; netif_stop_queue(dev); /* Shutdown the Seeq. */ reset_hpc3_and_seeq(sp->hregs, sregs); + free_irq(irq, dev); return 0; } @@ -734,7 +736,7 @@ return 0; err_out_free_page: - free_page((unsigned long) sp); + free_page((unsigned long) sp->srings); err_out_free_dev: kfree(dev); @@ -754,15 +756,12 @@ { struct net_device *next, *dev; struct sgiseeq_private *sp; - int irq; for (dev = root_sgiseeq_dev; dev; dev = next) { sp = (struct sgiseeq_private *) netdev_priv(dev); next = sp->next_module; - irq = dev->irq; unregister_netdev(dev); - free_irq(irq, dev); - free_page((unsigned long) sp); + free_page((unsigned long) sp->srings); free_netdev(dev); } } diff -Naur linux-2.6.12.6.orig/drivers/net/titan_ge.c linux-2.6.12.6/drivers/net/titan_ge.c --- linux-2.6.12.6.orig/drivers/net/titan_ge.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/net/titan_ge.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,2071 @@ +/* + * drivers/net/titan_ge.c - Driver for Titan ethernet ports + * + * Copyright (C) 2003 PMC-Sierra Inc. + * Author : Manish Lachwani (lachwani@pmc-sierra.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * The MAC unit of the Titan consists of the following: + * + * -> XDMA Engine to move data to from the memory to the MAC packet FIFO + * -> FIFO is where the incoming and outgoing data is placed + * -> TRTG is the unit that pulls the data from the FIFO for Tx and pushes + * the data into the FIFO for Rx + * -> TMAC is the outgoing MAC interface and RMAC is the incoming. + * -> AFX is the address filtering block + * -> GMII block to communicate with the PHY + * + * Rx will look like the following: + * GMII --> RMAC --> AFX --> TRTG --> Rx FIFO --> XDMA --> CPU memory + * + * Tx will look like the following: + * CPU memory --> XDMA --> Tx FIFO --> TRTG --> TMAC --> GMII + * + * The Titan driver has support for the following performance features: + * -> Rx side checksumming + * -> Jumbo Frames + * -> Interrupt Coalscing + * -> Rx NAPI + * -> SKB Recycling + * -> Transmit/Receive descriptors in SRAM + * -> Fast routing for IP forwarding + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* For MII specifc registers, titan_mdio.h should be included */ +#include + +#include +#include +#include +#include +#include +#include + +#include "titan_ge.h" +#include "titan_mdio.h" + +/* Static Function Declarations */ +static int titan_ge_eth_open(struct net_device *); +static void titan_ge_eth_stop(struct net_device *); +static struct net_device_stats *titan_ge_get_stats(struct net_device *); +static int titan_ge_init_rx_desc_ring(titan_ge_port_info *, int, int, + unsigned long, unsigned long, + unsigned long); +static int titan_ge_init_tx_desc_ring(titan_ge_port_info *, int, + unsigned long, unsigned long); + +static int titan_ge_open(struct net_device *); +static int titan_ge_start_xmit(struct sk_buff *, struct net_device *); +static int titan_ge_stop(struct net_device *); + +static unsigned long titan_ge_tx_coal(unsigned long, int); + +static void titan_ge_port_reset(unsigned int); +static int titan_ge_free_tx_queue(titan_ge_port_info *); +static int titan_ge_rx_task(struct net_device *, titan_ge_port_info *); +static int titan_ge_port_start(struct net_device *, titan_ge_port_info *); + +static int titan_ge_return_tx_desc(titan_ge_port_info *, int); + +/* + * Some configuration for the FIFO and the XDMA channel needs + * to be done only once for all the ports. This flag controls + * that + */ +static unsigned long config_done; + +/* + * One time out of memory flag + */ +static unsigned int oom_flag; + +static int titan_ge_poll(struct net_device *netdev, int *budget); + +static int titan_ge_receive_queue(struct net_device *, unsigned int); + +static struct platform_device *titan_ge_device[3]; + +/* MAC Address */ +extern unsigned char titan_ge_mac_addr_base[6]; + +unsigned long titan_ge_base; +static unsigned long titan_ge_sram; + +static char titan_string[] = "titan"; + +/* + * The Titan GE has two alignment requirements: + * -> skb->data to be cacheline aligned (32 byte) + * -> IP header alignment to 16 bytes + * + * The latter is not implemented. So, that results in an extra copy on + * the Rx. This is a big performance hog. For the former case, the + * dev_alloc_skb() has been replaced with titan_ge_alloc_skb(). The size + * requested is calculated: + * + * Ethernet Frame Size : 1518 + * Ethernet Header : 14 + * Future Titan change for IP header alignment : 2 + * + * Hence, we allocate (1518 + 14 + 2+ 64) = 1580 bytes. For IP header + * alignment, we use skb_reserve(). + */ + +#define ALIGNED_RX_SKB_ADDR(addr) \ + ((((unsigned long)(addr) + (64UL - 1UL)) \ + & ~(64UL - 1UL)) - (unsigned long)(addr)) + +#define titan_ge_alloc_skb(__length, __gfp_flags) \ +({ struct sk_buff *__skb; \ + __skb = alloc_skb((__length) + 64, (__gfp_flags)); \ + if(__skb) { \ + int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \ + if(__offset) \ + skb_reserve(__skb, __offset); \ + } \ + __skb; \ +}) + +/* + * Configure the GMII block of the Titan based on what the PHY tells us + */ +static void titan_ge_gmii_config(int port_num) +{ + unsigned int reg_data = 0, phy_reg; + int err; + + err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg); + + if (err == TITAN_GE_MDIO_ERROR) { + printk(KERN_ERR + "Could not read PHY control register 0x11 \n"); + printk(KERN_ERR + "Setting speed to 1000 Mbps and Duplex to Full \n"); + + return; + } + + err = titan_ge_mdio_write(port_num, TITAN_GE_MDIO_PHY_IE, 0); + + if (phy_reg & 0x8000) { + if (phy_reg & 0x2000) { + /* Full Duplex and 1000 Mbps */ + TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE + + (port_num << 12)), 0x201); + } else { + /* Half Duplex and 1000 Mbps */ + TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE + + (port_num << 12)), 0x2201); + } + } + if (phy_reg & 0x4000) { + if (phy_reg & 0x2000) { + /* Full Duplex and 100 Mbps */ + TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE + + (port_num << 12)), 0x100); + } else { + /* Half Duplex and 100 Mbps */ + TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE + + (port_num << 12)), 0x2100); + } + } + reg_data = TITAN_GE_READ(TITAN_GE_GMII_CONFIG_GENERAL + + (port_num << 12)); + reg_data |= 0x3; + TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_GENERAL + + (port_num << 12)), reg_data); +} + +/* + * Enable the TMAC if it is not + */ +static void titan_ge_enable_tx(unsigned int port_num) +{ + unsigned long reg_data; + + reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)); + if (!(reg_data & 0x8000)) { + printk("TMAC disabled for port %d!! \n", port_num); + + reg_data |= 0x0001; /* Enable TMAC */ + reg_data |= 0x4000; /* CRC Check Enable */ + reg_data |= 0x2000; /* Padding enable */ + reg_data |= 0x0800; /* CRC Add enable */ + reg_data |= 0x0080; /* PAUSE frame */ + + TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + + (port_num << 12)), reg_data); + } +} + +/* + * Tx Timeout function + */ +static void titan_ge_tx_timeout(struct net_device *netdev) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + + printk(KERN_INFO "%s: TX timeout ", netdev->name); + printk(KERN_INFO "Resetting card \n"); + + /* Do the reset outside of interrupt context */ + schedule_work(&titan_ge_eth->tx_timeout_task); +} + +/* + * Update the AFX tables for UC and MC for slice 0 only + */ +static void titan_ge_update_afx(titan_ge_port_info * titan_ge_eth) +{ + int port = titan_ge_eth->port_num; + unsigned int i; + volatile unsigned long reg_data = 0; + u8 p_addr[6]; + + memcpy(p_addr, titan_ge_eth->port_mac_addr, 6); + + /* Set the MAC address here for TMAC and RMAC */ + TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port << 12)), + ((p_addr[5] << 8) | p_addr[4])); + TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port << 12)), + ((p_addr[3] << 8) | p_addr[2])); + TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port << 12)), + ((p_addr[1] << 8) | p_addr[0])); + + TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port << 12)), + ((p_addr[5] << 8) | p_addr[4])); + TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port << 12)), + ((p_addr[3] << 8) | p_addr[2])); + TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port << 12)), + ((p_addr[1] << 8) | p_addr[0])); + + TITAN_GE_WRITE((0x112c | (port << 12)), 0x1); + /* Configure the eight address filters */ + for (i = 0; i < 8; i++) { + /* Select each of the eight filters */ + TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 + + (port << 12)), i); + + /* Configure the match */ + reg_data = 0x9; /* Forward Enable Bit */ + TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 + + (port << 12)), reg_data); + + /* Finally, AFX Exact Match Address Registers */ + TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_LOW + (port << 12)), + ((p_addr[1] << 8) | p_addr[0])); + TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_MID + (port << 12)), + ((p_addr[3] << 8) | p_addr[2])); + TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_HIGH + (port << 12)), + ((p_addr[5] << 8) | p_addr[4])); + + /* VLAN id set to 0 */ + TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_VID + + (port << 12)), 0); + } +} + +/* + * Actual Routine to reset the adapter when the timeout occurred + */ +static void titan_ge_tx_timeout_task(struct net_device *netdev) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + int port = titan_ge_eth->port_num; + + printk("Titan GE: Transmit timed out. Resetting ... \n"); + + /* Dump debug info */ + printk(KERN_ERR "TRTG cause : %x \n", + TITAN_GE_READ(0x100c + (port << 12))); + + /* Fix this for the other ports */ + printk(KERN_ERR "FIFO cause : %x \n", TITAN_GE_READ(0x482c)); + printk(KERN_ERR "IE cause : %x \n", TITAN_GE_READ(0x0040)); + printk(KERN_ERR "XDMA GDI ERROR : %x \n", + TITAN_GE_READ(0x5008 + (port << 8))); + printk(KERN_ERR "CHANNEL ERROR: %x \n", + TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT + + (port << 8))); + + netif_device_detach(netdev); + titan_ge_port_reset(titan_ge_eth->port_num); + titan_ge_port_start(netdev, titan_ge_eth); + netif_device_attach(netdev); +} + +/* + * Change the MTU of the Ethernet Device + */ +static int titan_ge_change_mtu(struct net_device *netdev, int new_mtu) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + unsigned long flags; + + if ((new_mtu > 9500) || (new_mtu < 64)) + return -EINVAL; + + spin_lock_irqsave(&titan_ge_eth->lock, flags); + + netdev->mtu = new_mtu; + + /* Now we have to reopen the interface so that SKBs with the new + * size will be allocated */ + + if (netif_running(netdev)) { + titan_ge_eth_stop(netdev); + + if (titan_ge_eth_open(netdev) != TITAN_OK) { + printk(KERN_ERR + "%s: Fatal error on opening device\n", + netdev->name); + spin_unlock_irqrestore(&titan_ge_eth->lock, flags); + return -1; + } + } + + spin_unlock_irqrestore(&titan_ge_eth->lock, flags); + return 0; +} + +/* + * Titan Gbe Interrupt Handler. All the three ports send interrupt to one line + * only. Once an interrupt is triggered, figure out the port and then check + * the channel. + */ +static irqreturn_t titan_ge_int_handler(int irq, void *dev_id, + struct pt_regs *regs) +{ + struct net_device *netdev = (struct net_device *) dev_id; + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + unsigned int port_num = titan_ge_eth->port_num; + unsigned int reg_data; + unsigned int eth_int_cause_error = 0, is; + unsigned long eth_int_cause1; + int err = 0; +#ifdef CONFIG_SMP + unsigned long eth_int_cause2; +#endif + + /* Ack the CPU interrupt */ + switch (port_num) { + case 0: + is = OCD_READ(RM9000x2_OCD_INTP0STATUS1); + OCD_WRITE(RM9000x2_OCD_INTP0CLEAR1, is); + +#ifdef CONFIG_SMP + is = OCD_READ(RM9000x2_OCD_INTP1STATUS1); + OCD_WRITE(RM9000x2_OCD_INTP1CLEAR1, is); +#endif + break; + + case 1: + is = OCD_READ(RM9000x2_OCD_INTP0STATUS0); + OCD_WRITE(RM9000x2_OCD_INTP0CLEAR0, is); + +#ifdef CONFIG_SMP + is = OCD_READ(RM9000x2_OCD_INTP1STATUS0); + OCD_WRITE(RM9000x2_OCD_INTP1CLEAR0, is); +#endif + break; + + case 2: + is = OCD_READ(RM9000x2_OCD_INTP0STATUS4); + OCD_WRITE(RM9000x2_OCD_INTP0CLEAR4, is); + +#ifdef CONFIG_SMP + is = OCD_READ(RM9000x2_OCD_INTP1STATUS4); + OCD_WRITE(RM9000x2_OCD_INTP1CLEAR4, is); +#endif + } + + eth_int_cause1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A); +#ifdef CONFIG_SMP + eth_int_cause2 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_B); +#endif + + /* Spurious interrupt */ +#ifdef CONFIG_SMP + if ( (eth_int_cause1 == 0) && (eth_int_cause2 == 0)) { +#else + if (eth_int_cause1 == 0) { +#endif + eth_int_cause_error = TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT + + (port_num << 8)); + + if (eth_int_cause_error == 0) + return IRQ_NONE; + } + + /* Handle Tx first. No need to ack interrupts */ +#ifdef CONFIG_SMP + if ( (eth_int_cause1 & 0x20202) || + (eth_int_cause2 & 0x20202) ) +#else + if (eth_int_cause1 & 0x20202) +#endif + titan_ge_free_tx_queue(titan_ge_eth); + + /* Handle the Rx next */ +#ifdef CONFIG_SMP + if ( (eth_int_cause1 & 0x10101) || + (eth_int_cause2 & 0x10101)) { +#else + if (eth_int_cause1 & 0x10101) { +#endif + if (netif_rx_schedule_prep(netdev)) { + unsigned int ack; + + ack = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE); + /* Disable Tx and Rx both */ + if (port_num == 0) + ack &= ~(0x3); + if (port_num == 1) + ack &= ~(0x300); + + if (port_num == 2) + ack &= ~(0x30000); + + /* Interrupts have been disabled */ + TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, ack); + + __netif_rx_schedule(netdev); + } + } + + /* Handle error interrupts */ + if (eth_int_cause_error && (eth_int_cause_error != 0x2)) { + printk(KERN_ERR + "XDMA Channel Error : %x on port %d\n", + eth_int_cause_error, port_num); + + printk(KERN_ERR + "XDMA GDI Hardware error : %x on port %d\n", + TITAN_GE_READ(0x5008 + (port_num << 8)), port_num); + + printk(KERN_ERR + "XDMA currently has %d Rx descriptors \n", + TITAN_GE_READ(0x5048 + (port_num << 8))); + + printk(KERN_ERR + "XDMA currently has prefetcted %d Rx descriptors \n", + TITAN_GE_READ(0x505c + (port_num << 8))); + + TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT + + (port_num << 8)), eth_int_cause_error); + } + + /* + * PHY interrupt to inform abt the changes. Reading the + * PHY Status register will clear the interrupt + */ + if ((!(eth_int_cause1 & 0x30303)) && + (eth_int_cause_error == 0)) { + err = + titan_ge_mdio_read(port_num, + TITAN_GE_MDIO_PHY_IS, ®_data); + + if (reg_data & 0x0400) { + /* Link status change */ + titan_ge_mdio_read(port_num, + TITAN_GE_MDIO_PHY_STATUS, ®_data); + if (!(reg_data & 0x0400)) { + /* Link is down */ + netif_carrier_off(netdev); + netif_stop_queue(netdev); + } else { + /* Link is up */ + netif_carrier_on(netdev); + netif_wake_queue(netdev); + + /* Enable the queue */ + titan_ge_enable_tx(port_num); + } + } + } + + return IRQ_HANDLED; +} + +/* + * Multicast and Promiscuous mode set. The + * set_multi entry point is called whenever the + * multicast address list or the network interface + * flags are updated. + */ +static void titan_ge_set_multi(struct net_device *netdev) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + unsigned int port_num = titan_ge_eth->port_num; + unsigned long reg_data; + + reg_data = TITAN_GE_READ(TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 + + (port_num << 12)); + + if (netdev->flags & IFF_PROMISC) { + reg_data |= 0x2; + } + else if (netdev->flags & IFF_ALLMULTI) { + reg_data |= 0x01; + reg_data |= 0x400; /* Use the 64-bit Multicast Hash bin */ + } + else { + reg_data = 0x2; + } + + TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 + + (port_num << 12)), reg_data); + if (reg_data & 0x01) { + TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_LOW + + (port_num << 12)), 0xffff); + TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDLOW + + (port_num << 12)), 0xffff); + TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDHI + + (port_num << 12)), 0xffff); + TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_HI + + (port_num << 12)), 0xffff); + } +} + +/* + * Open the network device + */ +static int titan_ge_open(struct net_device *netdev) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + unsigned int port_num = titan_ge_eth->port_num; + unsigned int irq = TITAN_ETH_PORT_IRQ - port_num; + int retval; + + retval = request_irq(irq, titan_ge_int_handler, + SA_INTERRUPT | SA_SAMPLE_RANDOM , netdev->name, netdev); + + if (retval != 0) { + printk(KERN_ERR "Cannot assign IRQ number to TITAN GE \n"); + return -1; + } + + netdev->irq = irq; + printk(KERN_INFO "Assigned IRQ %d to port %d\n", irq, port_num); + + spin_lock_irq(&(titan_ge_eth->lock)); + + if (titan_ge_eth_open(netdev) != TITAN_OK) { + spin_unlock_irq(&(titan_ge_eth->lock)); + printk("%s: Error opening interface \n", netdev->name); + free_irq(netdev->irq, netdev); + return -EBUSY; + } + + spin_unlock_irq(&(titan_ge_eth->lock)); + + return 0; +} + +/* + * Allocate the SKBs for the Rx ring. Also used + * for refilling the queue + */ +static int titan_ge_rx_task(struct net_device *netdev, + titan_ge_port_info *titan_ge_port) +{ + struct device *device = &titan_ge_device[titan_ge_port->port_num]->dev; + volatile titan_ge_rx_desc *rx_desc; + struct sk_buff *skb; + int rx_used_desc; + int count = 0; + + while (titan_ge_port->rx_ring_skbs < titan_ge_port->rx_ring_size) { + + /* First try to get the skb from the recycler */ +#ifdef TITAN_GE_JUMBO_FRAMES + skb = titan_ge_alloc_skb(TITAN_GE_JUMBO_BUFSIZE, GFP_ATOMIC); +#else + skb = titan_ge_alloc_skb(TITAN_GE_STD_BUFSIZE, GFP_ATOMIC); +#endif + if (unlikely(!skb)) { + /* OOM, set the flag */ + printk("OOM \n"); + oom_flag = 1; + break; + } + count++; + skb->dev = netdev; + + titan_ge_port->rx_ring_skbs++; + + rx_used_desc = titan_ge_port->rx_used_desc_q; + rx_desc = &(titan_ge_port->rx_desc_area[rx_used_desc]); + +#ifdef TITAN_GE_JUMBO_FRAMES + rx_desc->buffer_addr = dma_map_single(device, skb->data, + TITAN_GE_JUMBO_BUFSIZE - 2, DMA_FROM_DEVICE); +#else + rx_desc->buffer_addr = dma_map_single(device, skb->data, + TITAN_GE_STD_BUFSIZE - 2, DMA_FROM_DEVICE); +#endif + + titan_ge_port->rx_skb[rx_used_desc] = skb; + rx_desc->cmd_sts = TITAN_GE_RX_BUFFER_OWNED; + + titan_ge_port->rx_used_desc_q = + (rx_used_desc + 1) % TITAN_GE_RX_QUEUE; + } + + return count; +} + +/* + * Actual init of the Tital GE port. There is one register for + * the channel configuration + */ +static void titan_port_init(struct net_device *netdev, + titan_ge_port_info * titan_ge_eth) +{ + unsigned long reg_data; + + titan_ge_port_reset(titan_ge_eth->port_num); + + /* First reset the TMAC */ + reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG); + reg_data |= 0x80000000; + TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data); + + udelay(30); + + reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG); + reg_data &= ~(0xc0000000); + TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data); + + /* Now reset the RMAC */ + reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG); + reg_data |= 0x00080000; + TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data); + + udelay(30); + + reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG); + reg_data &= ~(0x000c0000); + TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data); +} + +/* + * Start the port. All the hardware specific configuration + * for the XDMA, Tx FIFO, Rx FIFO, TMAC, RMAC, TRTG and AFX + * go here + */ +static int titan_ge_port_start(struct net_device *netdev, + titan_ge_port_info * titan_port) +{ + volatile unsigned long reg_data, reg_data1; + int port_num = titan_port->port_num; + int count = 0; + unsigned long reg_data_1; + + if (config_done == 0) { + reg_data = TITAN_GE_READ(0x0004); + reg_data |= 0x100; + TITAN_GE_WRITE(0x0004, reg_data); + + reg_data &= ~(0x100); + TITAN_GE_WRITE(0x0004, reg_data); + + /* Turn on GMII/MII mode and turn off TBI mode */ + reg_data = TITAN_GE_READ(TITAN_GE_TSB_CTRL_1); + reg_data |= 0x00000700; + reg_data &= ~(0x00800000); /* Fencing */ + + TITAN_GE_WRITE(0x000c, 0x00001100); + + TITAN_GE_WRITE(TITAN_GE_TSB_CTRL_1, reg_data); + + /* Set the CPU Resource Limit register */ + TITAN_GE_WRITE(0x00f8, 0x8); + + /* Be conservative when using the BIU buffers */ + TITAN_GE_WRITE(0x0068, 0x4); + } + + titan_port->tx_threshold = 0; + titan_port->rx_threshold = 0; + + /* We need to write the descriptors for Tx and Rx */ + TITAN_GE_WRITE((TITAN_GE_CHANNEL0_TX_DESC + (port_num << 8)), + (unsigned long) titan_port->tx_dma); + TITAN_GE_WRITE((TITAN_GE_CHANNEL0_RX_DESC + (port_num << 8)), + (unsigned long) titan_port->rx_dma); + + if (config_done == 0) { + /* Step 1: XDMA config */ + reg_data = TITAN_GE_READ(TITAN_GE_XDMA_CONFIG); + reg_data &= ~(0x80000000); /* clear reset */ + reg_data |= 0x1 << 29; /* sparse tx descriptor spacing */ + reg_data |= 0x1 << 28; /* sparse rx descriptor spacing */ + reg_data |= (0x1 << 23) | (0x1 << 24); /* Descriptor Coherency */ + reg_data |= (0x1 << 21) | (0x1 << 22); /* Data Coherency */ + TITAN_GE_WRITE(TITAN_GE_XDMA_CONFIG, reg_data); + } + + /* IR register for the XDMA */ + reg_data = TITAN_GE_READ(TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8)); + reg_data |= 0x80068000; /* No Rx_OOD */ + TITAN_GE_WRITE((TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8)), reg_data); + + /* Start the Tx and Rx XDMA controller */ + reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + (port_num << 8)); + reg_data &= 0x4fffffff; /* Clear tx reset */ + reg_data &= 0xfff4ffff; /* Clear rx reset */ + +#ifdef TITAN_GE_JUMBO_FRAMES + reg_data |= 0xa0 | 0x30030000; +#else + reg_data |= 0x40 | 0x20030000; +#endif + +#ifndef CONFIG_SMP + reg_data &= ~(0x10); + reg_data |= 0x0f; /* All of the packet */ +#endif + + TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + (port_num << 8)), reg_data); + + /* Rx desc count */ + count = titan_ge_rx_task(netdev, titan_port); + TITAN_GE_WRITE((0x5048 + (port_num << 8)), count); + count = TITAN_GE_READ(0x5048 + (port_num << 8)); + + udelay(30); + + /* + * Step 2: Configure the SDQPF, i.e. FIFO + */ + if (config_done == 0) { + reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL); + reg_data = 0x1; + TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data); + reg_data &= ~(0x1); + TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data); + reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL); + TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data); + + reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL); + reg_data = 0x1; + TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data); + reg_data &= ~(0x1); + TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data); + reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL); + TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data); + } + /* + * Enable RX FIFO 0, 4 and 8 + */ + if (port_num == 0) { + reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_0); + + reg_data |= 0x100000; + reg_data |= (0xff << 10); + + TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data); + /* + * BAV2,BAV and DAV settings for the Rx FIFO + */ + reg_data1 = TITAN_GE_READ(0x4844); + reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1); + TITAN_GE_WRITE(0x4844, reg_data1); + + reg_data &= ~(0x00100000); + reg_data |= 0x200000; + + TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data); + + reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_0); + reg_data |= 0x100000; + + TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data); + + reg_data |= (0xff << 10); + + TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data); + + /* + * BAV2, BAV and DAV settings for the Tx FIFO + */ + reg_data1 = TITAN_GE_READ(0x4944); + reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10); + + TITAN_GE_WRITE(0x4944, reg_data1); + + reg_data &= ~(0x00100000); + reg_data |= 0x200000; + + TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data); + + } + + if (port_num == 1) { + reg_data = TITAN_GE_READ(0x4870); + + reg_data |= 0x100000; + reg_data |= (0xff << 10) | (0xff + 1); + + TITAN_GE_WRITE(0x4870, reg_data); + /* + * BAV2,BAV and DAV settings for the Rx FIFO + */ + reg_data1 = TITAN_GE_READ(0x4874); + reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1); + TITAN_GE_WRITE(0x4874, reg_data1); + + reg_data &= ~(0x00100000); + reg_data |= 0x200000; + + TITAN_GE_WRITE(0x4870, reg_data); + + reg_data = TITAN_GE_READ(0x494c); + reg_data |= 0x100000; + + TITAN_GE_WRITE(0x494c, reg_data); + reg_data |= (0xff << 10) | (0xff + 1); + TITAN_GE_WRITE(0x494c, reg_data); + + /* + * BAV2, BAV and DAV settings for the Tx FIFO + */ + reg_data1 = TITAN_GE_READ(0x4950); + reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10); + + TITAN_GE_WRITE(0x4950, reg_data1); + + reg_data &= ~(0x00100000); + reg_data |= 0x200000; + + TITAN_GE_WRITE(0x494c, reg_data); + } + + /* + * Titan 1.2 revision does support port #2 + */ + if (port_num == 2) { + /* + * Put the descriptors in the SRAM + */ + reg_data = TITAN_GE_READ(0x48a0); + + reg_data |= 0x100000; + reg_data |= (0xff << 10) | (2*(0xff + 1)); + + TITAN_GE_WRITE(0x48a0, reg_data); + /* + * BAV2,BAV and DAV settings for the Rx FIFO + */ + reg_data1 = TITAN_GE_READ(0x48a4); + reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1); + TITAN_GE_WRITE(0x48a4, reg_data1); + + reg_data &= ~(0x00100000); + reg_data |= 0x200000; + + TITAN_GE_WRITE(0x48a0, reg_data); + + reg_data = TITAN_GE_READ(0x4958); + reg_data |= 0x100000; + + TITAN_GE_WRITE(0x4958, reg_data); + reg_data |= (0xff << 10) | (2*(0xff + 1)); + TITAN_GE_WRITE(0x4958, reg_data); + + /* + * BAV2, BAV and DAV settings for the Tx FIFO + */ + reg_data1 = TITAN_GE_READ(0x495c); + reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10); + + TITAN_GE_WRITE(0x495c, reg_data1); + + reg_data &= ~(0x00100000); + reg_data |= 0x200000; + + TITAN_GE_WRITE(0x4958, reg_data); + } + + if (port_num == 2) { + reg_data = TITAN_GE_READ(0x48a0); + + reg_data |= 0x100000; + reg_data |= (0xff << 10) | (2*(0xff + 1)); + + TITAN_GE_WRITE(0x48a0, reg_data); + /* + * BAV2,BAV and DAV settings for the Rx FIFO + */ + reg_data1 = TITAN_GE_READ(0x48a4); + reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1); + TITAN_GE_WRITE(0x48a4, reg_data1); + + reg_data &= ~(0x00100000); + reg_data |= 0x200000; + + TITAN_GE_WRITE(0x48a0, reg_data); + + reg_data = TITAN_GE_READ(0x4958); + reg_data |= 0x100000; + + TITAN_GE_WRITE(0x4958, reg_data); + reg_data |= (0xff << 10) | (2*(0xff + 1)); + TITAN_GE_WRITE(0x4958, reg_data); + + /* + * BAV2, BAV and DAV settings for the Tx FIFO + */ + reg_data1 = TITAN_GE_READ(0x495c); + reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10); + + TITAN_GE_WRITE(0x495c, reg_data1); + + reg_data &= ~(0x00100000); + reg_data |= 0x200000; + + TITAN_GE_WRITE(0x4958, reg_data); + } + + /* + * Step 3: TRTG block enable + */ + reg_data = TITAN_GE_READ(TITAN_GE_TRTG_CONFIG + (port_num << 12)); + + /* + * This is the 1.2 revision of the chip. It has fix for the + * IP header alignment. Now, the IP header begins at an + * aligned address and this wont need an extra copy in the + * driver. This performance drawback existed in the previous + * versions of the silicon + */ + reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12)); + reg_data_1 |= 0x40000000; + TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); + + reg_data_1 |= 0x04000000; + TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); + + mdelay(5); + + reg_data_1 &= ~(0x04000000); + TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); + + mdelay(5); + + reg_data |= 0x0001; + TITAN_GE_WRITE((TITAN_GE_TRTG_CONFIG + (port_num << 12)), reg_data); + + /* + * Step 4: Start the Tx activity + */ + TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_2 + (port_num << 12)), 0xe197); +#ifdef TITAN_GE_JUMBO_FRAMES + TITAN_GE_WRITE((0x1258 + (port_num << 12)), 0x4000); +#endif + reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)); + reg_data |= 0x0001; /* Enable TMAC */ + reg_data |= 0x6c70; /* PAUSE also set */ + + TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)), reg_data); + + udelay(30); + + /* Destination Address drop bit */ + reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_2 + (port_num << 12)); + reg_data |= 0x218; /* DA_DROP bit and pause */ + TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_2 + (port_num << 12)), reg_data); + + TITAN_GE_WRITE((0x1218 + (port_num << 12)), 0x3); + +#ifdef TITAN_GE_JUMBO_FRAMES + TITAN_GE_WRITE((0x1208 + (port_num << 12)), 0x4000); +#endif + /* Start the Rx activity */ + reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)); + reg_data |= 0x0001; /* RMAC Enable */ + reg_data |= 0x0010; /* CRC Check enable */ + reg_data |= 0x0040; /* Min Frame check enable */ + reg_data |= 0x4400; /* Max Frame check enable */ + + TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data); + + udelay(30); + + /* + * Enable the Interrupts for Tx and Rx + */ + reg_data1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE); + + if (port_num == 0) { + reg_data1 |= 0x3; +#ifdef CONFIG_SMP + TITAN_GE_WRITE(0x0038, 0x003); +#else + TITAN_GE_WRITE(0x0038, 0x303); +#endif + } + + if (port_num == 1) { + reg_data1 |= 0x300; + } + + if (port_num == 2) + reg_data1 |= 0x30000; + + TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1); + TITAN_GE_WRITE(0x003c, 0x300); + + if (config_done == 0) { + TITAN_GE_WRITE(0x0024, 0x04000024); /* IRQ vector */ + TITAN_GE_WRITE(0x0020, 0x000fb000); /* INTMSG base */ + } + + /* Priority */ + reg_data = TITAN_GE_READ(0x1038 + (port_num << 12)); + reg_data &= ~(0x00f00000); + TITAN_GE_WRITE((0x1038 + (port_num << 12)), reg_data); + + /* Step 5: GMII config */ + titan_ge_gmii_config(port_num); + + if (config_done == 0) { + TITAN_GE_WRITE(0x1a80, 0); + config_done = 1; + } + + return TITAN_OK; +} + +/* + * Function to queue the packet for the Ethernet device + */ +static void titan_ge_tx_queue(titan_ge_port_info * titan_ge_eth, + struct sk_buff * skb) +{ + struct device *device = &titan_ge_device[titan_ge_eth->port_num]->dev; + unsigned int curr_desc = titan_ge_eth->tx_curr_desc_q; + volatile titan_ge_tx_desc *tx_curr; + int port_num = titan_ge_eth->port_num; + + tx_curr = &(titan_ge_eth->tx_desc_area[curr_desc]); + tx_curr->buffer_addr = + dma_map_single(device, skb->data, skb_headlen(skb), + DMA_TO_DEVICE); + + titan_ge_eth->tx_skb[curr_desc] = (struct sk_buff *) skb; + tx_curr->buffer_len = skb_headlen(skb); + + /* Last descriptor enables interrupt and changes ownership */ + tx_curr->cmd_sts = 0x1 | (1 << 15) | (1 << 5); + + /* Kick the XDMA to start the transfer from memory to the FIFO */ + TITAN_GE_WRITE((0x5044 + (port_num << 8)), 0x1); + + /* Current descriptor updated */ + titan_ge_eth->tx_curr_desc_q = (curr_desc + 1) % TITAN_GE_TX_QUEUE; + + /* Prefetch the next descriptor */ + prefetch((const void *) + &titan_ge_eth->tx_desc_area[titan_ge_eth->tx_curr_desc_q]); +} + +/* + * Actually does the open of the Ethernet device + */ +static int titan_ge_eth_open(struct net_device *netdev) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + unsigned int port_num = titan_ge_eth->port_num; + struct device *device = &titan_ge_device[port_num]->dev; + unsigned long reg_data; + unsigned int phy_reg; + int err = 0; + + /* Stop the Rx activity */ + reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)); + reg_data &= ~(0x00000001); + TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data); + + /* Clear the port interrupts */ + TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT + (port_num << 8)), 0x0); + + if (config_done == 0) { + TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0); + TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_B, 0); + } + + /* Set the MAC Address */ + memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6); + + if (config_done == 0) + titan_port_init(netdev, titan_ge_eth); + + titan_ge_update_afx(titan_ge_eth); + + /* Allocate the Tx ring now */ + titan_ge_eth->tx_ring_skbs = 0; + titan_ge_eth->tx_ring_size = TITAN_GE_TX_QUEUE; + + /* Allocate space in the SRAM for the descriptors */ + titan_ge_eth->tx_desc_area = (titan_ge_tx_desc *) + (titan_ge_sram + TITAN_TX_RING_BYTES * port_num); + titan_ge_eth->tx_dma = TITAN_SRAM_BASE + TITAN_TX_RING_BYTES * port_num; + + if (!titan_ge_eth->tx_desc_area) { + printk(KERN_ERR + "%s: Cannot allocate Tx Ring (size %d bytes) for port %d\n", + netdev->name, TITAN_TX_RING_BYTES, port_num); + return -ENOMEM; + } + + memset(titan_ge_eth->tx_desc_area, 0, titan_ge_eth->tx_desc_area_size); + + /* Now initialize the Tx descriptor ring */ + titan_ge_init_tx_desc_ring(titan_ge_eth, + titan_ge_eth->tx_ring_size, + (unsigned long) titan_ge_eth->tx_desc_area, + (unsigned long) titan_ge_eth->tx_dma); + + /* Allocate the Rx ring now */ + titan_ge_eth->rx_ring_size = TITAN_GE_RX_QUEUE; + titan_ge_eth->rx_ring_skbs = 0; + + titan_ge_eth->rx_desc_area = + (titan_ge_rx_desc *)(titan_ge_sram + 0x1000 + TITAN_RX_RING_BYTES * port_num); + + titan_ge_eth->rx_dma = TITAN_SRAM_BASE + 0x1000 + TITAN_RX_RING_BYTES * port_num; + + if (!titan_ge_eth->rx_desc_area) { + printk(KERN_ERR "%s: Cannot allocate Rx Ring (size %d bytes)\n", + netdev->name, TITAN_RX_RING_BYTES); + + printk(KERN_ERR "%s: Freeing previously allocated TX queues...", + netdev->name); + + dma_free_coherent(device, titan_ge_eth->tx_desc_area_size, + (void *) titan_ge_eth->tx_desc_area, + titan_ge_eth->tx_dma); + + return -ENOMEM; + } + + memset(titan_ge_eth->rx_desc_area, 0, titan_ge_eth->rx_desc_area_size); + + /* Now initialize the Rx ring */ +#ifdef TITAN_GE_JUMBO_FRAMES + if ((titan_ge_init_rx_desc_ring + (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_JUMBO_BUFSIZE, + (unsigned long) titan_ge_eth->rx_desc_area, 0, + (unsigned long) titan_ge_eth->rx_dma)) == 0) +#else + if ((titan_ge_init_rx_desc_ring + (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_STD_BUFSIZE, + (unsigned long) titan_ge_eth->rx_desc_area, 0, + (unsigned long) titan_ge_eth->rx_dma)) == 0) +#endif + panic("%s: Error initializing RX Ring\n", netdev->name); + + /* Fill the Rx ring with the SKBs */ + titan_ge_port_start(netdev, titan_ge_eth); + + /* + * Check if Interrupt Coalscing needs to be turned on. The + * values specified in the register is multiplied by + * (8 x 64 nanoseconds) to determine when an interrupt should + * be sent to the CPU. + */ + + if (TITAN_GE_TX_COAL) { + titan_ge_eth->tx_int_coal = + titan_ge_tx_coal(TITAN_GE_TX_COAL, port_num); + } + + err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg); + if (err == TITAN_GE_MDIO_ERROR) { + printk(KERN_ERR + "Could not read PHY control register 0x11 \n"); + return TITAN_ERROR; + } + if (!(phy_reg & 0x0400)) { + netif_carrier_off(netdev); + netif_stop_queue(netdev); + return TITAN_ERROR; + } else { + netif_carrier_on(netdev); + netif_start_queue(netdev); + } + + return TITAN_OK; +} + +/* + * Queue the packet for Tx. Currently no support for zero copy, + * checksum offload and Scatter Gather. The chip does support + * Scatter Gather only. But, that wont help here since zero copy + * requires support for Tx checksumming also. + */ +int titan_ge_start_xmit(struct sk_buff *skb, struct net_device *netdev) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + unsigned long flags; + struct net_device_stats *stats; +//printk("titan_ge_start_xmit\n"); + + stats = &titan_ge_eth->stats; + spin_lock_irqsave(&titan_ge_eth->lock, flags); + + if ((TITAN_GE_TX_QUEUE - titan_ge_eth->tx_ring_skbs) <= + (skb_shinfo(skb)->nr_frags + 1)) { + netif_stop_queue(netdev); + spin_unlock_irqrestore(&titan_ge_eth->lock, flags); + printk(KERN_ERR "Tx OOD \n"); + return 1; + } + + titan_ge_tx_queue(titan_ge_eth, skb); + titan_ge_eth->tx_ring_skbs++; + + if (TITAN_GE_TX_QUEUE <= (titan_ge_eth->tx_ring_skbs + 4)) { + spin_unlock_irqrestore(&titan_ge_eth->lock, flags); + titan_ge_free_tx_queue(titan_ge_eth); + spin_lock_irqsave(&titan_ge_eth->lock, flags); + } + + stats->tx_bytes += skb->len; + stats->tx_packets++; + + spin_unlock_irqrestore(&titan_ge_eth->lock, flags); + + netdev->trans_start = jiffies; + + return 0; +} + +/* + * Actually does the Rx. Rx side checksumming supported. + */ +static int titan_ge_rx(struct net_device *netdev, int port_num, + titan_ge_port_info * titan_ge_port, + titan_ge_packet * packet) +{ + int rx_curr_desc, rx_used_desc; + volatile titan_ge_rx_desc *rx_desc; + + rx_curr_desc = titan_ge_port->rx_curr_desc_q; + rx_used_desc = titan_ge_port->rx_used_desc_q; + + if (((rx_curr_desc + 1) % TITAN_GE_RX_QUEUE) == rx_used_desc) + return TITAN_ERROR; + + rx_desc = &(titan_ge_port->rx_desc_area[rx_curr_desc]); + + if (rx_desc->cmd_sts & TITAN_GE_RX_BUFFER_OWNED) + return TITAN_ERROR; + + packet->skb = titan_ge_port->rx_skb[rx_curr_desc]; + packet->len = (rx_desc->cmd_sts & 0x7fff); + + /* + * At this point, we dont know if the checksumming + * actually helps relieve CPU. So, keep it for + * port 0 only + */ + packet->checksum = ntohs((rx_desc->buffer & 0xffff0000) >> 16); + packet->cmd_sts = rx_desc->cmd_sts; + + titan_ge_port->rx_curr_desc_q = (rx_curr_desc + 1) % TITAN_GE_RX_QUEUE; + + /* Prefetch the next descriptor */ + prefetch((const void *) + &titan_ge_port->rx_desc_area[titan_ge_port->rx_curr_desc_q + 1]); + + return TITAN_OK; +} + +/* + * Free the Tx queue of the used SKBs + */ +static int titan_ge_free_tx_queue(titan_ge_port_info *titan_ge_eth) +{ + unsigned long flags; + + /* Take the lock */ + spin_lock_irqsave(&(titan_ge_eth->lock), flags); + + while (titan_ge_return_tx_desc(titan_ge_eth, titan_ge_eth->port_num) == 0) + if (titan_ge_eth->tx_ring_skbs != 1) + titan_ge_eth->tx_ring_skbs--; + + spin_unlock_irqrestore(&titan_ge_eth->lock, flags); + + return TITAN_OK; +} + +/* + * Threshold beyond which we do the cleaning of + * Tx queue and new allocation for the Rx + * queue + */ +#define TX_THRESHOLD 4 +#define RX_THRESHOLD 10 + +/* + * Receive the packets and send it to the kernel. + */ +static int titan_ge_receive_queue(struct net_device *netdev, unsigned int max) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + unsigned int port_num = titan_ge_eth->port_num; + titan_ge_packet packet; + struct net_device_stats *stats; + struct sk_buff *skb; + unsigned long received_packets = 0; + unsigned int ack; + + stats = &titan_ge_eth->stats; + + while ((--max) + && (titan_ge_rx(netdev, port_num, titan_ge_eth, &packet) == TITAN_OK)) { + skb = (struct sk_buff *) packet.skb; + + titan_ge_eth->rx_ring_skbs--; + + if (--titan_ge_eth->rx_work_limit < 0) + break; + received_packets++; + + stats->rx_packets++; + stats->rx_bytes += packet.len; + + if ((packet.cmd_sts & TITAN_GE_RX_PERR) || + (packet.cmd_sts & TITAN_GE_RX_OVERFLOW_ERROR) || + (packet.cmd_sts & TITAN_GE_RX_TRUNC) || + (packet.cmd_sts & TITAN_GE_RX_CRC_ERROR)) { + stats->rx_dropped++; + dev_kfree_skb_any(skb); + + continue; + } + /* + * Either support fast path or slow path. Decision + * making can really slow down the performance. The + * idea is to cut down the number of checks and improve + * the fastpath. + */ + + skb_put(skb, packet.len - 2); + + /* + * Increment data pointer by two since thats where + * the MAC starts + */ + skb_reserve(skb, 2); + skb->protocol = eth_type_trans(skb, netdev); + netif_receive_skb(skb); + + if (titan_ge_eth->rx_threshold > RX_THRESHOLD) { + ack = titan_ge_rx_task(netdev, titan_ge_eth); + TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack); + titan_ge_eth->rx_threshold = 0; + } else + titan_ge_eth->rx_threshold++; + + if (titan_ge_eth->tx_threshold > TX_THRESHOLD) { + titan_ge_eth->tx_threshold = 0; + titan_ge_free_tx_queue(titan_ge_eth); + } + else + titan_ge_eth->tx_threshold++; + + } + return received_packets; +} + + +/* + * Enable the Rx side interrupts + */ +static void titan_ge_enable_int(unsigned int port_num, + titan_ge_port_info *titan_ge_eth, + struct net_device *netdev) +{ + unsigned long reg_data = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE); + + if (port_num == 0) + reg_data |= 0x3; + if (port_num == 1) + reg_data |= 0x300; + if (port_num == 2) + reg_data |= 0x30000; + + /* Re-enable interrupts */ + TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data); +} + +/* + * Main function to handle the polling for Rx side NAPI. + * Receive interrupts have been disabled at this point. + * The poll schedules the transmit followed by receive. + */ +static int titan_ge_poll(struct net_device *netdev, int *budget) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + int port_num = titan_ge_eth->port_num; + int work_done = 0; + unsigned long flags, status; + + titan_ge_eth->rx_work_limit = *budget; + if (titan_ge_eth->rx_work_limit > netdev->quota) + titan_ge_eth->rx_work_limit = netdev->quota; + + do { + /* Do the transmit cleaning work here */ + titan_ge_free_tx_queue(titan_ge_eth); + + /* Ack the Rx interrupts */ + if (port_num == 0) + TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x3); + if (port_num == 1) + TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x300); + if (port_num == 2) + TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x30000); + + work_done += titan_ge_receive_queue(netdev, 0); + + /* Out of quota and there is work to be done */ + if (titan_ge_eth->rx_work_limit < 0) + goto not_done; + + /* Receive alloc_skb could lead to OOM */ + if (oom_flag == 1) { + oom_flag = 0; + goto oom; + } + + status = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A); + } while (status & 0x30300); + + /* If we are here, then no more interrupts to process */ + goto done; + +not_done: + *budget -= work_done; + netdev->quota -= work_done; + return 1; + +oom: + printk(KERN_ERR "OOM \n"); + netif_rx_complete(netdev); + return 0; + +done: + /* + * No more packets on the poll list. Turn the interrupts + * back on and we should be able to catch the new + * packets in the interrupt handler + */ + if (!work_done) + work_done = 1; + + *budget -= work_done; + netdev->quota -= work_done; + + spin_lock_irqsave(&titan_ge_eth->lock, flags); + + /* Remove us from the poll list */ + netif_rx_complete(netdev); + + /* Re-enable interrupts */ + titan_ge_enable_int(port_num, titan_ge_eth, netdev); + + spin_unlock_irqrestore(&titan_ge_eth->lock, flags); + + return 0; +} + +/* + * Close the network device + */ +int titan_ge_stop(struct net_device *netdev) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + + spin_lock_irq(&(titan_ge_eth->lock)); + titan_ge_eth_stop(netdev); + free_irq(netdev->irq, netdev); + spin_unlock_irq(&titan_ge_eth->lock); + + return TITAN_OK; +} + +/* + * Free the Tx ring + */ +static void titan_ge_free_tx_rings(struct net_device *netdev) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + unsigned int port_num = titan_ge_eth->port_num; + unsigned int curr; + unsigned long reg_data; + + /* Stop the Tx DMA */ + reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + + (port_num << 8)); + reg_data |= 0xc0000000; + TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + + (port_num << 8)), reg_data); + + /* Disable the TMAC */ + reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + + (port_num << 12)); + reg_data &= ~(0x00000001); + TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + + (port_num << 12)), reg_data); + + for (curr = 0; + (titan_ge_eth->tx_ring_skbs) && (curr < TITAN_GE_TX_QUEUE); + curr++) { + if (titan_ge_eth->tx_skb[curr]) { + dev_kfree_skb(titan_ge_eth->tx_skb[curr]); + titan_ge_eth->tx_ring_skbs--; + } + } + + if (titan_ge_eth->tx_ring_skbs != 0) + printk + ("%s: Error on Tx descriptor free - could not free %d" + " descriptors\n", netdev->name, + titan_ge_eth->tx_ring_skbs); + +#ifndef TITAN_RX_RING_IN_SRAM + dma_free_coherent(&titan_ge_device[port_num]->dev, + titan_ge_eth->tx_desc_area_size, + (void *) titan_ge_eth->tx_desc_area, + titan_ge_eth->tx_dma); +#endif +} + +/* + * Free the Rx ring + */ +static void titan_ge_free_rx_rings(struct net_device *netdev) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + unsigned int port_num = titan_ge_eth->port_num; + unsigned int curr; + unsigned long reg_data; + + /* Stop the Rx DMA */ + reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + + (port_num << 8)); + reg_data |= 0x000c0000; + TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + + (port_num << 8)), reg_data); + + /* Disable the RMAC */ + reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + + (port_num << 12)); + reg_data &= ~(0x00000001); + TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + + (port_num << 12)), reg_data); + + for (curr = 0; + titan_ge_eth->rx_ring_skbs && (curr < TITAN_GE_RX_QUEUE); + curr++) { + if (titan_ge_eth->rx_skb[curr]) { + dev_kfree_skb(titan_ge_eth->rx_skb[curr]); + titan_ge_eth->rx_ring_skbs--; + } + } + + if (titan_ge_eth->rx_ring_skbs != 0) + printk(KERN_ERR + "%s: Error in freeing Rx Ring. %d skb's still" + " stuck in RX Ring - ignoring them\n", netdev->name, + titan_ge_eth->rx_ring_skbs); + +#ifndef TITAN_RX_RING_IN_SRAM + dma_free_coherent(&titan_ge_device[port_num]->dev, + titan_ge_eth->rx_desc_area_size, + (void *) titan_ge_eth->rx_desc_area, + titan_ge_eth->rx_dma); +#endif +} + +/* + * Actually does the stop of the Ethernet device + */ +static void titan_ge_eth_stop(struct net_device *netdev) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + + netif_stop_queue(netdev); + + titan_ge_port_reset(titan_ge_eth->port_num); + + titan_ge_free_tx_rings(netdev); + titan_ge_free_rx_rings(netdev); + + /* Disable the Tx and Rx Interrupts for all channels */ + TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, 0x0); +} + +/* + * Update the MAC address. Note that we have to write the + * address in three station registers, 16 bits each. And this + * has to be done for TMAC and RMAC + */ +static void titan_ge_update_mac_address(struct net_device *netdev) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + unsigned int port_num = titan_ge_eth->port_num; + u8 p_addr[6]; + + memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6); + memcpy(p_addr, netdev->dev_addr, 6); + + /* Update the Address Filtering Match tables */ + titan_ge_update_afx(titan_ge_eth); + + printk("Station MAC : %d %d %d %d %d %d \n", + p_addr[5], p_addr[4], p_addr[3], + p_addr[2], p_addr[1], p_addr[0]); + + /* Set the MAC address here for TMAC and RMAC */ + TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port_num << 12)), + ((p_addr[5] << 8) | p_addr[4])); + TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port_num << 12)), + ((p_addr[3] << 8) | p_addr[2])); + TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port_num << 12)), + ((p_addr[1] << 8) | p_addr[0])); + + TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port_num << 12)), + ((p_addr[5] << 8) | p_addr[4])); + TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port_num << 12)), + ((p_addr[3] << 8) | p_addr[2])); + TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port_num << 12)), + ((p_addr[1] << 8) | p_addr[0])); +} + +/* + * Set the MAC address of the Ethernet device + */ +static int titan_ge_set_mac_address(struct net_device *dev, void *addr) +{ + titan_ge_port_info *tp = netdev_priv(dev); + struct sockaddr *sa = addr; + + memcpy(dev->dev_addr, sa->sa_data, dev->addr_len); + + spin_lock_irq(&tp->lock); + titan_ge_update_mac_address(dev); + spin_unlock_irq(&tp->lock); + + return 0; +} + +/* + * Get the Ethernet device stats + */ +static struct net_device_stats *titan_ge_get_stats(struct net_device *netdev) +{ + titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); + + return &titan_ge_eth->stats; +} + +/* + * Initialize the Rx descriptor ring for the Titan Ge + */ +static int titan_ge_init_rx_desc_ring(titan_ge_port_info * titan_eth_port, + int rx_desc_num, + int rx_buff_size, + unsigned long rx_desc_base_addr, + unsigned long rx_buff_base_addr, + unsigned long rx_dma) +{ + volatile titan_ge_rx_desc *rx_desc; + unsigned long buffer_addr; + int index; + unsigned long titan_ge_rx_desc_bus = rx_dma; + + buffer_addr = rx_buff_base_addr; + rx_desc = (titan_ge_rx_desc *) rx_desc_base_addr; + + /* Check alignment */ + if (rx_buff_base_addr & 0xF) + return 0; + + /* Check Rx buffer size */ + if ((rx_buff_size < 8) || (rx_buff_size > TITAN_GE_MAX_RX_BUFFER)) + return 0; + + /* 64-bit alignment + if ((rx_buff_base_addr + rx_buff_size) & 0x7) + return 0; */ + + /* Initialize the Rx desc ring */ + for (index = 0; index < rx_desc_num; index++) { + titan_ge_rx_desc_bus += sizeof(titan_ge_rx_desc); + rx_desc[index].cmd_sts = 0; + rx_desc[index].buffer_addr = buffer_addr; + titan_eth_port->rx_skb[index] = NULL; + buffer_addr += rx_buff_size; + } + + titan_eth_port->rx_curr_desc_q = 0; + titan_eth_port->rx_used_desc_q = 0; + + titan_eth_port->rx_desc_area = (titan_ge_rx_desc *) rx_desc_base_addr; + titan_eth_port->rx_desc_area_size = + rx_desc_num * sizeof(titan_ge_rx_desc); + + titan_eth_port->rx_dma = rx_dma; + + return TITAN_OK; +} + +/* + * Initialize the Tx descriptor ring. Descriptors in the SRAM + */ +static int titan_ge_init_tx_desc_ring(titan_ge_port_info * titan_ge_port, + int tx_desc_num, + unsigned long tx_desc_base_addr, + unsigned long tx_dma) +{ + titan_ge_tx_desc *tx_desc; + int index; + unsigned long titan_ge_tx_desc_bus = tx_dma; + + if (tx_desc_base_addr & 0xF) + return 0; + + tx_desc = (titan_ge_tx_desc *) tx_desc_base_addr; + + for (index = 0; index < tx_desc_num; index++) { + titan_ge_port->tx_dma_array[index] = + (dma_addr_t) titan_ge_tx_desc_bus; + titan_ge_tx_desc_bus += sizeof(titan_ge_tx_desc); + tx_desc[index].cmd_sts = 0x0000; + tx_desc[index].buffer_len = 0; + tx_desc[index].buffer_addr = 0x00000000; + titan_ge_port->tx_skb[index] = NULL; + } + + titan_ge_port->tx_curr_desc_q = 0; + titan_ge_port->tx_used_desc_q = 0; + + titan_ge_port->tx_desc_area = (titan_ge_tx_desc *) tx_desc_base_addr; + titan_ge_port->tx_desc_area_size = + tx_desc_num * sizeof(titan_ge_tx_desc); + + titan_ge_port->tx_dma = tx_dma; + return TITAN_OK; +} + +/* + * Initialize the device as an Ethernet device + */ +static int __init titan_ge_probe(struct device *device) +{ + titan_ge_port_info *titan_ge_eth; + struct net_device *netdev; + int port = to_platform_device(device)->id; + int err; + + netdev = alloc_etherdev(sizeof(titan_ge_port_info)); + if (!netdev) { + err = -ENODEV; + goto out; + } + + netdev->open = titan_ge_open; + netdev->stop = titan_ge_stop; + netdev->hard_start_xmit = titan_ge_start_xmit; + netdev->get_stats = titan_ge_get_stats; + netdev->set_multicast_list = titan_ge_set_multi; + netdev->set_mac_address = titan_ge_set_mac_address; + + /* Tx timeout */ + netdev->tx_timeout = titan_ge_tx_timeout; + netdev->watchdog_timeo = 2 * HZ; + + /* Set these to very high values */ + netdev->poll = titan_ge_poll; + netdev->weight = 64; + + netdev->tx_queue_len = TITAN_GE_TX_QUEUE; + netif_carrier_off(netdev); + netdev->base_addr = 0; + + netdev->change_mtu = titan_ge_change_mtu; + + titan_ge_eth = netdev_priv(netdev); + /* Allocation of memory for the driver structures */ + + titan_ge_eth->port_num = port; + + /* Configure the Tx timeout handler */ + INIT_WORK(&titan_ge_eth->tx_timeout_task, + (void (*)(void *)) titan_ge_tx_timeout_task, netdev); + + spin_lock_init(&titan_ge_eth->lock); + + /* set MAC addresses */ + memcpy(netdev->dev_addr, titan_ge_mac_addr_base, 6); + netdev->dev_addr[5] += port; + + err = register_netdev(netdev); + + if (err) + goto out_free_netdev; + + printk(KERN_NOTICE + "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", + netdev->name, port, netdev->dev_addr[0], + netdev->dev_addr[1], netdev->dev_addr[2], + netdev->dev_addr[3], netdev->dev_addr[4], + netdev->dev_addr[5]); + + printk(KERN_NOTICE "Rx NAPI supported, Tx Coalescing ON \n"); + + return 0; + +out_free_netdev: + kfree(netdev); + +out: + return err; +} + +static void __devexit titan_device_remove(struct device *device) +{ +} + +/* + * Reset the Ethernet port + */ +static void titan_ge_port_reset(unsigned int port_num) +{ + unsigned int reg_data; + + /* Stop the Tx port activity */ + reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + + (port_num << 12)); + reg_data &= ~(0x0001); + TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + + (port_num << 12)), reg_data); + + /* Stop the Rx port activity */ + reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + + (port_num << 12)); + reg_data &= ~(0x0001); + TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + + (port_num << 12)), reg_data); + + return; +} + +/* + * Return the Tx desc after use by the XDMA + */ +static int titan_ge_return_tx_desc(titan_ge_port_info * titan_ge_eth, int port) +{ + int tx_desc_used; + struct sk_buff *skb; + + tx_desc_used = titan_ge_eth->tx_used_desc_q; + + /* return right away */ + if (tx_desc_used == titan_ge_eth->tx_curr_desc_q) + return TITAN_ERROR; + + /* Now the critical stuff */ + skb = titan_ge_eth->tx_skb[tx_desc_used]; + + dev_kfree_skb_any(skb); + + titan_ge_eth->tx_skb[tx_desc_used] = NULL; + titan_ge_eth->tx_used_desc_q = + (tx_desc_used + 1) % TITAN_GE_TX_QUEUE; + + return 0; +} + +/* + * Coalescing for the Tx path + */ +static unsigned long titan_ge_tx_coal(unsigned long delay, int port) +{ + unsigned long rx_delay; + + rx_delay = TITAN_GE_READ(TITAN_GE_INT_COALESCING); + delay = (delay << 16) | rx_delay; + + TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay); + TITAN_GE_WRITE(0x5038, delay); + + return delay; +} + +static struct device_driver titan_soc_driver = { + .name = titan_string, + .bus = &platform_bus_type, + .probe = titan_ge_probe, + .remove = __devexit_p(titan_device_remove), +}; + +static void titan_platform_release (struct device *device) +{ + struct platform_device *pldev; + + /* free device */ + pldev = to_platform_device (device); + kfree (pldev); +} + +/* + * Register the Titan GE with the kernel + */ +static int __init titan_ge_init_module(void) +{ + struct platform_device *pldev; + unsigned int version, device; + int i; + + printk(KERN_NOTICE + "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n"); + + titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE); + if (!titan_ge_base) { + printk("Mapping Titan GE failed\n"); + goto out; + } + + device = TITAN_GE_READ(TITAN_GE_DEVICE_ID); + version = (device & 0x000f0000) >> 16; + device &= 0x0000ffff; + + printk(KERN_NOTICE "Device Id : %x, Version : %x \n", device, version); + +#ifdef TITAN_RX_RING_IN_SRAM + titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE, + TITAN_SRAM_SIZE); + if (!titan_ge_sram) { + printk("Mapping Titan SRAM failed\n"); + goto out_unmap_ge; + } +#endif + + if (driver_register(&titan_soc_driver)) { + printk(KERN_ERR "Driver registration failed\n"); + goto out_unmap_sram; + } + + for (i = 0; i < 3; i++) { + titan_ge_device[i] = NULL; + + if (!(pldev = kmalloc (sizeof (*pldev), GFP_KERNEL))) + continue; + + memset (pldev, 0, sizeof (*pldev)); + pldev->name = titan_string; + pldev->id = i; + pldev->dev.release = titan_platform_release; + titan_ge_device[i] = pldev; + + if (platform_device_register (pldev)) { + kfree (pldev); + titan_ge_device[i] = NULL; + continue; + } + + if (!pldev->dev.driver) { + /* + * The driver was not bound to this device, there was + * no hardware at this address. Unregister it, as the + * release fuction will take care of freeing the + * allocated structure + */ + titan_ge_device[i] = NULL; + platform_device_unregister (pldev); + } + } + + return 0; + +out_unmap_sram: + iounmap((void *)titan_ge_sram); + +out_unmap_ge: + iounmap((void *)titan_ge_base); + +out: + return -ENOMEM; +} + +/* + * Unregister the Titan GE from the kernel + */ +static void __exit titan_ge_cleanup_module(void) +{ + int i; + + driver_unregister(&titan_soc_driver); + + for (i = 0; i < 3; i++) { + if (titan_ge_device[i]) { + platform_device_unregister (titan_ge_device[i]); + titan_ge_device[i] = NULL; + } + } + + iounmap((void *)titan_ge_sram); + iounmap((void *)titan_ge_base); +} + +MODULE_AUTHOR("Manish Lachwani "); +MODULE_DESCRIPTION("Titan GE Ethernet driver"); +MODULE_LICENSE("GPL"); + +module_init(titan_ge_init_module); +module_exit(titan_ge_cleanup_module); diff -Naur linux-2.6.12.6.orig/drivers/net/titan_ge.h linux-2.6.12.6/drivers/net/titan_ge.h --- linux-2.6.12.6.orig/drivers/net/titan_ge.h 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/net/titan_ge.h 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,419 @@ +#ifndef _TITAN_GE_H_ +#define _TITAN_GE_H_ + +#include +#include +#include +#include +#include +#include + +/* + * These functions should be later moved to a more generic location since there + * will be others accessing it also + */ + +/* + * This is the way it works: LKB5 Base is at 0x0128. TITAN_BASE is defined in + * include/asm/titan_dep.h. TITAN_GE_BASE is the value in the TITAN_GE_LKB5 + * register. + */ + +#define TITAN_GE_BASE 0xfe000000UL +#define TITAN_GE_SIZE 0x10000UL + +extern unsigned long titan_ge_base; + +#define TITAN_GE_WRITE(offset, data) \ + *(volatile u32 *)(titan_ge_base + (offset)) = (data) + +#define TITAN_GE_READ(offset) *(volatile u32 *)(titan_ge_base + (offset)) + +#ifndef msec_delay +#define msec_delay(x) do { if(in_interrupt()) { \ + /* Don't mdelay in interrupt context! */ \ + BUG(); \ + } else { \ + set_current_state(TASK_UNINTERRUPTIBLE); \ + schedule_timeout((x * HZ)/1000); \ + } } while(0) +#endif + +#define TITAN_GE_PORT_0 + +#define TITAN_SRAM_BASE ((OCD_READ(RM9000x2_OCD_LKB13) & ~1) << 4) +#define TITAN_SRAM_SIZE 0x2000UL + +extern unsigned long titan_ge_sram; + +/* + * We may need these constants + */ +#define TITAN_BIT0 0x00000001 +#define TITAN_BIT1 0x00000002 +#define TITAN_BIT2 0x00000004 +#define TITAN_BIT3 0x00000008 +#define TITAN_BIT4 0x00000010 +#define TITAN_BIT5 0x00000020 +#define TITAN_BIT6 0x00000040 +#define TITAN_BIT7 0x00000080 +#define TITAN_BIT8 0x00000100 +#define TITAN_BIT9 0x00000200 +#define TITAN_BIT10 0x00000400 +#define TITAN_BIT11 0x00000800 +#define TITAN_BIT12 0x00001000 +#define TITAN_BIT13 0x00002000 +#define TITAN_BIT14 0x00004000 +#define TITAN_BIT15 0x00008000 +#define TITAN_BIT16 0x00010000 +#define TITAN_BIT17 0x00020000 +#define TITAN_BIT18 0x00040000 +#define TITAN_BIT19 0x00080000 +#define TITAN_BIT20 0x00100000 +#define TITAN_BIT21 0x00200000 +#define TITAN_BIT22 0x00400000 +#define TITAN_BIT23 0x00800000 +#define TITAN_BIT24 0x01000000 +#define TITAN_BIT25 0x02000000 +#define TITAN_BIT26 0x04000000 +#define TITAN_BIT27 0x08000000 +#define TITAN_BIT28 0x10000000 +#define TITAN_BIT29 0x20000000 +#define TITAN_BIT30 0x40000000 +#define TITAN_BIT31 0x80000000 + +/* Flow Control */ +#define TITAN_GE_FC_NONE 0x0 +#define TITAN_GE_FC_FULL 0x1 +#define TITAN_GE_FC_TX_PAUSE 0x2 +#define TITAN_GE_FC_RX_PAUSE 0x3 + +/* Duplex Settings */ +#define TITAN_GE_FULL_DUPLEX 0x1 +#define TITAN_GE_HALF_DUPLEX 0x2 + +/* Speed settings */ +#define TITAN_GE_SPEED_1000 0x1 +#define TITAN_GE_SPEED_100 0x2 +#define TITAN_GE_SPEED_10 0x3 + +/* Debugging info only */ +#undef TITAN_DEBUG + +/* Keep the rings in the Titan's SSRAM */ +#define TITAN_RX_RING_IN_SRAM + +#ifdef CONFIG_MIPS64 +#define TITAN_GE_IE_MASK 0xfffffffffb001b64 +#define TITAN_GE_IE_STATUS 0xfffffffffb001b60 +#else +#define TITAN_GE_IE_MASK 0xfb001b64 +#define TITAN_GE_IE_STATUS 0xfb001b60 +#endif + +/* Support for Jumbo Frames */ +#undef TITAN_GE_JUMBO_FRAMES + +/* Rx buffer size */ +#ifdef TITAN_GE_JUMBO_FRAMES +#define TITAN_GE_JUMBO_BUFSIZE 9080 +#else +#define TITAN_GE_STD_BUFSIZE 1580 +#endif + +/* + * Tx and Rx Interrupt Coalescing parameter. These values are + * for 1 Ghz processor. Rx coalescing can be taken care of + * by NAPI. NAPI is adaptive and hence useful. Tx coalescing + * is not adaptive. Hence, these values need to be adjusted + * based on load, CPU speed etc. + */ +#define TITAN_GE_RX_COAL 150 +#define TITAN_GE_TX_COAL 300 + +#if defined(__BIG_ENDIAN) + +/* Define the Rx descriptor */ +typedef struct eth_rx_desc { + u32 reserved; /* Unused */ + u32 buffer_addr; /* CPU buffer address */ + u32 cmd_sts; /* Command and Status */ + u32 buffer; /* XDMA buffer address */ +} titan_ge_rx_desc; + +/* Define the Tx descriptor */ +typedef struct eth_tx_desc { + u16 cmd_sts; /* Command, Status and Buffer count */ + u16 buffer_len; /* Length of the buffer */ + u32 buffer_addr; /* Physical address of the buffer */ +} titan_ge_tx_desc; + +#elif defined(__LITTLE_ENDIAN) + +/* Define the Rx descriptor */ +typedef struct eth_rx_desc { + u32 buffer_addr; /* CPU buffer address */ + u32 reserved; /* Unused */ + u32 buffer; /* XDMA buffer address */ + u32 cmd_sts; /* Command and Status */ +} titan_ge_rx_desc; + +/* Define the Tx descriptor */ +typedef struct eth_tx_desc { + u32 buffer_addr; /* Physical address of the buffer */ + u16 buffer_len; /* Length of the buffer */ + u16 cmd_sts; /* Command, Status and Buffer count */ +} titan_ge_tx_desc; +#endif + +/* Default Tx Queue Size */ +#define TITAN_GE_TX_QUEUE 128 +#define TITAN_TX_RING_BYTES (TITAN_GE_TX_QUEUE * sizeof(struct eth_tx_desc)) + +/* Default Rx Queue Size */ +#define TITAN_GE_RX_QUEUE 64 +#define TITAN_RX_RING_BYTES (TITAN_GE_RX_QUEUE * sizeof(struct eth_rx_desc)) + +/* Packet Structure */ +typedef struct _pkt_info { + unsigned int len; + unsigned int cmd_sts; + unsigned int buffer; + struct sk_buff *skb; + unsigned int checksum; +} titan_ge_packet; + + +#define PHYS_CNT 3 + +/* Titan Port specific data structure */ +typedef struct _eth_port_ctrl { + unsigned int port_num; + u8 port_mac_addr[6]; + + /* Rx descriptor pointers */ + int rx_curr_desc_q, rx_used_desc_q; + + /* Tx descriptor pointers */ + int tx_curr_desc_q, tx_used_desc_q; + + /* Rx descriptor area */ + volatile titan_ge_rx_desc *rx_desc_area; + unsigned int rx_desc_area_size; + struct sk_buff* rx_skb[TITAN_GE_RX_QUEUE]; + + /* Tx Descriptor area */ + volatile titan_ge_tx_desc *tx_desc_area; + unsigned int tx_desc_area_size; + struct sk_buff* tx_skb[TITAN_GE_TX_QUEUE]; + + /* Timeout task */ + struct work_struct tx_timeout_task; + + /* DMA structures and handles */ + dma_addr_t tx_dma; + dma_addr_t rx_dma; + dma_addr_t tx_dma_array[TITAN_GE_TX_QUEUE]; + + /* Device lock */ + spinlock_t lock; + + unsigned int tx_ring_skbs; + unsigned int rx_ring_size; + unsigned int tx_ring_size; + unsigned int rx_ring_skbs; + + struct net_device_stats stats; + + /* Tx and Rx coalescing */ + unsigned long rx_int_coal; + unsigned long tx_int_coal; + + /* Threshold for replenishing the Rx and Tx rings */ + unsigned int tx_threshold; + unsigned int rx_threshold; + + /* NAPI work limit */ + unsigned int rx_work_limit; +} titan_ge_port_info; + +/* Titan specific constants */ +#define TITAN_ETH_PORT_IRQ 3 + +/* Max Rx buffer */ +#define TITAN_GE_MAX_RX_BUFFER 65536 + +/* Tx and Rx Error */ +#define TITAN_GE_ERROR + +/* Rx Descriptor Command and Status */ + +#define TITAN_GE_RX_CRC_ERROR TITAN_BIT27 /* crc error */ +#define TITAN_GE_RX_OVERFLOW_ERROR TITAN_BIT15 /* overflow */ +#define TITAN_GE_RX_BUFFER_OWNED TITAN_BIT21 /* buffer ownership */ +#define TITAN_GE_RX_STP TITAN_BIT31 /* start of packet */ +#define TITAN_GE_RX_BAM TITAN_BIT30 /* broadcast address match */ +#define TITAN_GE_RX_PAM TITAN_BIT28 /* physical address match */ +#define TITAN_GE_RX_LAFM TITAN_BIT29 /* logical address filter match */ +#define TITAN_GE_RX_VLAN TITAN_BIT26 /* virtual lans */ +#define TITAN_GE_RX_PERR TITAN_BIT19 /* packet error */ +#define TITAN_GE_RX_TRUNC TITAN_BIT20 /* packet size greater than 32 buffers */ + +/* Tx Descriptor Command */ +#define TITAN_GE_TX_BUFFER_OWNED TITAN_BIT5 /* buffer ownership */ +#define TITAN_GE_TX_ENABLE_INTERRUPT TITAN_BIT15 /* Interrupt Enable */ + +/* Return Status */ +#define TITAN_OK 0x1 /* Good Status */ +#define TITAN_ERROR 0x2 /* Error Status */ + +/* MIB specific register offset */ +#define TITAN_GE_MSTATX_STATS_BASE_LOW 0x0800 /* MSTATX COUNTL[15:0] */ +#define TITAN_GE_MSTATX_STATS_BASE_MID 0x0804 /* MSTATX COUNTM[15:0] */ +#define TITAN_GE_MSTATX_STATS_BASE_HI 0x0808 /* MSTATX COUNTH[7:0] */ +#define TITAN_GE_MSTATX_CONTROL 0x0828 /* MSTATX Control */ +#define TITAN_GE_MSTATX_VARIABLE_SELECT 0x082C /* MSTATX Variable Select */ + +/* MIB counter offsets, add to the TITAN_GE_MSTATX_STATS_BASE_XXX */ +#define TITAN_GE_MSTATX_RXFRAMESOK 0x0040 +#define TITAN_GE_MSTATX_RXOCTETSOK 0x0050 +#define TITAN_GE_MSTATX_RXFRAMES 0x0060 +#define TITAN_GE_MSTATX_RXOCTETS 0x0070 +#define TITAN_GE_MSTATX_RXUNICASTFRAMESOK 0x0080 +#define TITAN_GE_MSTATX_RXBROADCASTFRAMESOK 0x0090 +#define TITAN_GE_MSTATX_RXMULTICASTFRAMESOK 0x00A0 +#define TITAN_GE_MSTATX_RXTAGGEDFRAMESOK 0x00B0 +#define TITAN_GE_MSTATX_RXMACPAUSECONTROLFRAMESOK 0x00C0 +#define TITAN_GE_MSTATX_RXMACCONTROLFRAMESOK 0x00D0 +#define TITAN_GE_MSTATX_RXFCSERROR 0x00E0 +#define TITAN_GE_MSTATX_RXALIGNMENTERROR 0x00F0 +#define TITAN_GE_MSTATX_RXSYMBOLERROR 0x0100 +#define TITAN_GE_MSTATX_RXLAYER1ERROR 0x0110 +#define TITAN_GE_MSTATX_RXINRANGELENGTHERROR 0x0120 +#define TITAN_GE_MSTATX_RXLONGLENGTHERROR 0x0130 +#define TITAN_GE_MSTATX_RXLONGLENGTHCRCERROR 0x0140 +#define TITAN_GE_MSTATX_RXSHORTLENGTHERROR 0x0150 +#define TITAN_GE_MSTATX_RXSHORTLLENGTHCRCERROR 0x0160 +#define TITAN_GE_MSTATX_RXFRAMES64OCTETS 0x0170 +#define TITAN_GE_MSTATX_RXFRAMES65TO127OCTETS 0x0180 +#define TITAN_GE_MSTATX_RXFRAMES128TO255OCTETS 0x0190 +#define TITAN_GE_MSTATX_RXFRAMES256TO511OCTETS 0x01A0 +#define TITAN_GE_MSTATX_RXFRAMES512TO1023OCTETS 0x01B0 +#define TITAN_GE_MSTATX_RXFRAMES1024TO1518OCTETS 0x01C0 +#define TITAN_GE_MSTATX_RXFRAMES1519TOMAXSIZE 0x01D0 +#define TITAN_GE_MSTATX_RXSTATIONADDRESSFILTERED 0x01E0 +#define TITAN_GE_MSTATX_RXVARIABLE 0x01F0 +#define TITAN_GE_MSTATX_GENERICADDRESSFILTERED 0x0200 +#define TITAN_GE_MSTATX_UNICASTFILTERED 0x0210 +#define TITAN_GE_MSTATX_MULTICASTFILTERED 0x0220 +#define TITAN_GE_MSTATX_BROADCASTFILTERED 0x0230 +#define TITAN_GE_MSTATX_HASHFILTERED 0x0240 +#define TITAN_GE_MSTATX_TXFRAMESOK 0x0250 +#define TITAN_GE_MSTATX_TXOCTETSOK 0x0260 +#define TITAN_GE_MSTATX_TXOCTETS 0x0270 +#define TITAN_GE_MSTATX_TXTAGGEDFRAMESOK 0x0280 +#define TITAN_GE_MSTATX_TXMACPAUSECONTROLFRAMESOK 0x0290 +#define TITAN_GE_MSTATX_TXFCSERROR 0x02A0 +#define TITAN_GE_MSTATX_TXSHORTLENGTHERROR 0x02B0 +#define TITAN_GE_MSTATX_TXLONGLENGTHERROR 0x02C0 +#define TITAN_GE_MSTATX_TXSYSTEMERROR 0x02D0 +#define TITAN_GE_MSTATX_TXMACERROR 0x02E0 +#define TITAN_GE_MSTATX_TXCARRIERSENSEERROR 0x02F0 +#define TITAN_GE_MSTATX_TXSQETESTERROR 0x0300 +#define TITAN_GE_MSTATX_TXUNICASTFRAMESOK 0x0310 +#define TITAN_GE_MSTATX_TXBROADCASTFRAMESOK 0x0320 +#define TITAN_GE_MSTATX_TXMULTICASTFRAMESOK 0x0330 +#define TITAN_GE_MSTATX_TXUNICASTFRAMESATTEMPTED 0x0340 +#define TITAN_GE_MSTATX_TXBROADCASTFRAMESATTEMPTED 0x0350 +#define TITAN_GE_MSTATX_TXMULTICASTFRAMESATTEMPTED 0x0360 +#define TITAN_GE_MSTATX_TXFRAMES64OCTETS 0x0370 +#define TITAN_GE_MSTATX_TXFRAMES65TO127OCTETS 0x0380 +#define TITAN_GE_MSTATX_TXFRAMES128TO255OCTETS 0x0390 +#define TITAN_GE_MSTATX_TXFRAMES256TO511OCTETS 0x03A0 +#define TITAN_GE_MSTATX_TXFRAMES512TO1023OCTETS 0x03B0 +#define TITAN_GE_MSTATX_TXFRAMES1024TO1518OCTETS 0x03C0 +#define TITAN_GE_MSTATX_TXFRAMES1519TOMAXSIZE 0x03D0 +#define TITAN_GE_MSTATX_TXVARIABLE 0x03E0 +#define TITAN_GE_MSTATX_RXSYSTEMERROR 0x03F0 +#define TITAN_GE_MSTATX_SINGLECOLLISION 0x0400 +#define TITAN_GE_MSTATX_MULTIPLECOLLISION 0x0410 +#define TITAN_GE_MSTATX_DEFERREDXMISSIONS 0x0420 +#define TITAN_GE_MSTATX_LATECOLLISIONS 0x0430 +#define TITAN_GE_MSTATX_ABORTEDDUETOXSCOLLS 0x0440 + +/* Interrupt specific defines */ +#define TITAN_GE_DEVICE_ID 0x0000 /* Device ID */ +#define TITAN_GE_RESET 0x0004 /* Reset reg */ +#define TITAN_GE_TSB_CTRL_0 0x000C /* TSB Control reg 0 */ +#define TITAN_GE_TSB_CTRL_1 0x0010 /* TSB Control reg 1 */ +#define TITAN_GE_INTR_GRP0_STATUS 0x0040 /* General Interrupt Group 0 Status */ +#define TITAN_GE_INTR_XDMA_CORE_A 0x0048 /* XDMA Channel Interrupt Status, Core A*/ +#define TITAN_GE_INTR_XDMA_CORE_B 0x004C /* XDMA Channel Interrupt Status, Core B*/ +#define TITAN_GE_INTR_XDMA_IE 0x0058 /* XDMA Channel Interrupt Enable */ +#define TITAN_GE_SDQPF_ECC_INTR 0x480C /* SDQPF ECC Interrupt Status */ +#define TITAN_GE_SDQPF_RXFIFO_CTL 0x4828 /* SDQPF RxFifo Control and Interrupt Enb*/ +#define TITAN_GE_SDQPF_RXFIFO_INTR 0x482C /* SDQPF RxFifo Interrupt Status */ +#define TITAN_GE_SDQPF_TXFIFO_CTL 0x4928 /* SDQPF TxFifo Control and Interrupt Enb*/ +#define TITAN_GE_SDQPF_TXFIFO_INTR 0x492C /* SDQPF TxFifo Interrupt Status */ +#define TITAN_GE_SDQPF_RXFIFO_0 0x4840 /* SDQPF RxFIFO Enable */ +#define TITAN_GE_SDQPF_TXFIFO_0 0x4940 /* SDQPF TxFIFO Enable */ +#define TITAN_GE_XDMA_CONFIG 0x5000 /* XDMA Global Configuration */ +#define TITAN_GE_XDMA_INTR_SUMMARY 0x5010 /* XDMA Interrupt Summary */ +#define TITAN_GE_XDMA_BUFADDRPRE 0x5018 /* XDMA Buffer Address Prefix */ +#define TITAN_GE_XDMA_DESCADDRPRE 0x501C /* XDMA Descriptor Address Prefix */ +#define TITAN_GE_XDMA_PORTWEIGHT 0x502C /* XDMA Port Weight Configuration */ + +/* Rx MAC defines */ +#define TITAN_GE_RMAC_CONFIG_1 0x1200 /* RMAC Configuration 1 */ +#define TITAN_GE_RMAC_CONFIG_2 0x1204 /* RMAC Configuration 2 */ +#define TITAN_GE_RMAC_MAX_FRAME_LEN 0x1208 /* RMAC Max Frame Length */ +#define TITAN_GE_RMAC_STATION_HI 0x120C /* Rx Station Address High */ +#define TITAN_GE_RMAC_STATION_MID 0x1210 /* Rx Station Address Middle */ +#define TITAN_GE_RMAC_STATION_LOW 0x1214 /* Rx Station Address Low */ +#define TITAN_GE_RMAC_LINK_CONFIG 0x1218 /* RMAC Link Configuration */ + +/* Tx MAC defines */ +#define TITAN_GE_TMAC_CONFIG_1 0x1240 /* TMAC Configuration 1 */ +#define TITAN_GE_TMAC_CONFIG_2 0x1244 /* TMAC Configuration 2 */ +#define TITAN_GE_TMAC_IPG 0x1248 /* TMAC Inter-Packet Gap */ +#define TITAN_GE_TMAC_STATION_HI 0x124C /* Tx Station Address High */ +#define TITAN_GE_TMAC_STATION_MID 0x1250 /* Tx Station Address Middle */ +#define TITAN_GE_TMAC_STATION_LOW 0x1254 /* Tx Station Address Low */ +#define TITAN_GE_TMAC_MAX_FRAME_LEN 0x1258 /* TMAC Max Frame Length */ +#define TITAN_GE_TMAC_MIN_FRAME_LEN 0x125C /* TMAC Min Frame Length */ +#define TITAN_GE_TMAC_PAUSE_FRAME_TIME 0x1260 /* TMAC Pause Frame Time */ +#define TITAN_GE_TMAC_PAUSE_FRAME_INTERVAL 0x1264 /* TMAC Pause Frame Interval */ + +/* GMII register */ +#define TITAN_GE_GMII_INTERRUPT_STATUS 0x1348 /* GMII Interrupt Status */ +#define TITAN_GE_GMII_CONFIG_GENERAL 0x134C /* GMII Configuration General */ +#define TITAN_GE_GMII_CONFIG_MODE 0x1350 /* GMII Configuration Mode */ + +/* Tx and Rx XDMA defines */ +#define TITAN_GE_INT_COALESCING 0x5030 /* Interrupt Coalescing */ +#define TITAN_GE_CHANNEL0_CONFIG 0x5040 /* Channel 0 XDMA config */ +#define TITAN_GE_CHANNEL0_INTERRUPT 0x504c /* Channel 0 Interrupt Status */ +#define TITAN_GE_GDI_INTERRUPT_ENABLE 0x5050 /* IE for the GDI Errors */ +#define TITAN_GE_CHANNEL0_PACKET 0x5060 /* Channel 0 Packet count */ +#define TITAN_GE_CHANNEL0_BYTE 0x5064 /* Channel 0 Byte count */ +#define TITAN_GE_CHANNEL0_TX_DESC 0x5054 /* Channel 0 Tx first desc */ +#define TITAN_GE_CHANNEL0_RX_DESC 0x5058 /* Channel 0 Rx first desc */ + +/* AFX (Address Filter Exact) register offsets for Slice 0 */ +#define TITAN_GE_AFX_EXACT_MATCH_LOW 0x1100 /* AFX Exact Match Address Low*/ +#define TITAN_GE_AFX_EXACT_MATCH_MID 0x1104 /* AFX Exact Match Address Mid*/ +#define TITAN_GE_AFX_EXACT_MATCH_HIGH 0x1108 /* AFX Exact Match Address Hi */ +#define TITAN_GE_AFX_EXACT_MATCH_VID 0x110C /* AFX Exact Match VID */ +#define TITAN_GE_AFX_MULTICAST_HASH_LOW 0x1110 /* AFX Multicast HASH Low */ +#define TITAN_GE_AFX_MULTICAST_HASH_MIDLOW 0x1114 /* AFX Multicast HASH MidLow */ +#define TITAN_GE_AFX_MULTICAST_HASH_MIDHI 0x1118 /* AFX Multicast HASH MidHi */ +#define TITAN_GE_AFX_MULTICAST_HASH_HI 0x111C /* AFX Multicast HASH Hi */ +#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 0x1120 /* AFX Address Filter Ctrl 0 */ +#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 0x1124 /* AFX Address Filter Ctrl 1 */ +#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 0x1128 /* AFX Address Filter Ctrl 2 */ + +/* Traffic Groomer block */ +#define TITAN_GE_TRTG_CONFIG 0x1000 /* TRTG Config */ + +#endif /* _TITAN_GE_H_ */ + diff -Naur linux-2.6.12.6.orig/drivers/net/titan_mdio.c linux-2.6.12.6/drivers/net/titan_mdio.c --- linux-2.6.12.6.orig/drivers/net/titan_mdio.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/net/titan_mdio.c 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,217 @@ +/* + * drivers/net/titan_mdio.c - Driver for Titan ethernet ports + * + * Copyright (C) 2003 PMC-Sierra Inc. + * Author : Manish Lachwani (lachwani@pmc-sierra.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Management Data IO (MDIO) driver for the Titan GMII. Interacts with the Marvel PHY + * on the Titan. No support for the TBI as yet. + * + */ + +#include "titan_mdio.h" + +#define MDIO_DEBUG + +/* + * Local constants + */ +#define MAX_CLKA 1023 +#define MAX_PHY_DEV 31 +#define MAX_PHY_REG 31 +#define WRITEADDRS_OPCODE 0x0 +#define READ_OPCODE 0x2 +#define WRITE_OPCODE 0x1 +#define MAX_MDIO_POLL 100 + +/* + * Titan MDIO and SCMB registers + */ +#define TITAN_GE_SCMB_CONTROL 0x01c0 /* SCMB Control */ +#define TITAN_GE_SCMB_CLKA 0x01c4 /* SCMB Clock A */ +#define TITAN_GE_MDIO_COMMAND 0x01d0 /* MDIO Command */ +#define TITAN_GE_MDIO_DEVICE_PORT_ADDRESS 0x01d4 /* MDIO Device and Port addrs */ +#define TITAN_GE_MDIO_DATA 0x01d8 /* MDIO Data */ +#define TITAN_GE_MDIO_INTERRUPTS 0x01dC /* MDIO Interrupts */ + +/* + * Function to poll the MDIO + */ +static int titan_ge_mdio_poll(void) +{ + int i, val; + + for (i = 0; i < MAX_MDIO_POLL; i++) { + val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND); + + if (!(val & 0x8000)) + return TITAN_GE_MDIO_GOOD; + } + + return TITAN_GE_MDIO_ERROR; +} + + +/* + * Initialize and configure the MDIO + */ +int titan_ge_mdio_setup(titan_ge_mdio_config *titan_mdio) +{ + unsigned long val; + + /* Reset the SCMB and program into MDIO mode*/ + TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x9000); + TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x1000); + + /* CLK A */ + val = TITAN_GE_MDIO_READ(TITAN_GE_SCMB_CLKA); + val = ( (val & ~(0x03ff)) | (titan_mdio->clka & 0x03ff)); + TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CLKA, val); + + /* Preamble Suppresion */ + val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND); + val = ( (val & ~(0x0001)) | (titan_mdio->mdio_spre & 0x0001)); + TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val); + + /* MDIO mode */ + val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS); + val = ( (val & ~(0x4000)) | (titan_mdio->mdio_mode & 0x4000)); + TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val); + + return TITAN_GE_MDIO_GOOD; +} + +/* + * Set the PHY address in indirect mode + */ +int titan_ge_mdio_inaddrs(int dev_addr, int reg_addr) +{ + volatile unsigned long val; + + /* Setup the PHY device */ + val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS); + val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00)); + val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f)); + TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val); + + /* Write the new address */ + val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND); + val = ( (val & ~(0x0300)) | ( (WRITEADDRS_OPCODE << 8) & 0x0300)); + TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val); + + return TITAN_GE_MDIO_GOOD; +} + +/* + * Read the MDIO register. This is what the individual parametes mean: + * + * dev_addr : PHY ID + * reg_addr : register offset + * + * See the spec for the Titan MAC. We operate in the Direct Mode. + */ + +#define MAX_RETRIES 2 + +int titan_ge_mdio_read(int dev_addr, int reg_addr, unsigned int *pdata) +{ + volatile unsigned long val; + int retries = 0; + + /* Setup the PHY device */ + +again: + val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS); + val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00)); + val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f)); + val |= 0x4000; + TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val); + + udelay(30); + + /* Issue the read command */ + val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND); + val = ( (val & ~(0x0300)) | ( (READ_OPCODE << 8) & 0x0300)); + TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val); + + udelay(30); + + if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD) + return TITAN_GE_MDIO_ERROR; + + *pdata = (unsigned int)TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DATA); + val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS); + + udelay(30); + + if (val & 0x2) { + if (retries == MAX_RETRIES) + return TITAN_GE_MDIO_ERROR; + else { + retries++; + goto again; + } + } + + return TITAN_GE_MDIO_GOOD; +} + +/* + * Write to the MDIO register + * + * dev_addr : PHY ID + * reg_addr : register that needs to be written to + * + */ +int titan_ge_mdio_write(int dev_addr, int reg_addr, unsigned int data) +{ + volatile unsigned long val; + + if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD) + return TITAN_GE_MDIO_ERROR; + + /* Setup the PHY device */ + val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS); + val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00)); + val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f)); + val |= 0x4000; + TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val); + + udelay(30); + + /* Setup the data to write */ + TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DATA, data); + + udelay(30); + + /* Issue the write command */ + val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND); + val = ( (val & ~(0x0300)) | ( (WRITE_OPCODE << 8) & 0x0300)); + TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val); + + udelay(30); + + if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD) + return TITAN_GE_MDIO_ERROR; + + val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS); + if (val & 0x2) + return TITAN_GE_MDIO_ERROR; + + return TITAN_GE_MDIO_GOOD; +} + diff -Naur linux-2.6.12.6.orig/drivers/net/titan_mdio.h linux-2.6.12.6/drivers/net/titan_mdio.h --- linux-2.6.12.6.orig/drivers/net/titan_mdio.h 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/net/titan_mdio.h 2005-10-02 23:47:38.000000000 +0000 @@ -0,0 +1,56 @@ +/* + * MDIO used to interact with the PHY when using GMII/MII + */ +#ifndef _TITAN_MDIO_H +#define _TITAN_MDIO_H + +#include +#include +#include +#include "titan_ge.h" + + +#define TITAN_GE_MDIO_ERROR (-9000) +#define TITAN_GE_MDIO_GOOD 0 + +#define TITAN_GE_MDIO_BASE titan_ge_base + +#define TITAN_GE_MDIO_READ(offset) \ + *(volatile u32 *)(titan_ge_base + (offset)) + +#define TITAN_GE_MDIO_WRITE(offset, data) \ + *(volatile u32 *)(titan_ge_base + (offset)) = (data) + + +/* GMII specific registers */ +#define TITAN_GE_MARVEL_PHY_ID 0x00 +#define TITAN_PHY_AUTONEG_ADV 0x04 +#define TITAN_PHY_LP_ABILITY 0x05 +#define TITAN_GE_MDIO_MII_CTRL 0x09 +#define TITAN_GE_MDIO_MII_EXTENDED 0x0f +#define TITAN_GE_MDIO_PHY_CTRL 0x10 +#define TITAN_GE_MDIO_PHY_STATUS 0x11 +#define TITAN_GE_MDIO_PHY_IE 0x12 +#define TITAN_GE_MDIO_PHY_IS 0x13 +#define TITAN_GE_MDIO_PHY_LED 0x18 +#define TITAN_GE_MDIO_PHY_LED_OVER 0x19 +#define PHY_ANEG_TIME_WAIT 45 /* 45 seconds wait time */ + +/* + * MDIO Config Structure + */ +typedef struct { + unsigned int clka; + int mdio_spre; + int mdio_mode; +} titan_ge_mdio_config; + +/* + * Function Prototypes + */ +int titan_ge_mdio_setup(titan_ge_mdio_config *); +int titan_ge_mdio_inaddrs(int, int); +int titan_ge_mdio_read(int, int, unsigned int *); +int titan_ge_mdio_write(int, int, unsigned int); + +#endif /* _TITAN_MDIO_H */ diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/Kconfig linux-2.6.12.6/drivers/net/tulip/Kconfig --- linux-2.6.12.6.orig/drivers/net/tulip/Kconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/Kconfig 2005-10-02 23:47:38.000000000 +0000 @@ -135,6 +135,18 @@ . The module will be called dmfe. +config ULI526X + tristate "ULi M526x controller support" + depends on NET_TULIP && PCI + select CRC32 + ---help--- + This driver is for ULi M5261/M5263 10/100M Ethernet Controller + (). + + To compile this driver as a module, choose M here and read + . The module will + be called uli526x. + config PCMCIA_XIRCOM tristate "Xircom CardBus support (new driver)" depends on NET_TULIP && CARDBUS diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/Makefile linux-2.6.12.6/drivers/net/tulip/Makefile --- linux-2.6.12.6.orig/drivers/net/tulip/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/Makefile 2005-10-02 23:47:38.000000000 +0000 @@ -9,6 +9,7 @@ obj-$(CONFIG_DE2104X) += de2104x.o obj-$(CONFIG_TULIP) += tulip.o obj-$(CONFIG_DE4X5) += de4x5.o +obj-$(CONFIG_ULI526X) += uli526x.o # Declare multi-part drivers. diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/de2104x.c linux-2.6.12.6/drivers/net/tulip/de2104x.c --- linux-2.6.12.6.orig/drivers/net/tulip/de2104x.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/de2104x.c 2005-10-02 23:47:38.000000000 +0000 @@ -446,13 +446,13 @@ mapping = de->rx_skb[rx_tail].mapping = - pci_map_single(de->pdev, copy_skb->tail, + pci_map_single(de->pdev, copy_skb->data, buflen, PCI_DMA_FROMDEVICE); de->rx_skb[rx_tail].skb = copy_skb; } else { pci_dma_sync_single_for_cpu(de->pdev, mapping, len, PCI_DMA_FROMDEVICE); skb_reserve(copy_skb, RX_OFFSET); - memcpy(skb_put(copy_skb, len), skb->tail, len); + memcpy(skb_put(copy_skb, len), skb->data, len); pci_dma_sync_single_for_device(de->pdev, mapping, len, PCI_DMA_FROMDEVICE); @@ -1269,7 +1269,7 @@ skb->dev = de->dev; de->rx_skb[i].mapping = pci_map_single(de->pdev, - skb->tail, de->rx_buf_sz, PCI_DMA_FROMDEVICE); + skb->data, de->rx_buf_sz, PCI_DMA_FROMDEVICE); de->rx_skb[i].skb = skb; de->rx_ring[i].opts1 = cpu_to_le32(DescOwn); @@ -1934,7 +1934,7 @@ struct de_private *de; int rc; void __iomem *regs; - long pciaddr; + unsigned long pciaddr; static int board_idx = -1; board_idx++; diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/de4x5.c linux-2.6.12.6/drivers/net/tulip/de4x5.c --- linux-2.6.12.6.orig/drivers/net/tulip/de4x5.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/de4x5.c 2005-10-02 23:47:39.000000000 +0000 @@ -2144,9 +2144,9 @@ u_long iobase = 0; /* Clear upper 32 bits in Alphas */ int i, j, cfrv; struct de4x5_private *lp = netdev_priv(dev); - struct list_head *walk = &pdev->bus_list; + struct list_head *walk; - for (walk = walk->next; walk != &pdev->bus_list; walk = walk->next) { + list_for_each(walk, &pdev->bus_list) { struct pci_dev *this_dev = pci_dev_b(walk); /* Skip the pci_bus list entry */ diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/dmfe.c linux-2.6.12.6/drivers/net/tulip/dmfe.c --- linux-2.6.12.6.orig/drivers/net/tulip/dmfe.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/dmfe.c 2005-10-02 23:47:39.000000000 +0000 @@ -78,6 +78,7 @@ #include #include #include +#include #include #include #include @@ -354,7 +355,7 @@ SET_MODULE_OWNER(dev); SET_NETDEV_DEV(dev, &pdev->dev); - if (pci_set_dma_mask(pdev, 0xffffffff)) { + if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n"); err = -ENODEV; goto err_out_free; @@ -743,11 +744,6 @@ DMFE_DBUG(0, "dmfe_interrupt()", 0); - if (!dev) { - DMFE_DBUG(1, "dmfe_interrupt() without DEVICE arg", 0); - return IRQ_NONE; - } - spin_lock_irqsave(&db->lock, flags); /* Got DM910X status */ @@ -949,8 +945,8 @@ /* Received Packet CRC check need or not */ if ( (db->dm910x_chk_mode & 1) && - (cal_CRC(skb->tail, rxlen, 1) != - (*(u32 *) (skb->tail+rxlen) ))) { /* FIXME (?) */ + (cal_CRC(skb->data, rxlen, 1) != + (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */ /* Found a error received packet */ dmfe_reuse_skb(db, rxptr->rx_skb_ptr); db->dm910x_chk_mode = 3; @@ -963,7 +959,7 @@ /* size less than COPY_SIZE, allocate a rxlen SKB */ skb->dev = dev; skb_reserve(skb, 2); /* 16byte align */ - memcpy(skb_put(skb, rxlen), rxptr->rx_skb_ptr->tail, rxlen); + memcpy(skb_put(skb, rxlen), rxptr->rx_skb_ptr->data, rxlen); dmfe_reuse_skb(db, rxptr->rx_skb_ptr); } else { skb->dev = dev; @@ -1256,7 +1252,7 @@ if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) { rxptr->rx_skb_ptr = skb; - rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) ); + rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) ); wmb(); rxptr->rdes0 = cpu_to_le32(0x80000000); db->rx_avail_cnt++; @@ -1467,7 +1463,7 @@ if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL ) break; rxptr->rx_skb_ptr = skb; /* FIXME (?) */ - rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) ); + rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) ); wmb(); rxptr->rdes0 = cpu_to_le32(0x80000000); rxptr = rxptr->next_rx_desc; @@ -1806,7 +1802,7 @@ if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) { /* SROM V4.01 */ /* Get NIC support media mode */ - db->NIC_capability = le16_to_cpup(srom + 34); + db->NIC_capability = le16_to_cpup((__le16 *)srom + 34/2); db->PHY_reg4 = 0; for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) { switch( db->NIC_capability & tmp_reg ) { @@ -1818,7 +1814,8 @@ } /* Media Mode Force or not check */ - dmfe_mode = le32_to_cpup(srom + 34) & le32_to_cpup(srom + 36); + dmfe_mode = le32_to_cpup((__le32 *)srom + 34/4) & + le32_to_cpup((__le32 *)srom + 36/4); switch(dmfe_mode) { case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */ case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */ diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/eeprom.c linux-2.6.12.6/drivers/net/tulip/eeprom.c --- linux-2.6.12.6.orig/drivers/net/tulip/eeprom.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/eeprom.c 2005-10-02 23:47:39.000000000 +0000 @@ -63,6 +63,22 @@ */ { 0x1e00, 0x0000, 0x000b, 0x8f01, 0x0103, 0x0300, 0x0821, 0x000, 0x0001, 0x0000, 0x01e1 } }, + {"Cobalt Microserver", 0, 0x10, 0xE0, {0x1e00, /* 0 == controller #, 1e == offset */ + 0x0000, /* 0 == high offset, 0 == gap */ + 0x0800, /* Default Autoselect */ + 0x8001, /* 1 leaf, extended type, bogus len */ + 0x0003, /* Type 3 (MII), PHY #0 */ + 0x0400, /* 0 init instr, 4 reset instr */ + 0x0801, /* Set control mode, GP0 output */ + 0x0000, /* Drive GP0 Low (RST is active low) */ + 0x0800, /* control mode, GP0 input (undriven) */ + 0x0000, /* clear control mode */ + 0x7800, /* 100TX FDX + HDX, 10bT FDX + HDX */ + 0x01e0, /* Advertise all above */ + 0x5000, /* FDX all above */ + 0x1800, /* Set fast TTM in 100bt modes */ + 0x0000, /* PHY cannot be unplugged */ + }}, {NULL}}; diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/interrupt.c linux-2.6.12.6/drivers/net/tulip/interrupt.c --- linux-2.6.12.6.orig/drivers/net/tulip/interrupt.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/interrupt.c 2005-10-02 23:47:39.000000000 +0000 @@ -78,7 +78,7 @@ if (skb == NULL) break; - mapping = pci_map_single(tp->pdev, skb->tail, PKT_BUF_SZ, + mapping = pci_map_single(tp->pdev, skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE); tp->rx_buffers[entry].mapping = mapping; @@ -199,12 +199,12 @@ tp->rx_buffers[entry].mapping, pkt_len, PCI_DMA_FROMDEVICE); #if ! defined(__alpha__) - eth_copy_and_sum(skb, tp->rx_buffers[entry].skb->tail, + eth_copy_and_sum(skb, tp->rx_buffers[entry].skb->data, pkt_len, 0); skb_put(skb, pkt_len); #else memcpy(skb_put(skb, pkt_len), - tp->rx_buffers[entry].skb->tail, + tp->rx_buffers[entry].skb->data, pkt_len); #endif pci_dma_sync_single_for_device(tp->pdev, @@ -423,12 +423,12 @@ tp->rx_buffers[entry].mapping, pkt_len, PCI_DMA_FROMDEVICE); #if ! defined(__alpha__) - eth_copy_and_sum(skb, tp->rx_buffers[entry].skb->tail, + eth_copy_and_sum(skb, tp->rx_buffers[entry].skb->data, pkt_len, 0); skb_put(skb, pkt_len); #else memcpy(skb_put(skb, pkt_len), - tp->rx_buffers[entry].skb->tail, + tp->rx_buffers[entry].skb->data, pkt_len); #endif pci_dma_sync_single_for_device(tp->pdev, diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/media.c linux-2.6.12.6/drivers/net/tulip/media.c --- linux-2.6.12.6.orig/drivers/net/tulip/media.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/media.c 2005-10-02 23:47:39.000000000 +0000 @@ -44,8 +44,10 @@ /* MII transceiver control section. Read and write the MII registers using software-generated serial - MDIO protocol. See the MII specifications or DP83840A data sheet - for details. */ + MDIO protocol. + See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions") + or DP83840A data sheet for more details. + */ int tulip_mdio_read(struct net_device *dev, int phy_id, int location) { @@ -81,25 +83,6 @@ return retval & 0xffff; } - if(tp->chip_id == ULI526X && tp->revision >= 0x40) { - int value; - int i = 1000; - - value = ioread32(ioaddr + CSR9); - iowrite32(value & 0xFFEFFFFF, ioaddr + CSR9); - - value = (phy_id << 21) | (location << 16) | 0x08000000; - iowrite32(value, ioaddr + CSR10); - - while(--i > 0) { - mdio_delay(); - if(ioread32(ioaddr + CSR10) & 0x10000000) - break; - } - retval = ioread32(ioaddr + CSR10); - spin_unlock_irqrestore(&tp->mii_lock, flags); - return retval & 0xFFFF; - } /* Establish sync by sending at least 32 logic ones. */ for (i = 32; i >= 0; i--) { iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr); @@ -159,23 +142,6 @@ spin_unlock_irqrestore(&tp->mii_lock, flags); return; } - if (tp->chip_id == ULI526X && tp->revision >= 0x40) { - int value; - int i = 1000; - - value = ioread32(ioaddr + CSR9); - iowrite32(value & 0xFFEFFFFF, ioaddr + CSR9); - - value = (phy_id << 21) | (location << 16) | 0x04000000 | (val & 0xFFFF); - iowrite32(value, ioaddr + CSR10); - - while(--i > 0) { - if (ioread32(ioaddr + CSR10) & 0x10000000) - break; - } - spin_unlock_irqrestore(&tp->mii_lock, flags); - return; - } /* Establish sync by sending 32 logic ones. */ for (i = 32; i >= 0; i--) { @@ -297,24 +263,56 @@ u16 *reset_sequence = &((u16*)(p+3))[init_length]; int reset_length = p[2 + init_length*2]; misc_info = reset_sequence + reset_length; - if (startup) + if (startup) { + int timeout = 10; /* max 1 ms */ for (i = 0; i < reset_length; i++) iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15); + + /* flush posted writes */ + ioread32(ioaddr + CSR15); + + /* Sect 3.10.3 in DP83840A.pdf (p39) */ + udelay(500); + + /* Section 4.2 in DP83840A.pdf (p43) */ + /* and IEEE 802.3 "22.2.4.1.1 Reset" */ + while (timeout-- && + (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET)) + udelay(100); + } for (i = 0; i < init_length; i++) iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15); + + ioread32(ioaddr + CSR15); /* flush posted writes */ } else { u8 *init_sequence = p + 2; u8 *reset_sequence = p + 3 + init_length; int reset_length = p[2 + init_length]; misc_info = (u16*)(reset_sequence + reset_length); if (startup) { + int timeout = 10; /* max 1 ms */ iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12); for (i = 0; i < reset_length; i++) iowrite32(reset_sequence[i], ioaddr + CSR12); + + /* flush posted writes */ + ioread32(ioaddr + CSR12); + + /* Sect 3.10.3 in DP83840A.pdf (p39) */ + udelay(500); + + /* Section 4.2 in DP83840A.pdf (p43) */ + /* and IEEE 802.3 "22.2.4.1.1 Reset" */ + while (timeout-- && + (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET)) + udelay(100); } for (i = 0; i < init_length; i++) iowrite32(init_sequence[i], ioaddr + CSR12); + + ioread32(ioaddr + CSR12); /* flush posted writes */ } + tmp_info = get_u16(&misc_info[1]); if (tmp_info) tp->advertising[phy_num] = tmp_info | 1; @@ -400,6 +398,9 @@ } tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0); + + mdelay(1); + return; } diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/timer.c linux-2.6.12.6/drivers/net/tulip/timer.c --- linux-2.6.12.6.orig/drivers/net/tulip/timer.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/timer.c 2005-10-02 23:47:39.000000000 +0000 @@ -39,7 +39,6 @@ case MX98713: case COMPEX9881: case DM910X: - case ULI526X: default: { struct medialeaf *mleaf; unsigned char *p; diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/tulip.h linux-2.6.12.6/drivers/net/tulip/tulip.h --- linux-2.6.12.6.orig/drivers/net/tulip/tulip.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/tulip.h 2005-10-02 23:47:39.000000000 +0000 @@ -88,7 +88,6 @@ I21145, DM910X, CONEXANT, - ULI526X }; @@ -475,18 +474,18 @@ udelay(10); if (!i) - printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed\n", - pci_name(tp->pdev)); + printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed" + " (CSR5 0x%x CSR6 0x%x)\n", + pci_name(tp->pdev), + ioread32(ioaddr + CSR5), + ioread32(ioaddr + CSR6)); } } static inline void tulip_restart_rxtx(struct tulip_private *tp) { - if(!(tp->chip_id == ULI526X && - (tp->revision == 0x40 || tp->revision == 0x50))) { - tulip_stop_rxtx(tp); - udelay(5); - } + tulip_stop_rxtx(tp); + udelay(5); tulip_start_rxtx(tp); } diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/tulip_core.c linux-2.6.12.6/drivers/net/tulip/tulip_core.c --- linux-2.6.12.6.orig/drivers/net/tulip/tulip_core.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/tulip_core.c 2005-10-02 23:47:39.000000000 +0000 @@ -22,7 +22,7 @@ #else #define DRV_VERSION "1.1.13" #endif -#define DRV_RELDATE "May 11, 2002" +#define DRV_RELDATE "December 15, 2004" #include @@ -148,7 +148,7 @@ HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer }, /* DC21142, DC21143 */ - { "Digital DS21143 Tulip", 128, 0x0801fbff, + { "Digital DS21142/DS21143 Tulip", 128, 0x0801fbff, HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY | HAS_INTR_MITIGATION | HAS_PCI_MWI, t21142_timer }, @@ -199,9 +199,6 @@ { "Conexant LANfinity", 256, 0x0001ebef, HAS_MII | HAS_ACPI, tulip_timer }, - /* ULi526X */ - { "ULi M5261/M5263", 128, 0x0001ebef, - HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI, tulip_timer }, }; @@ -239,9 +236,9 @@ { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, - { 0x10b9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ULI526X }, /* ALi 1563 integrated ethernet */ - { 0x10b9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ULI526X }, /* ALi 1563 integrated ethernet */ { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */ + { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */ + { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, { } /* terminate list */ }; MODULE_DEVICE_TABLE(pci, tulip_pci_tbl); @@ -521,7 +518,7 @@ dev->name); } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142 || tp->chip_id == MX98713 || tp->chip_id == COMPEX9881 - || tp->chip_id == DM910X || tp->chip_id == ULI526X) { + || tp->chip_id == DM910X) { printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, " "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n", dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12), @@ -624,7 +621,7 @@ tp->rx_buffers[i].skb = skb; if (skb == NULL) break; - mapping = pci_map_single(tp->pdev, skb->tail, + mapping = pci_map_single(tp->pdev, skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE); tp->rx_buffers[i].mapping = mapping; skb->dev = dev; /* Mark as being used by this device. */ @@ -1102,18 +1099,16 @@ entry = tp->cur_tx++ % TX_RING_SIZE; if (entry != 0) { - /* Avoid a chip errata by prefixing a dummy entry. Don't do - this on the ULI526X as it triggers a different problem */ - if (!(tp->chip_id == ULI526X && (tp->revision == 0x40 || tp->revision == 0x50))) { - tp->tx_buffers[entry].skb = NULL; - tp->tx_buffers[entry].mapping = 0; - tp->tx_ring[entry].length = - (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0; - tp->tx_ring[entry].buffer1 = 0; - /* Must set DescOwned later to avoid race with chip */ - dummy = entry; - entry = tp->cur_tx++ % TX_RING_SIZE; - } + /* Avoid a chip errata by prefixing a dummy entry. */ + tp->tx_buffers[entry].skb = NULL; + tp->tx_buffers[entry].mapping = 0; + tp->tx_ring[entry].length = + (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0; + tp->tx_ring[entry].buffer1 = 0; + /* Must set DescOwned later to avoid race with chip */ + dummy = entry; + entry = tp->cur_tx++ % TX_RING_SIZE; + } tp->tx_buffers[entry].skb = NULL; @@ -1234,10 +1229,6 @@ { if (pdev->vendor == 0x1282 && pdev->device == 0x9102) return 1; - if (pdev->vendor == 0x10b9 && pdev->device == 0x5261) - return 1; - if (pdev->vendor == 0x10b9 && pdev->device == 0x5263) - return 1; return 0; } @@ -1514,8 +1505,8 @@ (PCI_SLOT(pdev->devfn) == 12))) { /* Cobalt MAC address in first EEPROM locations. */ sa_offset = 0; - /* No media table either */ - tp->flags &= ~HAS_MEDIA_TABLE; + /* Ensure our media table fixup get's applied */ + memcpy(ee_data + 16, ee_data, 8); } #endif #ifdef CONFIG_GSC @@ -1679,7 +1670,6 @@ switch (chip_idx) { case DC21140: case DM910X: - case ULI526X: default: if (tp->mtable) iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12); @@ -1756,11 +1746,19 @@ { struct net_device *dev = pci_get_drvdata(pdev); - if (dev && netif_running (dev) && netif_device_present (dev)) { - netif_device_detach (dev); - tulip_down (dev); - /* pci_power_off(pdev, -1); */ - } + if (!dev) + return -EINVAL; + + if (netif_running(dev)) + tulip_down(dev); + + netif_device_detach(dev); + free_irq(dev->irq, dev); + + pci_save_state(pdev); + pci_disable_device(pdev); + pci_set_power_state(pdev, pci_choose_state(pdev, state)); + return 0; } @@ -1768,15 +1766,26 @@ static int tulip_resume(struct pci_dev *pdev) { struct net_device *dev = pci_get_drvdata(pdev); + int retval; + + if (!dev) + return -EINVAL; + + pci_set_power_state(pdev, PCI_D0); + pci_restore_state(pdev); - if (dev && netif_running (dev) && !netif_device_present (dev)) { -#if 1 - pci_enable_device (pdev); -#endif - /* pci_power_on(pdev); */ - tulip_up (dev); - netif_device_attach (dev); + pci_enable_device(pdev); + + if ((retval = request_irq(dev->irq, &tulip_interrupt, SA_SHIRQ, dev->name, dev))) { + printk (KERN_ERR "tulip: request_irq failed in resume\n"); + return retval; } + + netif_device_attach(dev); + + if (netif_running(dev)) + tulip_up(dev); + return 0; } diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/uli526x.c linux-2.6.12.6/drivers/net/tulip/uli526x.c --- linux-2.6.12.6.orig/drivers/net/tulip/uli526x.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/uli526x.c 2005-10-02 23:47:39.000000000 +0000 @@ -0,0 +1,1749 @@ +/* + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2 + of the License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + +*/ + +#define DRV_NAME "uli526x" +#define DRV_VERSION "0.9.3" +#define DRV_RELDATE "2005-7-29" + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +/* Board/System/Debug information/definition ---------------- */ +#define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/ +#define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/ + +#define ULI526X_IO_SIZE 0x100 +#define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */ +#define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */ +#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */ +#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */ +#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT) +#define TX_BUF_ALLOC 0x600 +#define RX_ALLOC_SIZE 0x620 +#define ULI526X_RESET 1 +#define CR0_DEFAULT 0 +#define CR6_DEFAULT 0x22200000 +#define CR7_DEFAULT 0x180c1 +#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */ +#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */ +#define MAX_PACKET_SIZE 1514 +#define ULI5261_MAX_MULTICAST 14 +#define RX_COPY_SIZE 100 +#define MAX_CHECK_PACKET 0x8000 + +#define ULI526X_10MHF 0 +#define ULI526X_100MHF 1 +#define ULI526X_10MFD 4 +#define ULI526X_100MFD 5 +#define ULI526X_AUTO 8 + +#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */ +#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */ +#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */ +#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */ +#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */ +#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */ + +#define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */ +#define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */ +#define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */ + +#define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value)) + +#define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half"); + + +/* CR9 definition: SROM/MII */ +#define CR9_SROM_READ 0x4800 +#define CR9_SRCS 0x1 +#define CR9_SRCLK 0x2 +#define CR9_CRDOUT 0x8 +#define SROM_DATA_0 0x0 +#define SROM_DATA_1 0x4 +#define PHY_DATA_1 0x20000 +#define PHY_DATA_0 0x00000 +#define MDCLKH 0x10000 + +#define PHY_POWER_DOWN 0x800 + +#define SROM_V41_CODE 0x14 + +#define SROM_CLK_WRITE(data, ioaddr) \ + outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \ + udelay(5); \ + outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \ + udelay(5); \ + outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \ + udelay(5); + +/* Structure/enum declaration ------------------------------- */ +struct tx_desc { + u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */ + char *tx_buf_ptr; /* Data for us */ + struct tx_desc *next_tx_desc; +} __attribute__(( aligned(32) )); + +struct rx_desc { + u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */ + struct sk_buff *rx_skb_ptr; /* Data for us */ + struct rx_desc *next_rx_desc; +} __attribute__(( aligned(32) )); + +struct uli526x_board_info { + u32 chip_id; /* Chip vendor/Device ID */ + struct net_device *next_dev; /* next device */ + struct pci_dev *pdev; /* PCI device */ + spinlock_t lock; + + long ioaddr; /* I/O base address */ + u32 cr0_data; + u32 cr5_data; + u32 cr6_data; + u32 cr7_data; + u32 cr15_data; + + /* pointer for memory physical address */ + dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */ + dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */ + dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */ + dma_addr_t first_tx_desc_dma; + dma_addr_t first_rx_desc_dma; + + /* descriptor pointer */ + unsigned char *buf_pool_ptr; /* Tx buffer pool memory */ + unsigned char *buf_pool_start; /* Tx buffer pool align dword */ + unsigned char *desc_pool_ptr; /* descriptor pool memory */ + struct tx_desc *first_tx_desc; + struct tx_desc *tx_insert_ptr; + struct tx_desc *tx_remove_ptr; + struct rx_desc *first_rx_desc; + struct rx_desc *rx_insert_ptr; + struct rx_desc *rx_ready_ptr; /* packet come pointer */ + unsigned long tx_packet_cnt; /* transmitted packet count */ + unsigned long rx_avail_cnt; /* available rx descriptor count */ + unsigned long interval_rx_cnt; /* rx packet count a callback time */ + + u16 dbug_cnt; + u16 NIC_capability; /* NIC media capability */ + u16 PHY_reg4; /* Saved Phyxcer register 4 value */ + + u8 media_mode; /* user specify media mode */ + u8 op_mode; /* real work media mode */ + u8 phy_addr; + u8 link_failed; /* Ever link failed */ + u8 wait_reset; /* Hardware failed, need to reset */ + struct timer_list timer; + + /* System defined statistic counter */ + struct net_device_stats stats; + + /* Driver defined statistic counter */ + unsigned long tx_fifo_underrun; + unsigned long tx_loss_carrier; + unsigned long tx_no_carrier; + unsigned long tx_late_collision; + unsigned long tx_excessive_collision; + unsigned long tx_jabber_timeout; + unsigned long reset_count; + unsigned long reset_cr8; + unsigned long reset_fatal; + unsigned long reset_TXtimeout; + + /* NIC SROM data */ + unsigned char srom[128]; + u8 init; +}; + +enum uli526x_offsets { + DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, + DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, + DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70, + DCR15 = 0x78 +}; + +enum uli526x_CR6_bits { + CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, + CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, + CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000 +}; + +/* Global variable declaration ----------------------------- */ +static int __devinitdata printed_version; +static char version[] __devinitdata = + KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version " + DRV_VERSION " (" DRV_RELDATE ")\n"; + +static int uli526x_debug; +static unsigned char uli526x_media_mode = ULI526X_AUTO; +static u32 uli526x_cr6_user_set; + +/* For module input parameter */ +static int debug; +static u32 cr6set; +static unsigned char mode = 8; + +/* function declaration ------------------------------------- */ +static int uli526x_open(struct net_device *); +static int uli526x_start_xmit(struct sk_buff *, struct net_device *); +static int uli526x_stop(struct net_device *); +static struct net_device_stats * uli526x_get_stats(struct net_device *); +static void uli526x_set_filter_mode(struct net_device *); +static struct ethtool_ops netdev_ethtool_ops; +static u16 read_srom_word(long, int); +static irqreturn_t uli526x_interrupt(int, void *, struct pt_regs *); +static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long); +static void allocate_rx_buffer(struct uli526x_board_info *); +static void update_cr6(u32, unsigned long); +static void send_filter_frame(struct net_device *, int); +static u16 phy_read(unsigned long, u8, u8, u32); +static u16 phy_readby_cr10(unsigned long, u8, u8); +static void phy_write(unsigned long, u8, u8, u16, u32); +static void phy_writeby_cr10(unsigned long, u8, u8, u16); +static void phy_write_1bit(unsigned long, u32, u32); +static u16 phy_read_1bit(unsigned long, u32); +static u8 uli526x_sense_speed(struct uli526x_board_info *); +static void uli526x_process_mode(struct uli526x_board_info *); +static void uli526x_timer(unsigned long); +static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *); +static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *); +static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *); +static void uli526x_dynamic_reset(struct net_device *); +static void uli526x_free_rxbuffer(struct uli526x_board_info *); +static void uli526x_init(struct net_device *); +static void uli526x_set_phyxcer(struct uli526x_board_info *); + +/* ULI526X network board routine ---------------------------- */ + +/* + * Search ULI526X board, allocate space and register it + */ + +static int __devinit uli526x_init_one (struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct uli526x_board_info *db; /* board information structure */ + struct net_device *dev; + int i, err; + + ULI526X_DBUG(0, "uli526x_init_one()", 0); + + if (!printed_version++) + printk(version); + + /* Init network device */ + dev = alloc_etherdev(sizeof(*db)); + if (dev == NULL) + return -ENOMEM; + SET_MODULE_OWNER(dev); + SET_NETDEV_DEV(dev, &pdev->dev); + + if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { + printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n"); + err = -ENODEV; + goto err_out_free; + } + + /* Enable Master/IO access, Disable memory access */ + err = pci_enable_device(pdev); + if (err) + goto err_out_free; + + if (!pci_resource_start(pdev, 0)) { + printk(KERN_ERR DRV_NAME ": I/O base is zero\n"); + err = -ENODEV; + goto err_out_disable; + } + + if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) { + printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n"); + err = -ENODEV; + goto err_out_disable; + } + + if (pci_request_regions(pdev, DRV_NAME)) { + printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n"); + err = -ENODEV; + goto err_out_disable; + } + + /* Init system & device */ + db = netdev_priv(dev); + + /* Allocate Tx/Rx descriptor memory */ + db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr); + if(db->desc_pool_ptr == NULL) + { + err = -ENOMEM; + goto err_out_nomem; + } + db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr); + if(db->buf_pool_ptr == NULL) + { + err = -ENOMEM; + goto err_out_nomem; + } + + db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; + db->first_tx_desc_dma = db->desc_pool_dma_ptr; + db->buf_pool_start = db->buf_pool_ptr; + db->buf_pool_dma_start = db->buf_pool_dma_ptr; + + db->chip_id = ent->driver_data; + db->ioaddr = pci_resource_start(pdev, 0); + + db->pdev = pdev; + db->init = 1; + + dev->base_addr = db->ioaddr; + dev->irq = pdev->irq; + pci_set_drvdata(pdev, dev); + + /* Register some necessary functions */ + dev->open = &uli526x_open; + dev->hard_start_xmit = &uli526x_start_xmit; + dev->stop = &uli526x_stop; + dev->get_stats = &uli526x_get_stats; + dev->set_multicast_list = &uli526x_set_filter_mode; + dev->ethtool_ops = &netdev_ethtool_ops; + spin_lock_init(&db->lock); + + + /* read 64 word srom data */ + for (i = 0; i < 64; i++) + ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i)); + + /* Set Node address */ + if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */ + { + outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode + outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port + outl(0, db->ioaddr + DCR14); //Clear reset port + outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer + outl(0, db->ioaddr + DCR14); //Clear reset port + outl(0, db->ioaddr + DCR13); //Clear CR13 + outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port + //Read MAC address from CR14 + for (i = 0; i < 6; i++) + dev->dev_addr[i] = inl(db->ioaddr + DCR14); + //Read end + outl(0, db->ioaddr + DCR13); //Clear CR13 + outl(0, db->ioaddr + DCR0); //Clear CR0 + udelay(10); + } + else /*Exist SROM*/ + { + for (i = 0; i < 6; i++) + dev->dev_addr[i] = db->srom[20 + i]; + } + err = register_netdev (dev); + if (err) + goto err_out_res; + + printk(KERN_INFO "%s: ULi M%04lx at pci%s,",dev->name,ent->driver_data >> 16,pci_name(pdev)); + + for (i = 0; i < 6; i++) + printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]); + printk(", irq %d.\n", dev->irq); + + pci_set_master(pdev); + + return 0; + +err_out_res: + pci_release_regions(pdev); +err_out_nomem: + if(db->desc_pool_ptr) + pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, + db->desc_pool_ptr, db->desc_pool_dma_ptr); + + if(db->buf_pool_ptr != NULL) + pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, + db->buf_pool_ptr, db->buf_pool_dma_ptr); +err_out_disable: + pci_disable_device(pdev); +err_out_free: + pci_set_drvdata(pdev, NULL); + free_netdev(dev); + + return err; +} + + +static void __devexit uli526x_remove_one (struct pci_dev *pdev) +{ + struct net_device *dev = pci_get_drvdata(pdev); + struct uli526x_board_info *db = netdev_priv(dev); + + ULI526X_DBUG(0, "uli526x_remove_one()", 0); + + pci_free_consistent(db->pdev, sizeof(struct tx_desc) * + DESC_ALL_CNT + 0x20, db->desc_pool_ptr, + db->desc_pool_dma_ptr); + pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, + db->buf_pool_ptr, db->buf_pool_dma_ptr); + unregister_netdev(dev); + pci_release_regions(pdev); + free_netdev(dev); /* free board information */ + pci_set_drvdata(pdev, NULL); + pci_disable_device(pdev); + ULI526X_DBUG(0, "uli526x_remove_one() exit", 0); +} + + +/* + * Open the interface. + * The interface is opened whenever "ifconfig" activates it. + */ + +static int uli526x_open(struct net_device *dev) +{ + int ret; + struct uli526x_board_info *db = netdev_priv(dev); + + ULI526X_DBUG(0, "uli526x_open", 0); + + ret = request_irq(dev->irq, &uli526x_interrupt, SA_SHIRQ, dev->name, dev); + if (ret) + return ret; + + /* system variable init */ + db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set; + db->tx_packet_cnt = 0; + db->rx_avail_cnt = 0; + db->link_failed = 1; + netif_carrier_off(dev); + db->wait_reset = 0; + + db->NIC_capability = 0xf; /* All capability*/ + db->PHY_reg4 = 0x1e0; + + /* CR6 operation mode decision */ + db->cr6_data |= ULI526X_TXTH_256; + db->cr0_data = CR0_DEFAULT; + + /* Initialize ULI526X board */ + uli526x_init(dev); + + /* Active System Interface */ + netif_wake_queue(dev); + + /* set and active a timer process */ + init_timer(&db->timer); + db->timer.expires = ULI526X_TIMER_WUT + HZ * 2; + db->timer.data = (unsigned long)dev; + db->timer.function = &uli526x_timer; + add_timer(&db->timer); + + return 0; +} + + +/* Initialize ULI526X board + * Reset ULI526X board + * Initialize TX/Rx descriptor chain structure + * Send the set-up frame + * Enable Tx/Rx machine + */ + +static void uli526x_init(struct net_device *dev) +{ + struct uli526x_board_info *db = netdev_priv(dev); + unsigned long ioaddr = db->ioaddr; + u8 phy_tmp; + u16 phy_value; + u16 phy_reg_reset; + + ULI526X_DBUG(0, "uli526x_init()", 0); + + /* Reset M526x MAC controller */ + outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */ + udelay(100); + outl(db->cr0_data, ioaddr + DCR0); + udelay(5); + + /* Phy addr : In some boards,M5261/M5263 phy address != 1 */ + db->phy_addr = 1; + for(phy_tmp=0;phy_tmp<32;phy_tmp++) + { + phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add + if(phy_value != 0xffff&&phy_value!=0) + { + db->phy_addr = phy_tmp; + break; + } + } + if(phy_tmp == 32) + printk(KERN_WARNING "Can not find the phy address!!!"); + /* Parser SROM and media mode */ + db->media_mode = uli526x_media_mode; + + /* Phyxcer capability setting */ + phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id); + phy_reg_reset = (phy_reg_reset | 0x8000); + phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id); + udelay(500); + + /* Process Phyxcer Media Mode */ + uli526x_set_phyxcer(db); + + /* Media Mode Process */ + if ( !(db->media_mode & ULI526X_AUTO) ) + db->op_mode = db->media_mode; /* Force Mode */ + + /* Initialize Transmit/Receive decriptor and CR3/4 */ + uli526x_descriptor_init(db, ioaddr); + + /* Init CR6 to program M526X operation */ + update_cr6(db->cr6_data, ioaddr); + + /* Send setup frame */ + send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */ + + /* Init CR7, interrupt active bit */ + db->cr7_data = CR7_DEFAULT; + outl(db->cr7_data, ioaddr + DCR7); + + /* Init CR15, Tx jabber and Rx watchdog timer */ + outl(db->cr15_data, ioaddr + DCR15); + + /* Enable ULI526X Tx/Rx function */ + db->cr6_data |= CR6_RXSC | CR6_TXSC; + update_cr6(db->cr6_data, ioaddr); +} + + +/* + * Hardware start transmission. + * Send a packet to media from the upper layer. + */ + +static int uli526x_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct uli526x_board_info *db = netdev_priv(dev); + struct tx_desc *txptr; + unsigned long flags; + + ULI526X_DBUG(0, "uli526x_start_xmit", 0); + + /* Resource flag check */ + netif_stop_queue(dev); + + /* Too large packet check */ + if (skb->len > MAX_PACKET_SIZE) { + printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len); + dev_kfree_skb(skb); + return 0; + } + + spin_lock_irqsave(&db->lock, flags); + + /* No Tx resource check, it never happen nromally */ + if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) { + spin_unlock_irqrestore(&db->lock, flags); + printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_packet_cnt); + return 1; + } + + /* Disable NIC interrupt */ + outl(0, dev->base_addr + DCR7); + + /* transmit this packet */ + txptr = db->tx_insert_ptr; + memcpy(txptr->tx_buf_ptr, skb->data, skb->len); + txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len); + + /* Point to next transmit free descriptor */ + db->tx_insert_ptr = txptr->next_tx_desc; + + /* Transmit Packet Process */ + if ( (db->tx_packet_cnt < TX_DESC_CNT) ) { + txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ + db->tx_packet_cnt++; /* Ready to send */ + outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */ + dev->trans_start = jiffies; /* saved time stamp */ + } + + /* Tx resource check */ + if ( db->tx_packet_cnt < TX_FREE_DESC_CNT ) + netif_wake_queue(dev); + + /* Restore CR7 to enable interrupt */ + spin_unlock_irqrestore(&db->lock, flags); + outl(db->cr7_data, dev->base_addr + DCR7); + + /* free this SKB */ + dev_kfree_skb(skb); + + return 0; +} + + +/* + * Stop the interface. + * The interface is stopped when it is brought. + */ + +static int uli526x_stop(struct net_device *dev) +{ + struct uli526x_board_info *db = netdev_priv(dev); + unsigned long ioaddr = dev->base_addr; + + ULI526X_DBUG(0, "uli526x_stop", 0); + + /* disable system */ + netif_stop_queue(dev); + + /* deleted timer */ + del_timer_sync(&db->timer); + + /* Reset & stop ULI526X board */ + outl(ULI526X_RESET, ioaddr + DCR0); + udelay(5); + phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); + + /* free interrupt */ + free_irq(dev->irq, dev); + + /* free allocated rx buffer */ + uli526x_free_rxbuffer(db); + +#if 0 + /* show statistic counter */ + printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n", + db->tx_fifo_underrun, db->tx_excessive_collision, + db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier, + db->tx_jabber_timeout, db->reset_count, db->reset_cr8, + db->reset_fatal, db->reset_TXtimeout); +#endif + + return 0; +} + + +/* + * M5261/M5263 insterrupt handler + * receive the packet to upper layer, free the transmitted packet + */ + +static irqreturn_t uli526x_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + struct net_device *dev = dev_id; + struct uli526x_board_info *db = netdev_priv(dev); + unsigned long ioaddr = dev->base_addr; + unsigned long flags; + + if (!dev) { + ULI526X_DBUG(1, "uli526x_interrupt() without DEVICE arg", 0); + return IRQ_NONE; + } + + spin_lock_irqsave(&db->lock, flags); + outl(0, ioaddr + DCR7); + + /* Got ULI526X status */ + db->cr5_data = inl(ioaddr + DCR5); + outl(db->cr5_data, ioaddr + DCR5); + if ( !(db->cr5_data & 0x180c1) ) { + spin_unlock_irqrestore(&db->lock, flags); + outl(db->cr7_data, ioaddr + DCR7); + return IRQ_HANDLED; + } + + /* Check system status */ + if (db->cr5_data & 0x2000) { + /* system bus error happen */ + ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data); + db->reset_fatal++; + db->wait_reset = 1; /* Need to RESET */ + spin_unlock_irqrestore(&db->lock, flags); + return IRQ_HANDLED; + } + + /* Received the coming packet */ + if ( (db->cr5_data & 0x40) && db->rx_avail_cnt ) + uli526x_rx_packet(dev, db); + + /* reallocate rx descriptor buffer */ + if (db->rx_avail_cntcr5_data & 0x01) + uli526x_free_tx_pkt(dev, db); + + /* Restore CR7 to enable interrupt mask */ + outl(db->cr7_data, ioaddr + DCR7); + + spin_unlock_irqrestore(&db->lock, flags); + return IRQ_HANDLED; +} + + +/* + * Free TX resource after TX complete + */ + +static void uli526x_free_tx_pkt(struct net_device *dev, struct uli526x_board_info * db) +{ + struct tx_desc *txptr; + u32 tdes0; + + txptr = db->tx_remove_ptr; + while(db->tx_packet_cnt) { + tdes0 = le32_to_cpu(txptr->tdes0); + /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */ + if (tdes0 & 0x80000000) + break; + + /* A packet sent completed */ + db->tx_packet_cnt--; + db->stats.tx_packets++; + + /* Transmit statistic counter */ + if ( tdes0 != 0x7fffffff ) { + /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */ + db->stats.collisions += (tdes0 >> 3) & 0xf; + db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff; + if (tdes0 & TDES0_ERR_MASK) { + db->stats.tx_errors++; + if (tdes0 & 0x0002) { /* UnderRun */ + db->tx_fifo_underrun++; + if ( !(db->cr6_data & CR6_SFT) ) { + db->cr6_data = db->cr6_data | CR6_SFT; + update_cr6(db->cr6_data, db->ioaddr); + } + } + if (tdes0 & 0x0100) + db->tx_excessive_collision++; + if (tdes0 & 0x0200) + db->tx_late_collision++; + if (tdes0 & 0x0400) + db->tx_no_carrier++; + if (tdes0 & 0x0800) + db->tx_loss_carrier++; + if (tdes0 & 0x4000) + db->tx_jabber_timeout++; + } + } + + txptr = txptr->next_tx_desc; + }/* End of while */ + + /* Update TX remove pointer to next */ + db->tx_remove_ptr = txptr; + + /* Resource available check */ + if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT ) + netif_wake_queue(dev); /* Active upper layer, send again */ +} + + +/* + * Receive the come packet and pass to upper layer + */ + +static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db) +{ + struct rx_desc *rxptr; + struct sk_buff *skb; + int rxlen; + u32 rdes0; + + rxptr = db->rx_ready_ptr; + + while(db->rx_avail_cnt) { + rdes0 = le32_to_cpu(rxptr->rdes0); + if (rdes0 & 0x80000000) /* packet owner check */ + { + break; + } + + db->rx_avail_cnt--; + db->interval_rx_cnt++; + + pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE); + if ( (rdes0 & 0x300) != 0x300) { + /* A packet without First/Last flag */ + /* reuse this SKB */ + ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); + uli526x_reuse_skb(db, rxptr->rx_skb_ptr); + } else { + /* A packet with First/Last flag */ + rxlen = ( (rdes0 >> 16) & 0x3fff) - 4; + + /* error summary bit check */ + if (rdes0 & 0x8000) { + /* This is a error packet */ + //printk(DRV_NAME ": rdes0: %lx\n", rdes0); + db->stats.rx_errors++; + if (rdes0 & 1) + db->stats.rx_fifo_errors++; + if (rdes0 & 2) + db->stats.rx_crc_errors++; + if (rdes0 & 0x80) + db->stats.rx_length_errors++; + } + + if ( !(rdes0 & 0x8000) || + ((db->cr6_data & CR6_PM) && (rxlen>6)) ) { + skb = rxptr->rx_skb_ptr; + + /* Good packet, send to upper layer */ + /* Shorst packet used new SKB */ + if ( (rxlen < RX_COPY_SIZE) && + ( (skb = dev_alloc_skb(rxlen + 2) ) + != NULL) ) { + /* size less than COPY_SIZE, allocate a rxlen SKB */ + skb->dev = dev; + skb_reserve(skb, 2); /* 16byte align */ + memcpy(skb_put(skb, rxlen), rxptr->rx_skb_ptr->tail, rxlen); + uli526x_reuse_skb(db, rxptr->rx_skb_ptr); + } else { + skb->dev = dev; + skb_put(skb, rxlen); + } + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + dev->last_rx = jiffies; + db->stats.rx_packets++; + db->stats.rx_bytes += rxlen; + + } else { + /* Reuse SKB buffer when the packet is error */ + ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); + uli526x_reuse_skb(db, rxptr->rx_skb_ptr); + } + } + + rxptr = rxptr->next_rx_desc; + } + + db->rx_ready_ptr = rxptr; +} + + +/* + * Get statistics from driver. + */ + +static struct net_device_stats * uli526x_get_stats(struct net_device *dev) +{ + struct uli526x_board_info *db = netdev_priv(dev); + + ULI526X_DBUG(0, "uli526x_get_stats", 0); + return &db->stats; +} + + +/* + * Set ULI526X multicast address + */ + +static void uli526x_set_filter_mode(struct net_device * dev) +{ + struct uli526x_board_info *db = dev->priv; + unsigned long flags; + + ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0); + spin_lock_irqsave(&db->lock, flags); + + if (dev->flags & IFF_PROMISC) { + ULI526X_DBUG(0, "Enable PROM Mode", 0); + db->cr6_data |= CR6_PM | CR6_PBF; + update_cr6(db->cr6_data, db->ioaddr); + spin_unlock_irqrestore(&db->lock, flags); + return; + } + + if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) { + ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count); + db->cr6_data &= ~(CR6_PM | CR6_PBF); + db->cr6_data |= CR6_PAM; + spin_unlock_irqrestore(&db->lock, flags); + return; + } + + ULI526X_DBUG(0, "Set multicast address", dev->mc_count); + send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */ + spin_unlock_irqrestore(&db->lock, flags); +} + +static void +ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd) +{ + ecmd->supported = (SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_Autoneg | + SUPPORTED_MII); + + ecmd->advertising = (ADVERTISED_10baseT_Half | + ADVERTISED_10baseT_Full | + ADVERTISED_100baseT_Half | + ADVERTISED_100baseT_Full | + ADVERTISED_Autoneg | + ADVERTISED_MII); + + + ecmd->port = PORT_MII; + ecmd->phy_address = db->phy_addr; + + ecmd->transceiver = XCVR_EXTERNAL; + + ecmd->speed = 10; + ecmd->duplex = DUPLEX_HALF; + + if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD) + { + ecmd->speed = 100; + } + if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD) + { + ecmd->duplex = DUPLEX_FULL; + } + if(db->link_failed) + { + ecmd->speed = -1; + ecmd->duplex = -1; + } + + if (db->media_mode & ULI526X_AUTO) + { + ecmd->autoneg = AUTONEG_ENABLE; + } +} + +static void netdev_get_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + struct uli526x_board_info *np = netdev_priv(dev); + + strcpy(info->driver, DRV_NAME); + strcpy(info->version, DRV_VERSION); + if (np->pdev) + strcpy(info->bus_info, pci_name(np->pdev)); + else + sprintf(info->bus_info, "EISA 0x%lx %d", + dev->base_addr, dev->irq); +} + +static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { + struct uli526x_board_info *np = netdev_priv(dev); + + ULi_ethtool_gset(np, cmd); + + return 0; +} + +static u32 netdev_get_link(struct net_device *dev) { + struct uli526x_board_info *np = netdev_priv(dev); + + if(np->link_failed) + return 0; + else + return 1; +} + +static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) +{ + wol->supported = WAKE_PHY | WAKE_MAGIC; + wol->wolopts = 0; +} + +static struct ethtool_ops netdev_ethtool_ops = { + .get_drvinfo = netdev_get_drvinfo, + .get_settings = netdev_get_settings, + .get_link = netdev_get_link, + .get_wol = uli526x_get_wol, +}; + +/* + * A periodic timer routine + * Dynamic media sense, allocate Rx buffer... + */ + +static void uli526x_timer(unsigned long data) +{ + u32 tmp_cr8; + unsigned char tmp_cr12=0; + struct net_device *dev = (struct net_device *) data; + struct uli526x_board_info *db = netdev_priv(dev); + unsigned long flags; + u8 TmpSpeed=10; + + //ULI526X_DBUG(0, "uli526x_timer()", 0); + spin_lock_irqsave(&db->lock, flags); + + + /* Dynamic reset ULI526X : system error or transmit time-out */ + tmp_cr8 = inl(db->ioaddr + DCR8); + if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) { + db->reset_cr8++; + db->wait_reset = 1; + } + db->interval_rx_cnt = 0; + + /* TX polling kick monitor */ + if ( db->tx_packet_cnt && + time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) { + outl(0x1, dev->base_addr + DCR1); // Tx polling again + + // TX Timeout + if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) { + db->reset_TXtimeout++; + db->wait_reset = 1; + printk( "%s: Tx timeout - resetting\n", + dev->name); + } + } + + if (db->wait_reset) { + ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt); + db->reset_count++; + uli526x_dynamic_reset(dev); + db->timer.expires = ULI526X_TIMER_WUT; + add_timer(&db->timer); + spin_unlock_irqrestore(&db->lock, flags); + return; + } + + /* Link status check, Dynamic media type change */ + if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0) + tmp_cr12 = 3; + + if ( !(tmp_cr12 & 0x3) && !db->link_failed ) { + /* Link Failed */ + ULI526X_DBUG(0, "Link Failed", tmp_cr12); + netif_carrier_off(dev); + printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name); + db->link_failed = 1; + + /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */ + /* AUTO don't need */ + if ( !(db->media_mode & 0x8) ) + phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id); + + /* AUTO mode, if INT phyxcer link failed, select EXT device */ + if (db->media_mode & ULI526X_AUTO) { + db->cr6_data&=~0x00000200; /* bit9=0, HD mode */ + update_cr6(db->cr6_data, db->ioaddr); + } + } else + if ((tmp_cr12 & 0x3) && db->link_failed) { + ULI526X_DBUG(0, "Link link OK", tmp_cr12); + db->link_failed = 0; + + /* Auto Sense Speed */ + if ( (db->media_mode & ULI526X_AUTO) && + uli526x_sense_speed(db) ) + db->link_failed = 1; + uli526x_process_mode(db); + + if(db->link_failed==0) + { + if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD) + { + TmpSpeed = 100; + } + if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD) + { + printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed); + } + else + { + printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed); + } + netif_carrier_on(dev); + } + /* SHOW_MEDIA_TYPE(db->op_mode); */ + } + else if(!(tmp_cr12 & 0x3) && db->link_failed) + { + if(db->init==1) + { + printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name); + netif_carrier_off(dev); + } + } + db->init=0; + + /* Timer active again */ + db->timer.expires = ULI526X_TIMER_WUT; + add_timer(&db->timer); + spin_unlock_irqrestore(&db->lock, flags); +} + + +/* + * Dynamic reset the ULI526X board + * Stop ULI526X board + * Free Tx/Rx allocated memory + * Reset ULI526X board + * Re-initialize ULI526X board + */ + +static void uli526x_dynamic_reset(struct net_device *dev) +{ + struct uli526x_board_info *db = netdev_priv(dev); + + ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0); + + /* Sopt MAC controller */ + db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */ + update_cr6(db->cr6_data, dev->base_addr); + outl(0, dev->base_addr + DCR7); /* Disable Interrupt */ + outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5); + + /* Disable upper layer interface */ + netif_stop_queue(dev); + + /* Free Rx Allocate buffer */ + uli526x_free_rxbuffer(db); + + /* system variable init */ + db->tx_packet_cnt = 0; + db->rx_avail_cnt = 0; + db->link_failed = 1; + db->init=1; + db->wait_reset = 0; + + /* Re-initialize ULI526X board */ + uli526x_init(dev); + + /* Restart upper layer interface */ + netif_wake_queue(dev); +} + + +/* + * free all allocated rx buffer + */ + +static void uli526x_free_rxbuffer(struct uli526x_board_info * db) +{ + ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0); + + /* free allocated rx buffer */ + while (db->rx_avail_cnt) { + dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr); + db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc; + db->rx_avail_cnt--; + } +} + + +/* + * Reuse the SK buffer + */ + +static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb) +{ + struct rx_desc *rxptr = db->rx_insert_ptr; + + if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) { + rxptr->rx_skb_ptr = skb; + rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) ); + wmb(); + rxptr->rdes0 = cpu_to_le32(0x80000000); + db->rx_avail_cnt++; + db->rx_insert_ptr = rxptr->next_rx_desc; + } else + ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt); +} + + +/* + * Initialize transmit/Receive descriptor + * Using Chain structure, and allocate Tx/Rx buffer + */ + +static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr) +{ + struct tx_desc *tmp_tx; + struct rx_desc *tmp_rx; + unsigned char *tmp_buf; + dma_addr_t tmp_tx_dma, tmp_rx_dma; + dma_addr_t tmp_buf_dma; + int i; + + ULI526X_DBUG(0, "uli526x_descriptor_init()", 0); + + /* tx descriptor start pointer */ + db->tx_insert_ptr = db->first_tx_desc; + db->tx_remove_ptr = db->first_tx_desc; + outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */ + + /* rx descriptor start pointer */ + db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT; + db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT; + db->rx_insert_ptr = db->first_rx_desc; + db->rx_ready_ptr = db->first_rx_desc; + outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */ + + /* Init Transmit chain */ + tmp_buf = db->buf_pool_start; + tmp_buf_dma = db->buf_pool_dma_start; + tmp_tx_dma = db->first_tx_desc_dma; + for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) { + tmp_tx->tx_buf_ptr = tmp_buf; + tmp_tx->tdes0 = cpu_to_le32(0); + tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */ + tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma); + tmp_tx_dma += sizeof(struct tx_desc); + tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma); + tmp_tx->next_tx_desc = tmp_tx + 1; + tmp_buf = tmp_buf + TX_BUF_ALLOC; + tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC; + } + (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma); + tmp_tx->next_tx_desc = db->first_tx_desc; + + /* Init Receive descriptor chain */ + tmp_rx_dma=db->first_rx_desc_dma; + for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) { + tmp_rx->rdes0 = cpu_to_le32(0); + tmp_rx->rdes1 = cpu_to_le32(0x01000600); + tmp_rx_dma += sizeof(struct rx_desc); + tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma); + tmp_rx->next_rx_desc = tmp_rx + 1; + } + (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma); + tmp_rx->next_rx_desc = db->first_rx_desc; + + /* pre-allocate Rx buffer */ + allocate_rx_buffer(db); +} + + +/* + * Update CR6 value + * Firstly stop ULI526X, then written value and start + */ + +static void update_cr6(u32 cr6_data, unsigned long ioaddr) +{ + + outl(cr6_data, ioaddr + DCR6); + udelay(5); +} + + +/* + * Send a setup frame for M5261/M5263 + * This setup frame initialize ULI526X address filter mode + */ + +static void send_filter_frame(struct net_device *dev, int mc_cnt) +{ + struct uli526x_board_info *db = netdev_priv(dev); + struct dev_mc_list *mcptr; + struct tx_desc *txptr; + u16 * addrptr; + u32 * suptr; + int i; + + ULI526X_DBUG(0, "send_filter_frame()", 0); + + txptr = db->tx_insert_ptr; + suptr = (u32 *) txptr->tx_buf_ptr; + + /* Node address */ + addrptr = (u16 *) dev->dev_addr; + *suptr++ = addrptr[0]; + *suptr++ = addrptr[1]; + *suptr++ = addrptr[2]; + + /* broadcast address */ + *suptr++ = 0xffff; + *suptr++ = 0xffff; + *suptr++ = 0xffff; + + /* fit the multicast address */ + for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { + addrptr = (u16 *) mcptr->dmi_addr; + *suptr++ = addrptr[0]; + *suptr++ = addrptr[1]; + *suptr++ = addrptr[2]; + } + + for (; i<14; i++) { + *suptr++ = 0xffff; + *suptr++ = 0xffff; + *suptr++ = 0xffff; + } + + /* prepare the setup frame */ + db->tx_insert_ptr = txptr->next_tx_desc; + txptr->tdes1 = cpu_to_le32(0x890000c0); + + /* Resource Check and Send the setup packet */ + if (db->tx_packet_cnt < TX_DESC_CNT) { + /* Resource Empty */ + db->tx_packet_cnt++; + txptr->tdes0 = cpu_to_le32(0x80000000); + update_cr6(db->cr6_data | 0x2000, dev->base_addr); + outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */ + update_cr6(db->cr6_data, dev->base_addr); + dev->trans_start = jiffies; + } else + printk(KERN_ERR DRV_NAME ": No Tx resource - Send_filter_frame!\n"); +} + + +/* + * Allocate rx buffer, + * As possible as allocate maxiumn Rx buffer + */ + +static void allocate_rx_buffer(struct uli526x_board_info *db) +{ + struct rx_desc *rxptr; + struct sk_buff *skb; + + rxptr = db->rx_insert_ptr; + + while(db->rx_avail_cnt < RX_DESC_CNT) { + if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL ) + break; + rxptr->rx_skb_ptr = skb; /* FIXME (?) */ + rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) ); + wmb(); + rxptr->rdes0 = cpu_to_le32(0x80000000); + rxptr = rxptr->next_rx_desc; + db->rx_avail_cnt++; + } + + db->rx_insert_ptr = rxptr; +} + + +/* + * Read one word data from the serial ROM + */ + +static u16 read_srom_word(long ioaddr, int offset) +{ + int i; + u16 srom_data = 0; + long cr9_ioaddr = ioaddr + DCR9; + + outl(CR9_SROM_READ, cr9_ioaddr); + outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); + + /* Send the Read Command 110b */ + SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); + SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); + SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr); + + /* Send the offset */ + for (i = 5; i >= 0; i--) { + srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0; + SROM_CLK_WRITE(srom_data, cr9_ioaddr); + } + + outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); + + for (i = 16; i > 0; i--) { + outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr); + udelay(5); + srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0); + outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); + udelay(5); + } + + outl(CR9_SROM_READ, cr9_ioaddr); + return srom_data; +} + + +/* + * Auto sense the media mode + */ + +static u8 uli526x_sense_speed(struct uli526x_board_info * db) +{ + u8 ErrFlag = 0; + u16 phy_mode; + + phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); + phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); + + if ( (phy_mode & 0x24) == 0x24 ) { + + phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7); + if(phy_mode&0x8000) + phy_mode = 0x8000; + else if(phy_mode&0x4000) + phy_mode = 0x4000; + else if(phy_mode&0x2000) + phy_mode = 0x2000; + else + phy_mode = 0x1000; + + /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */ + switch (phy_mode) { + case 0x1000: db->op_mode = ULI526X_10MHF; break; + case 0x2000: db->op_mode = ULI526X_10MFD; break; + case 0x4000: db->op_mode = ULI526X_100MHF; break; + case 0x8000: db->op_mode = ULI526X_100MFD; break; + default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break; + } + } else { + db->op_mode = ULI526X_10MHF; + ULI526X_DBUG(0, "Link Failed :", phy_mode); + ErrFlag = 1; + } + + return ErrFlag; +} + + +/* + * Set 10/100 phyxcer capability + * AUTO mode : phyxcer register4 is NIC capability + * Force mode: phyxcer register4 is the force media + */ + +static void uli526x_set_phyxcer(struct uli526x_board_info *db) +{ + u16 phy_reg; + + /* Phyxcer capability setting */ + phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0; + + if (db->media_mode & ULI526X_AUTO) { + /* AUTO Mode */ + phy_reg |= db->PHY_reg4; + } else { + /* Force Mode */ + switch(db->media_mode) { + case ULI526X_10MHF: phy_reg |= 0x20; break; + case ULI526X_10MFD: phy_reg |= 0x40; break; + case ULI526X_100MHF: phy_reg |= 0x80; break; + case ULI526X_100MFD: phy_reg |= 0x100; break; + } + + } + + /* Write new capability to Phyxcer Reg4 */ + if ( !(phy_reg & 0x01e0)) { + phy_reg|=db->PHY_reg4; + db->media_mode|=ULI526X_AUTO; + } + phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id); + + /* Restart Auto-Negotiation */ + phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); + udelay(50); +} + + +/* + * Process op-mode + AUTO mode : PHY controller in Auto-negotiation Mode + * Force mode: PHY controller in force mode with HUB + * N-way force capability with SWITCH + */ + +static void uli526x_process_mode(struct uli526x_board_info *db) +{ + u16 phy_reg; + + /* Full Duplex Mode Check */ + if (db->op_mode & 0x4) + db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */ + else + db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */ + + update_cr6(db->cr6_data, db->ioaddr); + + /* 10/100M phyxcer force mode need */ + if ( !(db->media_mode & 0x8)) { + /* Forece Mode */ + phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id); + if ( !(phy_reg & 0x1) ) { + /* parter without N-Way capability */ + phy_reg = 0x0; + switch(db->op_mode) { + case ULI526X_10MHF: phy_reg = 0x0; break; + case ULI526X_10MFD: phy_reg = 0x100; break; + case ULI526X_100MHF: phy_reg = 0x2000; break; + case ULI526X_100MFD: phy_reg = 0x2100; break; + } + phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id); + phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id); + } + } +} + + +/* + * Write a word to Phy register + */ + +static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id) +{ + u16 i; + unsigned long ioaddr; + + if(chip_id == PCI_ULI5263_ID) + { + phy_writeby_cr10(iobase, phy_addr, offset, phy_data); + return; + } + /* M5261/M5263 Chip */ + ioaddr = iobase + DCR9; + + /* Send 33 synchronization clock to Phy controller */ + for (i = 0; i < 35; i++) + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + + /* Send start command(01) to Phy */ + phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + + /* Send write command(01) to Phy */ + phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + + /* Send Phy address */ + for (i = 0x10; i > 0; i = i >> 1) + phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); + + /* Send register address */ + for (i = 0x10; i > 0; i = i >> 1) + phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); + + /* written trasnition */ + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); + + /* Write a word data to PHY controller */ + for ( i = 0x8000; i > 0; i >>= 1) + phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); + +} + + +/* + * Read a word data from phy register + */ + +static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id) +{ + int i; + u16 phy_data; + unsigned long ioaddr; + + if(chip_id == PCI_ULI5263_ID) + return phy_readby_cr10(iobase, phy_addr, offset); + /* M5261/M5263 Chip */ + ioaddr = iobase + DCR9; + + /* Send 33 synchronization clock to Phy controller */ + for (i = 0; i < 35; i++) + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + + /* Send start command(01) to Phy */ + phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + + /* Send read command(10) to Phy */ + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); + + /* Send Phy address */ + for (i = 0x10; i > 0; i = i >> 1) + phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); + + /* Send register address */ + for (i = 0x10; i > 0; i = i >> 1) + phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); + + /* Skip transition state */ + phy_read_1bit(ioaddr, chip_id); + + /* read 16bit data */ + for (phy_data = 0, i = 0; i < 16; i++) { + phy_data <<= 1; + phy_data |= phy_read_1bit(ioaddr, chip_id); + } + + return phy_data; +} + +static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset) +{ + unsigned long ioaddr,cr10_value; + + ioaddr = iobase + DCR10; + cr10_value = phy_addr; + cr10_value = (cr10_value<<5) + offset; + cr10_value = (cr10_value<<16) + 0x08000000; + outl(cr10_value,ioaddr); + udelay(1); + while(1) + { + cr10_value = inl(ioaddr); + if(cr10_value&0x10000000) + break; + } + return (cr10_value&0x0ffff); +} + +static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data) +{ + unsigned long ioaddr,cr10_value; + + ioaddr = iobase + DCR10; + cr10_value = phy_addr; + cr10_value = (cr10_value<<5) + offset; + cr10_value = (cr10_value<<16) + 0x04000000 + phy_data; + outl(cr10_value,ioaddr); + udelay(1); +} +/* + * Write one bit data to Phy Controller + */ + +static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id) +{ + outl(phy_data , ioaddr); /* MII Clock Low */ + udelay(1); + outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ + udelay(1); + outl(phy_data , ioaddr); /* MII Clock Low */ + udelay(1); +} + + +/* + * Read one bit phy data from PHY controller + */ + +static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id) +{ + u16 phy_data; + + outl(0x50000 , ioaddr); + udelay(1); + phy_data = ( inl(ioaddr) >> 19 ) & 0x1; + outl(0x40000 , ioaddr); + udelay(1); + + return phy_data; +} + + +static struct pci_device_id uli526x_pci_tbl[] = { + { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID }, + { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID }, + { 0, } +}; +MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl); + + +static struct pci_driver uli526x_driver = { + .name = "uli526x", + .id_table = uli526x_pci_tbl, + .probe = uli526x_init_one, + .remove = __devexit_p(uli526x_remove_one), +}; + +MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw"); +MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver"); +MODULE_LICENSE("GPL"); + +MODULE_PARM(debug, "i"); +MODULE_PARM(mode, "i"); +MODULE_PARM(cr6set, "i"); +MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)"); +MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA"); + +/* Description: + * when user used insmod to add module, system invoked init_module() + * to register the services. + */ + +static int __init uli526x_init_module(void) +{ + int rc; + + printk(version); + printed_version = 1; + + ULI526X_DBUG(0, "init_module() ", debug); + + if (debug) + uli526x_debug = debug; /* set debug flag */ + if (cr6set) + uli526x_cr6_user_set = cr6set; + + switch(mode) { + case ULI526X_10MHF: + case ULI526X_100MHF: + case ULI526X_10MFD: + case ULI526X_100MFD: + uli526x_media_mode = mode; + break; + default:uli526x_media_mode = ULI526X_AUTO; + break; + } + + rc = pci_module_init(&uli526x_driver); + if (rc < 0) + return rc; + + return 0; +} + + +/* + * Description: + * when user used rmmod to delete module, system invoked clean_module() + * to un-register all registered services. + */ + +static void __exit uli526x_cleanup_module(void) +{ + ULI526X_DBUG(0, "uli526x_clean_module() ", debug); + pci_unregister_driver(&uli526x_driver); +} + +module_init(uli526x_init_module); +module_exit(uli526x_cleanup_module); diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/winbond-840.c linux-2.6.12.6/drivers/net/tulip/winbond-840.c --- linux-2.6.12.6.orig/drivers/net/tulip/winbond-840.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/winbond-840.c 2005-10-02 23:47:39.000000000 +0000 @@ -121,6 +121,7 @@ #include #include #include +#include #include #include #include @@ -394,7 +395,7 @@ irq = pdev->irq; - if (pci_set_dma_mask(pdev,0xFFFFffff)) { + if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { printk(KERN_WARNING "Winbond-840: Device %s disabled due to DMA limitations.\n", pci_name(pdev)); return -EIO; @@ -848,7 +849,7 @@ if (skb == NULL) break; skb->dev = dev; /* Mark as being used by this device. */ - np->rx_addr[i] = pci_map_single(np->pci_dev,skb->tail, + np->rx_addr[i] = pci_map_single(np->pci_dev,skb->data, skb->len,PCI_DMA_FROMDEVICE); np->rx_ring[i].buffer1 = np->rx_addr[i]; @@ -1268,7 +1269,7 @@ pci_dma_sync_single_for_cpu(np->pci_dev,np->rx_addr[entry], np->rx_skbuff[entry]->len, PCI_DMA_FROMDEVICE); - eth_copy_and_sum(skb, np->rx_skbuff[entry]->tail, pkt_len, 0); + eth_copy_and_sum(skb, np->rx_skbuff[entry]->data, pkt_len, 0); skb_put(skb, pkt_len); pci_dma_sync_single_for_device(np->pci_dev,np->rx_addr[entry], np->rx_skbuff[entry]->len, @@ -1314,7 +1315,7 @@ break; /* Better luck next round. */ skb->dev = dev; /* Mark as being used by this device. */ np->rx_addr[entry] = pci_map_single(np->pci_dev, - skb->tail, + skb->data, skb->len, PCI_DMA_FROMDEVICE); np->rx_ring[entry].buffer1 = np->rx_addr[entry]; } diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/xircom_cb.c linux-2.6.12.6/drivers/net/tulip/xircom_cb.c --- linux-2.6.12.6.orig/drivers/net/tulip/xircom_cb.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/xircom_cb.c 2005-10-02 23:47:39.000000000 +0000 @@ -117,7 +117,7 @@ static int xircom_close(struct net_device *dev); static void xircom_up(struct xircom_private *card); static struct net_device_stats *xircom_get_stats(struct net_device *dev); -#if CONFIG_NET_POLL_CONTROLLER +#ifdef CONFIG_NET_POLL_CONTROLLER static void xircom_poll_controller(struct net_device *dev); #endif diff -Naur linux-2.6.12.6.orig/drivers/net/tulip/xircom_tulip_cb.c linux-2.6.12.6/drivers/net/tulip/xircom_tulip_cb.c --- linux-2.6.12.6.orig/drivers/net/tulip/xircom_tulip_cb.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/net/tulip/xircom_tulip_cb.c 2005-10-02 23:47:39.000000000 +0000 @@ -899,7 +899,7 @@ break; skb->dev = dev; /* Mark as being used by this device. */ tp->rx_ring[i].status = Rx0DescOwned; /* Owned by Xircom chip */ - tp->rx_ring[i].buffer1 = virt_to_bus(skb->tail); + tp->rx_ring[i].buffer1 = virt_to_bus(skb->data); } tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE); @@ -1291,7 +1291,7 @@ if (skb == NULL) break; skb->dev = dev; /* Mark as being used by this device. */ - tp->rx_ring[entry].buffer1 = virt_to_bus(skb->tail); + tp->rx_ring[entry].buffer1 = virt_to_bus(skb->data); work_done++; } tp->rx_ring[entry].status = Rx0DescOwned; diff -Naur linux-2.6.12.6.orig/drivers/pci/pci.ids linux-2.6.12.6/drivers/pci/pci.ids --- linux-2.6.12.6.orig/drivers/pci/pci.ids 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/pci/pci.ids 2005-10-02 23:47:39.000000000 +0000 @@ -4500,6 +4500,8 @@ 13c2 1011 Technotrend-Budget / Hauppauge WinTV-NOVA-T DVB card 13c2 1013 SATELCO Multimedia DVB 13c2 1102 Technotrend/Hauppauge DVB card rev2.1 + 9730 SAA9730 Integrated Multimedia and Peripheral Controller + 9730 0000 Integrated Multimedia and Peripheral Controller 1132 Mitel Corp. # This is the new official company name. See disclaimer on www.eicon.com for details! 1133 Eicon Networks Corporation @@ -7665,7 +7667,8 @@ 153c ANTAL Electronic 153d FILANET Corp 153e TECHWELL Inc -153f MIPS DENMARK +153f MIPS Technologies, Inc. + 0001 SOC-it 1540 PROVIDEO MULTIMEDIA Co Ltd 1541 MACHONE Communications 1542 VIVID Technology Inc diff -Naur linux-2.6.12.6.orig/drivers/pcmcia/Kconfig linux-2.6.12.6/drivers/pcmcia/Kconfig --- linux-2.6.12.6.orig/drivers/pcmcia/Kconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/pcmcia/Kconfig 2005-10-02 23:47:39.000000000 +0000 @@ -201,3 +201,4 @@ endif # PCCARD endmenu + diff -Naur linux-2.6.12.6.orig/drivers/pcmcia/Makefile linux-2.6.12.6/drivers/pcmcia/Makefile --- linux-2.6.12.6.orig/drivers/pcmcia/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/pcmcia/Makefile 2005-10-02 23:47:39.000000000 +0000 @@ -28,15 +28,21 @@ obj-$(CONFIG_PCMCIA_SA1100) += sa11xx_core.o sa1100_cs.o obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_core.o sa1111_cs.o obj-$(CONFIG_PCMCIA_PXA2XX) += pxa2xx_core.o pxa2xx_cs.o -obj-$(CONFIG_M32R_PCC) += m32r_pcc.o -obj-$(CONFIG_M32R_CFC) += m32r_cfc.o -obj-$(CONFIG_PCMCIA_AU1X00) += au1x00_ss.o obj-$(CONFIG_PCMCIA_VRC4171) += vrc4171_card.o obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o +obj-$(CONFIG_PCMCIA_AU1X00) += au1x00_ss.o + +pcmcia_core-y += cistpl.o rsrc_mgr.o bulkmem.o cs.o socket_sysfs.o +pcmcia_core-$(CONFIG_CARDBUS) += cardbus.o sa11xx_core-y += soc_common.o sa11xx_base.o pxa2xx_core-y += soc_common.o pxa2xx_base.o +sa1111_cs-y += sa1111_generic.o +sa1111_cs-$(CONFIG_ASSABET_NEPONSET) += sa1100_neponset.o +sa1111_cs-$(CONFIG_SA1100_BADGE4) += sa1100_badge4.o +sa1111_cs-$(CONFIG_SA1100_JORNADA720) += sa1100_jornada720.o + au1x00_ss-y += au1000_generic.o au1x00_ss-$(CONFIG_MIPS_PB1000) += au1000_pb1x00.o au1x00_ss-$(CONFIG_MIPS_PB1100) += au1000_pb1x00.o @@ -45,12 +51,7 @@ au1x00_ss-$(CONFIG_MIPS_DB1100) += au1000_db1x00.o au1x00_ss-$(CONFIG_MIPS_DB1500) += au1000_db1x00.o au1x00_ss-$(CONFIG_MIPS_DB1550) += au1000_db1x00.o -au1x00_ss-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o - -sa1111_cs-y += sa1111_generic.o -sa1111_cs-$(CONFIG_ASSABET_NEPONSET) += sa1100_neponset.o -sa1111_cs-$(CONFIG_SA1100_BADGE4) += sa1100_badge4.o -sa1111_cs-$(CONFIG_SA1100_JORNADA720) += sa1100_jornada720.o +au1x00_ss-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o sa1100_cs-y += sa1100_generic.o sa1100_cs-$(CONFIG_SA1100_ASSABET) += sa1100_assabet.o diff -Naur linux-2.6.12.6.orig/drivers/pcmcia/au1000_db1x00.c linux-2.6.12.6/drivers/pcmcia/au1000_db1x00.c --- linux-2.6.12.6.orig/drivers/pcmcia/au1000_db1x00.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/pcmcia/au1000_db1x00.c 2005-10-02 23:47:39.000000000 +0000 @@ -8,7 +8,7 @@ * * Copyright 2004 Pete Popov, updated the driver to 2.6. * Followed the sa11xx API and largely copied many of the hardware - * independent functions. + * independent functions. * * ######################################################################## * @@ -27,9 +27,10 @@ * * ######################################################################## * - * + * */ +#include #include #include #include @@ -71,7 +72,7 @@ au_sync_delay(2); } -static void +static void db1x00_pcmcia_socket_state(struct au1000_pcmcia_socket *skt, struct pcmcia_state *state) { u32 inserted; @@ -95,8 +96,8 @@ return; } - if (inserted) - debug("db1x00 socket %d: inserted %d, vs %d pcmcia %x\n", + if (inserted) + debug("db1x00 socket %d: inserted %d, vs %d pcmcia %x\n", skt->nr, inserted, vs, bcsr->pcmcia); if (inserted) { @@ -120,14 +121,14 @@ * we should turn off power to it */ if ((skt->nr == 0) && (bcsr->pcmcia & BCSR_PCMCIA_PC0RST)) { - bcsr->pcmcia &= ~(BCSR_PCMCIA_PC0RST | + bcsr->pcmcia &= ~(BCSR_PCMCIA_PC0RST | BCSR_PCMCIA_PC0DRVEN | BCSR_PCMCIA_PC0VPP | BCSR_PCMCIA_PC0VCC); au_sync_delay(10); } else if ((skt->nr == 1) && bcsr->pcmcia & BCSR_PCMCIA_PC1RST) { - bcsr->pcmcia &= ~(BCSR_PCMCIA_PC1RST | + bcsr->pcmcia &= ~(BCSR_PCMCIA_PC1RST | BCSR_PCMCIA_PC1DRVEN | BCSR_PCMCIA_PC1VPP | BCSR_PCMCIA_PC1VCC); @@ -137,21 +138,21 @@ state->bvd1=1; state->bvd2=1; - state->wrprot=0; + state->wrprot=0; } -static int +static int db1x00_pcmcia_configure_socket(struct au1000_pcmcia_socket *skt, struct socket_state_t *state) { u16 pwr; int sock = skt->nr; - debug("config_skt %d Vcc %dV Vpp %dV, reset %d\n", - sock, state->Vcc, state->Vpp, + debug("config_skt %d Vcc %dV Vpp %dV, reset %d\n", + sock, state->Vcc, state->Vpp, state->flags & SS_RESET); /* pcmcia reg was set to zero at init time. Be careful when - * initializing a socket not to wipe out the settings of the + * initializing a socket not to wipe out the settings of the * other socket. */ pwr = bcsr->pcmcia; @@ -176,9 +177,9 @@ case 33: default: pwr |= SET_VCC_VPP(0,0,sock); - printk("%s: bad Vcc/Vpp (%d:%d)\n", - __FUNCTION__, - state->Vcc, + printk("%s: bad Vcc/Vpp (%d:%d)\n", + __FUNCTION__, + state->Vcc, state->Vpp); break; } @@ -197,16 +198,16 @@ case 50: default: pwr |= SET_VCC_VPP(0,0,sock); - printk("%s: bad Vcc/Vpp (%d:%d)\n", - __FUNCTION__, - state->Vcc, + printk("%s: bad Vcc/Vpp (%d:%d)\n", + __FUNCTION__, + state->Vcc, state->Vpp); break; } break; default: /* what's this ? */ pwr |= SET_VCC_VPP(0,0,sock); - printk(KERN_ERR "%s: bad Vcc %d\n", + printk(KERN_ERR "%s: bad Vcc %d\n", __FUNCTION__, state->Vcc); break; } @@ -265,7 +266,7 @@ /* nothing to do for now */ } -struct pcmcia_low_level db1x00_pcmcia_ops = { +struct pcmcia_low_level db1x00_pcmcia_ops = { .owner = THIS_MODULE, .hw_init = db1x00_pcmcia_hw_init, diff -Naur linux-2.6.12.6.orig/drivers/pcmcia/au1000_generic.c linux-2.6.12.6/drivers/pcmcia/au1000_generic.c --- linux-2.6.12.6.orig/drivers/pcmcia/au1000_generic.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/pcmcia/au1000_generic.c 2005-10-02 23:47:39.000000000 +0000 @@ -7,8 +7,8 @@ * ppopov@embeddedalley.com or source@mvista.com * * Copyright 2004 Pete Popov, Embedded Alley Solutions, Inc. - * Updated the driver to 2.6. Followed the sa11xx API and largely - * copied many of the hardware independent functions. + * Updated the driver to 2.6. Followed the sa11xx API and largely + * copied many of the hardware independent functions. * * ######################################################################## * @@ -78,7 +78,7 @@ au1x_board_init, }; -static int +static int au1x00_pcmcia_skt_state(struct au1000_pcmcia_socket *skt) { struct pcmcia_state state; @@ -243,7 +243,7 @@ /* au1x00_pcmcia_get_socket() * Implements the get_socket() operation for the in-kernel PCMCIA - * service (formerly SS_GetSocket in Card Services). Not a very + * service (formerly SS_GetSocket in Card Services). Not a very * exciting routine. * * Returns: 0 @@ -342,7 +342,7 @@ map->static_start = skt->phys_mem + map->card_start; } - debug("set_mem_map %d start %08lx card_start %08x\n", + debug("set_mem_map %d start %08lx card_start %08x\n", map->map, map->static_start, map->card_start); return 0; @@ -409,11 +409,11 @@ skt->res_mem.flags = IORESOURCE_MEM; skt->res_attr.name = "attribute"; skt->res_attr.flags = IORESOURCE_MEM; - + /* * PCMCIA client drivers use the inb/outb macros to access the - * IO registers. Since mips_io_port_base is added to the - * access address of the mips implementation of inb/outb, + * IO registers. Since mips_io_port_base is added to the + * access address of the mips implementation of inb/outb, * we need to subtract it here because we want to access the * I/O or MEM address directly, without going through this * "mips_io_port_base" mechanism. @@ -459,7 +459,7 @@ do { struct au1000_pcmcia_socket *skt = PCMCIA_SOCKET(i); - + del_timer_sync(&skt->poll_timer); pcmcia_unregister_socket(&skt->socket); out_err: diff -Naur linux-2.6.12.6.orig/drivers/pcmcia/au1000_generic.h linux-2.6.12.6/drivers/pcmcia/au1000_generic.h --- linux-2.6.12.6.orig/drivers/pcmcia/au1000_generic.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/pcmcia/au1000_generic.h 2005-10-02 23:47:39.000000000 +0000 @@ -22,6 +22,8 @@ #define __ASM_AU1000_PCMCIA_H /* include the world */ +#include + #include #include #include @@ -61,21 +63,21 @@ struct pcmcia_state { unsigned detect: 1, - ready: 1, - wrprot: 1, + ready: 1, + wrprot: 1, bvd1: 1, bvd2: 1, - vs_3v: 1, - vs_Xv: 1; + vs_3v: 1, + vs_Xv: 1; }; struct pcmcia_configure { unsigned sock: 8, - vcc: 8, - vpp: 8, - output: 1, - speaker: 1, - reset: 1; + vcc: 8, + vpp: 8, + output: 1, + speaker: 1, + reset: 1; }; struct pcmcia_irqs { @@ -88,7 +90,7 @@ struct au1000_pcmcia_socket { struct pcmcia_socket socket; - /* + /* * Info from low level handler */ struct device *dev; diff -Naur linux-2.6.12.6.orig/drivers/pcmcia/au1000_pb1x00.c linux-2.6.12.6/drivers/pcmcia/au1000_pb1x00.c --- linux-2.6.12.6.orig/drivers/pcmcia/au1000_pb1x00.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/pcmcia/au1000_pb1x00.c 2005-10-02 23:47:39.000000000 +0000 @@ -21,6 +21,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. */ +#include #include #include #include diff -Naur linux-2.6.12.6.orig/drivers/pcmcia/au1000_xxs1500.c linux-2.6.12.6/drivers/pcmcia/au1000_xxs1500.c --- linux-2.6.12.6.orig/drivers/pcmcia/au1000_xxs1500.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/pcmcia/au1000_xxs1500.c 2005-10-02 23:47:39.000000000 +0000 @@ -23,11 +23,10 @@ * * ######################################################################## * - * + * */ #include #include -#include #include #include #include @@ -74,14 +73,14 @@ au_sync_delay(100); /* assert reset */ - au_writel(au_readl(GPIO2_PINSTATE) | (1<<4)|(1<<20), + au_writel(au_readl(GPIO2_PINSTATE) | (1<<4)|(1<<20), GPIO2_OUTPUT); au_sync_delay(100); return 0; } -static int +static int xxs1500_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state) { u32 inserted; u32 vs; @@ -123,7 +122,7 @@ state->bvd1= gpio2 & (1<<10); state->bvd2 = gpio2 & (1<<11); - state->wrprot=0; + state->wrprot=0; return 1; } @@ -137,13 +136,13 @@ } -static int +static int xxs1500_pcmcia_configure_socket(const struct pcmcia_configure *configure) { if(configure->sock > PCMCIA_MAX_SOCK) return -1; - DEBUG("Vcc %dV Vpp %dV, reset %d\n", + DEBUG("Vcc %dV Vpp %dV, reset %d\n", configure->vcc, configure->vpp, configure->reset); switch(configure->vcc){ @@ -167,22 +166,22 @@ if (!configure->reset) { DEBUG("deassert reset\n"); - au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<4))|(1<<20), + au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<4))|(1<<20), GPIO2_OUTPUT); au_sync_delay(100); - au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<5))|(1<<21), + au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<5))|(1<<21), GPIO2_OUTPUT); } else { DEBUG("assert reset\n"); - au_writel(au_readl(GPIO2_PINSTATE) | (1<<4)|(1<<20), + au_writel(au_readl(GPIO2_PINSTATE) | (1<<4)|(1<<20), GPIO2_OUTPUT); } au_sync_delay(100); return 0; } -struct pcmcia_low_level xxs1500_pcmcia_ops = { +struct pcmcia_low_level xxs1500_pcmcia_ops = { xxs1500_pcmcia_init, xxs1500_pcmcia_shutdown, xxs1500_pcmcia_socket_state, diff -Naur linux-2.6.12.6.orig/drivers/pcmcia/vrc4171_card.c linux-2.6.12.6/drivers/pcmcia/vrc4171_card.c --- linux-2.6.12.6.orig/drivers/pcmcia/vrc4171_card.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/pcmcia/vrc4171_card.c 2005-10-02 23:47:39.000000000 +0000 @@ -1,7 +1,7 @@ /* * vrc4171_card.c, NEC VRC4171 Card Controller driver for Socket Services. * - * Copyright (C) 2003-2005 Yoichi Yuasa + * Copyright (C) 2003 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,6 +26,7 @@ #include #include +#include #include @@ -47,6 +48,7 @@ #define CARD_CONTROLLER_INDEX 0x03e0 #define CARD_CONTROLLER_DATA 0x03e1 +#define CARD_CONTROLLER_SIZE 2 /* Power register */ #define VPP_GET_VCC 0x01 #define POWER_ENABLE 0x10 @@ -67,40 +69,18 @@ #define IRQPM_EN 0x08 #define CLRPMIRQ 0x10 -#define INTERRUPT_STATUS 0x05fa - #define IRQ_A 0x02 - #define IRQ_B 0x04 - -#define CONFIGURATION1 0x05fe - #define SLOTB_CONFIG 0xc000 - #define SLOTB_NONE 0x0000 - #define SLOTB_PCCARD 0x4000 - #define SLOTB_CF 0x8000 - #define SLOTB_FLASHROM 0xc000 - -#define CARD_CONTROLLER_START CARD_CONTROLLER_INDEX -#define CARD_CONTROLLER_END CARD_CONTROLLER_DATA - #define IO_MAX_MAPS 2 #define MEM_MAX_MAPS 5 -typedef enum { +enum { SLOT_PROBE = 0, SLOT_NOPROBE_IO, SLOT_NOPROBE_MEM, - SLOT_NOPROBE_ALL, - SLOT_INITIALIZED, -} vrc4171_slot_t; - -typedef enum { - SLOTB_IS_NONE, - SLOTB_IS_PCCARD, - SLOTB_IS_CF, - SLOTB_IS_FLASHROM, -} vrc4171_slotb_t; + SLOT_NOPROBE_ALL +}; typedef struct vrc4171_socket { - vrc4171_slot_t slot; + int noprobe; struct pcmcia_socket pcmcia_socket; char name[24]; int csc_irq; @@ -108,65 +88,10 @@ } vrc4171_socket_t; static vrc4171_socket_t vrc4171_sockets[CARD_MAX_SLOTS]; -static vrc4171_slotb_t vrc4171_slotb = SLOTB_IS_NONE; -static char vrc4171_card_name[] = "NEC VRC4171 Card Controller"; +static int vrc4171_slotb = SLOTB_IS_NONE; static unsigned int vrc4171_irq; static uint16_t vrc4171_irq_mask = 0xdeb8; -static struct resource vrc4171_card_resource[3] = { - { .name = vrc4171_card_name, - .start = CARD_CONTROLLER_START, - .end = CARD_CONTROLLER_END, - .flags = IORESOURCE_IO, }, - { .name = vrc4171_card_name, - .start = INTERRUPT_STATUS, - .end = INTERRUPT_STATUS, - .flags = IORESOURCE_IO, }, - { .name = vrc4171_card_name, - .start = CONFIGURATION1, - .end = CONFIGURATION1, - .flags = IORESOURCE_IO, }, -}; - -static struct platform_device vrc4171_card_device = { - .name = vrc4171_card_name, - .id = 0, - .num_resources = 3, - .resource = vrc4171_card_resource, -}; - -static inline uint16_t vrc4171_get_irq_status(void) -{ - return inw(INTERRUPT_STATUS); -} - -static inline void vrc4171_set_multifunction_pin(vrc4171_slotb_t config) -{ - uint16_t config1; - - config1 = inw(CONFIGURATION1); - config1 &= ~SLOTB_CONFIG; - - switch (config) { - case SLOTB_IS_NONE: - config1 |= SLOTB_NONE; - break; - case SLOTB_IS_PCCARD: - config1 |= SLOTB_PCCARD; - break; - case SLOTB_IS_CF: - config1 |= SLOTB_CF; - break; - case SLOTB_IS_FLASHROM: - config1 |= SLOTB_FLASHROM; - break; - default: - break; - } - - outw(config1, CONFIGURATION1); -} - static inline uint8_t exca_read_byte(int slot, uint8_t index) { if (slot == CARD_SLOTB) @@ -356,9 +281,9 @@ if (cscint & I365_CSC_STSCHG) state->flags |= SS_STSCHG; } else { - if (cscint & I365_CSC_BVD1) + if (cscint & I365_CSC_BVD1) state->csc_mask |= SS_BATDEAD; - if (cscint & I365_CSC_BVD2) + if (cscint & I365_CSC_BVD2) state->csc_mask |= SS_BATWARN; } if (cscint & I365_CSC_READY) @@ -495,9 +420,9 @@ if (sock == NULL || sock->sock >= CARD_MAX_SLOTS || mem == NULL || mem->map >= MEM_MAX_MAPS || - mem->res->start < CARD_MEM_START || mem->res->start > CARD_MEM_END || - mem->res->end < CARD_MEM_START || mem->res->end > CARD_MEM_END || - mem->res->start > mem->res->end || + mem->sys_start < CARD_MEM_START || mem->sys_start > CARD_MEM_END || + mem->sys_stop < CARD_MEM_START || mem->sys_stop > CARD_MEM_END || + mem->sys_start > mem->sys_stop || mem->card_start > CARD_MAX_MEM_OFFSET || mem->speed > CARD_MAX_MEM_SPEED) return -EINVAL; @@ -511,12 +436,12 @@ exca_write_byte(slot, I365_ADDRWIN, addrwin); } - start = (mem->res->start >> 12) & 0x3fff; + start = (mem->sys_start >> 12) & 0x3fff; if (mem->flags & MAP_16BIT) start |= I365_MEM_16BIT; exca_write_word(slot, I365_MEM(map)+I365_W_START, start); - stop = (mem->res->end >> 12) & 0x3fff; + stop = (mem->sys_stop >> 12) & 0x3fff; switch (mem->speed) { case 0: break; @@ -593,7 +518,7 @@ status = vrc4171_get_irq_status(); if (status & IRQ_A) { socket = &vrc4171_sockets[CARD_SLOTA]; - if (socket->slot == SLOT_INITIALIZED) { + if (socket->noprobe == SLOT_PROBE) { if (status & (1 << socket->csc_irq)) { events = get_events(CARD_SLOTA); if (events != 0) { @@ -606,7 +531,7 @@ if (status & IRQ_B) { socket = &vrc4171_sockets[CARD_SLOTB]; - if (socket->slot == SLOT_INITIALIZED) { + if (socket->noprobe == SLOT_PROBE) { if (status & (1 << socket->csc_irq)) { events = get_events(CARD_SLOTB); if (events != 0) { @@ -633,71 +558,63 @@ vrc4171_irq_mask &= ~(1 << irq); } -static int __devinit vrc4171_add_sockets(void) +static int __devinit vrc4171_add_socket(int slot) { vrc4171_socket_t *socket; - int slot, retval; + int retval; - for (slot = 0; slot < CARD_MAX_SLOTS; slot++) { - if (slot == CARD_SLOTB && vrc4171_slotb == SLOTB_IS_NONE) - continue; + if (slot >= CARD_MAX_SLOTS) + return -EINVAL; - socket = &vrc4171_sockets[slot]; - if (socket->slot != SLOT_PROBE) { - uint8_t addrwin; - - switch (socket->slot) { - case SLOT_NOPROBE_MEM: - addrwin = exca_read_byte(slot, I365_ADDRWIN); - addrwin &= 0x1f; - exca_write_byte(slot, I365_ADDRWIN, addrwin); - break; - case SLOT_NOPROBE_IO: - addrwin = exca_read_byte(slot, I365_ADDRWIN); - addrwin &= 0xc0; - exca_write_byte(slot, I365_ADDRWIN, addrwin); - break; - default: - break; - } + socket = &vrc4171_sockets[slot]; + if (socket->noprobe != SLOT_PROBE) { + uint8_t addrwin; - reserve_using_irq(slot); - continue; + switch (socket->noprobe) { + case SLOT_NOPROBE_MEM: + addrwin = exca_read_byte(slot, I365_ADDRWIN); + addrwin &= 0x1f; + exca_write_byte(slot, I365_ADDRWIN, addrwin); + break; + case SLOT_NOPROBE_IO: + addrwin = exca_read_byte(slot, I365_ADDRWIN); + addrwin &= 0xc0; + exca_write_byte(slot, I365_ADDRWIN, addrwin); + break; + default: + break; } - sprintf(socket->name, "NEC VRC4171 Card Slot %1c", 'A' + slot); - socket->pcmcia_socket.dev.dev = &vrc4171_card_device.dev; - socket->pcmcia_socket.ops = &vrc4171_pccard_operations; - socket->pcmcia_socket.owner = THIS_MODULE; + reserve_using_irq(slot); - retval = pcmcia_register_socket(&socket->pcmcia_socket); - if (retval < 0) - return retval; + return 0; + } - exca_write_byte(slot, I365_ADDRWIN, 0); - exca_write_byte(slot, GLOBAL_CONTROL, 0); + sprintf(socket->name, "NEC VRC4171 Card Slot %1c", 'A' + slot); - socket->slot = SLOT_INITIALIZED; - } + socket->pcmcia_socket.ops = &vrc4171_pccard_operations; + + retval = pcmcia_register_socket(&socket->pcmcia_socket); + if (retval != 0) + return retval; + + exca_write_byte(slot, I365_ADDRWIN, 0); + + exca_write_byte(slot, GLOBAL_CONTROL, 0); return 0; } -static void vrc4171_remove_sockets(void) +static void vrc4171_remove_socket(int slot) { vrc4171_socket_t *socket; - int slot; - for (slot = 0; slot < CARD_MAX_SLOTS; slot++) { - if (slot == CARD_SLOTB && vrc4171_slotb == SLOTB_IS_NONE) - continue; + if (slot >= CARD_MAX_SLOTS) + return; - socket = &vrc4171_sockets[slot]; - if (socket->slot == SLOT_INITIALIZED) - pcmcia_unregister_socket(&socket->pcmcia_socket); + socket = &vrc4171_sockets[slot]; - socket->slot = SLOT_PROBE; - } + pcmcia_unregister_socket(&socket->pcmcia_socket); } static int __devinit vrc4171_card_setup(char *options) @@ -721,13 +638,13 @@ options += 6; if (*options != '\0') { if (strncmp(options, "memnoprobe", 10) == 0) { - vrc4171_sockets[CARD_SLOTA].slot = SLOT_NOPROBE_MEM; + vrc4171_sockets[CARD_SLOTA].noprobe = SLOT_NOPROBE_MEM; options += 10; } else if (strncmp(options, "ionoprobe", 9) == 0) { - vrc4171_sockets[CARD_SLOTA].slot = SLOT_NOPROBE_IO; + vrc4171_sockets[CARD_SLOTA].noprobe = SLOT_NOPROBE_IO; options += 9; } else if ( strncmp(options, "noprobe", 7) == 0) { - vrc4171_sockets[CARD_SLOTA].slot = SLOT_NOPROBE_ALL; + vrc4171_sockets[CARD_SLOTA].noprobe = SLOT_NOPROBE_ALL; options += 7; } @@ -761,11 +678,11 @@ options++; if (strncmp(options, "memnoprobe", 10) == 0) - vrc4171_sockets[CARD_SLOTB].slot = SLOT_NOPROBE_MEM; + vrc4171_sockets[CARD_SLOTB].noprobe = SLOT_NOPROBE_MEM; if (strncmp(options, "ionoprobe", 9) == 0) - vrc4171_sockets[CARD_SLOTB].slot = SLOT_NOPROBE_IO; + vrc4171_sockets[CARD_SLOTB].noprobe = SLOT_NOPROBE_IO; if (strncmp(options, "noprobe", 7) == 0) - vrc4171_sockets[CARD_SLOTB].slot = SLOT_NOPROBE_ALL; + vrc4171_sockets[CARD_SLOTB].noprobe = SLOT_NOPROBE_ALL; } } @@ -774,72 +691,47 @@ __setup("vrc4171_card=", vrc4171_card_setup); -static int vrc4171_card_suspend(struct device *dev, pm_message_t state, u32 level) -{ - int retval = 0; - - if (level == SUSPEND_SAVE_STATE) - retval = pcmcia_socket_dev_suspend(dev, state); - - return retval; -} - -static int vrc4171_card_resume(struct device *dev, u32 level) -{ - int retval = 0; - - if (level == RESUME_RESTORE_STATE) - retval = pcmcia_socket_dev_resume(dev); - - return retval; -} - -static struct device_driver vrc4171_card_driver = { - .name = vrc4171_card_name, - .bus = &platform_bus_type, - .suspend = vrc4171_card_suspend, - .resume = vrc4171_card_resume, -}; - static int __devinit vrc4171_card_init(void) { - int retval; + int retval, slot; - retval = driver_register(&vrc4171_card_driver); - if (retval < 0) - return retval; + vrc4171_set_multifunction_pin(vrc4171_slotb); - retval = platform_device_register(&vrc4171_card_device); - if (retval < 0) { - driver_unregister(&vrc4171_card_driver); - return retval; - } + if (request_region(CARD_CONTROLLER_INDEX, CARD_CONTROLLER_SIZE, + "NEC VRC4171 Card Controller") == NULL) + return -EBUSY; - vrc4171_set_multifunction_pin(vrc4171_slotb); + for (slot = 0; slot < CARD_MAX_SLOTS; slot++) { + if (slot == CARD_SLOTB && vrc4171_slotb == SLOTB_IS_NONE) + break; - retval = vrc4171_add_sockets(); - if (retval == 0) - retval = request_irq(vrc4171_irq, pccard_interrupt, SA_SHIRQ, - vrc4171_card_name, vrc4171_sockets); + retval = vrc4171_add_socket(slot); + if (retval != 0) + return retval; + } + retval = request_irq(vrc4171_irq, pccard_interrupt, SA_SHIRQ, + "NEC VRC4171 Card Controller", vrc4171_sockets); if (retval < 0) { - vrc4171_remove_sockets(); - platform_device_unregister(&vrc4171_card_device); - driver_unregister(&vrc4171_card_driver); + for (slot = 0; slot < CARD_MAX_SLOTS; slot++) + vrc4171_remove_socket(slot); + return retval; } - printk(KERN_INFO "%s, connected to IRQ %d\n", vrc4171_card_driver.name, vrc4171_irq); + printk(KERN_INFO "NEC VRC4171 Card Controller, connected to IRQ %d\n", vrc4171_irq); return 0; } static void __devexit vrc4171_card_exit(void) { - free_irq(vrc4171_irq, vrc4171_sockets); - vrc4171_remove_sockets(); - platform_device_unregister(&vrc4171_card_device); - driver_unregister(&vrc4171_card_driver); + int slot; + + for (slot = 0; slot < CARD_MAX_SLOTS; slot++) + vrc4171_remove_socket(slot); + + release_region(CARD_CONTROLLER_INDEX, CARD_CONTROLLER_SIZE); } module_init(vrc4171_card_init); diff -Naur linux-2.6.12.6.orig/drivers/pcmcia/vrc4173_cardu.c linux-2.6.12.6/drivers/pcmcia/vrc4173_cardu.c --- linux-2.6.12.6.orig/drivers/pcmcia/vrc4173_cardu.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/pcmcia/vrc4173_cardu.c 2005-10-02 23:47:39.000000000 +0000 @@ -295,7 +295,7 @@ map = io->map; if (map > 1) - return -EINVAL; + return -EINVAL; io->start = exca_readw(socket, IO_WIN_SA(map)); io->stop = exca_readw(socket, IO_WIN_EA(map)); @@ -461,7 +461,7 @@ status = exca_readb(socket, IF_STATUS); csc = exca_readb(socket, CARD_SC); - if ((csc & CARD_DT_CHG) && + if ((csc & CARD_DT_CHG) && ((status & (CARD_DETECT1|CARD_DETECT2)) == (CARD_DETECT1|CARD_DETECT2))) events |= SS_DETECT; @@ -614,4 +614,3 @@ module_init(vrc4173_cardu_init); module_exit(vrc4173_cardu_exit); -MODULE_DEVICE_TABLE(pci, vrc4173_cardu_id_table); diff -Naur linux-2.6.12.6.orig/drivers/pcmcia/vrc4173_cardu.h linux-2.6.12.6/drivers/pcmcia/vrc4173_cardu.h --- linux-2.6.12.6.orig/drivers/pcmcia/vrc4173_cardu.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/pcmcia/vrc4173_cardu.h 2005-10-02 23:47:39.000000000 +0000 @@ -136,8 +136,8 @@ #define IO_WIN_CNT 0x007 #define IO_WIN_CNT_MASK(x) (0x03 << ((x) << 2)) - #define IO_WIN_DATA_AUTOSZ(x) (0x02 << ((x) << 2)) - #define IO_WIN_DATA_16BIT(x) (0x01 << ((x) << 2)) + #define IO_WIN_DATA_AUTOSZ(x) (0x02 << ((x) << 2)) + #define IO_WIN_DATA_16BIT(x) (0x01 << ((x) << 2)) #define IO_WIN_SA(x) (0x008 + ((x) << 2)) #define IO_WIN_EA(x) (0x00a + ((x) << 2)) diff -Naur linux-2.6.12.6.orig/drivers/scsi/NCR53C9x.h linux-2.6.12.6/drivers/scsi/NCR53C9x.h --- linux-2.6.12.6.orig/drivers/scsi/NCR53C9x.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/scsi/NCR53C9x.h 2005-10-02 23:47:39.000000000 +0000 @@ -145,12 +145,7 @@ #ifndef MULTIPLE_PAD_SIZES -#ifdef CONFIG_CPU_HAS_WB -#include -#define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0) -#else -#define esp_write(__reg, __val) ((__reg) = (__val)) -#endif +#define esp_write(__reg, __val) do{(__reg) = (__val); iob();} while(0) #define esp_read(__reg) (__reg) struct ESP_regs { diff -Naur linux-2.6.12.6.orig/drivers/scsi/dec_esp.c linux-2.6.12.6/drivers/scsi/dec_esp.c --- linux-2.6.12.6.orig/drivers/scsi/dec_esp.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/scsi/dec_esp.c 2005-10-02 23:47:39.000000000 +0000 @@ -18,7 +18,7 @@ * 20001005 - Initialization fixes for 2.4.0-test9 * Florian Lohoff * - * Copyright (C) 2002, 2003 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki */ #include @@ -41,6 +41,7 @@ #include #include #include +#include #include #define DEC_SCSI_SREG 0 @@ -54,7 +55,7 @@ static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count); static void dma_drain(struct NCR_ESP *esp); -static int dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd *sp); +static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd * sp); static void dma_dump_state(struct NCR_ESP *esp); static void dma_init_read(struct NCR_ESP *esp, u32 vaddress, int length); static void dma_init_write(struct NCR_ESP *esp, u32 vaddress, int length); @@ -63,9 +64,9 @@ static int dma_irq_p(struct NCR_ESP *esp); static int dma_ports_p(struct NCR_ESP *esp); static void dma_setup(struct NCR_ESP *esp, u32 addr, int count, int write); -static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, struct scsi_cmnd * sp); -static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, struct scsi_cmnd * sp); -static void dma_advance_sg(struct scsi_cmnd * sp); +static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp); +static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, Scsi_Cmnd * sp); +static void dma_advance_sg(Scsi_Cmnd * sp); static void pmaz_dma_drain(struct NCR_ESP *esp); static void pmaz_dma_init_read(struct NCR_ESP *esp, u32 vaddress, int length); @@ -73,7 +74,7 @@ static void pmaz_dma_ints_off(struct NCR_ESP *esp); static void pmaz_dma_ints_on(struct NCR_ESP *esp); static void pmaz_dma_setup(struct NCR_ESP *esp, u32 addr, int count, int write); -static void pmaz_dma_mmu_get_scsi_one(struct NCR_ESP *esp, struct scsi_cmnd * sp); +static void pmaz_dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp); #define TC_ESP_RAM_SIZE 0x20000 #define ESP_TGT_DMA_SIZE ((TC_ESP_RAM_SIZE/7) & ~(sizeof(int)-1)) @@ -97,7 +98,7 @@ static irqreturn_t scsi_dma_err_int(int, void *, struct pt_regs *); static irqreturn_t scsi_dma_int(int, void *, struct pt_regs *); -static int dec_esp_detect(struct scsi_host_template * tpnt); +int dec_esp_detect(Scsi_Host_Template * tpnt); static int dec_esp_release(struct Scsi_Host *shost) { @@ -109,9 +110,9 @@ return 0; } -static struct scsi_host_template driver_template = { +static Scsi_Host_Template driver_template = { .proc_name = "dec_esp", - .proc_info = esp_proc_info, + .proc_info = &esp_proc_info, .name = "NCR53C94", .detect = dec_esp_detect, .slave_alloc = esp_slave_alloc, @@ -132,7 +133,7 @@ #include "scsi_module.c" /***************************************************************** Detection */ -static int dec_esp_detect(Scsi_Host_Template * tpnt) +int dec_esp_detect(Scsi_Host_Template * tpnt) { struct NCR_ESP *esp; struct ConfigDev *esp_dev; @@ -183,7 +184,8 @@ esp->dregs = 0; /* ESP register base */ - esp->eregs = (struct ESP_regs *) (system_base + IOASIC_SCSI); + esp->eregs = (void *)CKSEG1ADDR(dec_kn_slot_base + + IOASIC_SCSI); /* Set the command buffer */ esp->esp_command = (volatile unsigned char *) cmd_buffer; @@ -228,10 +230,11 @@ mem_start = get_tc_base_addr(slot); /* Store base addr into esp struct */ - esp->slot = PHYSADDR(mem_start); + esp->slot = mem_start; esp->dregs = 0; - esp->eregs = (struct ESP_regs *) (mem_start + DEC_SCSI_SREG); + esp->eregs = (void *)CKSEG1ADDR(mem_start + + DEC_SCSI_SREG); esp->do_pio_cmds = 1; /* Set the command buffer */ @@ -376,7 +379,7 @@ } } -static int dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd * sp) +static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd * sp) { return sp->SCp.this_residual; } @@ -488,12 +491,12 @@ dma_init_write(esp, addr, count); } -static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, struct scsi_cmnd * sp) +static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp) { sp->SCp.ptr = (char *)virt_to_phys(sp->request_buffer); } -static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, struct scsi_cmnd * sp) +static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, Scsi_Cmnd * sp) { int sz = sp->SCp.buffers_residual; struct scatterlist *sg = sp->SCp.buffer; @@ -505,7 +508,7 @@ sp->SCp.ptr = (char *)(sp->SCp.buffer->dma_address); } -static void dma_advance_sg(struct scsi_cmnd * sp) +static void dma_advance_sg(Scsi_Cmnd * sp) { sp->SCp.ptr = (char *)(sp->SCp.buffer->dma_address); } @@ -513,14 +516,15 @@ static void pmaz_dma_drain(struct NCR_ESP *esp) { memcpy(phys_to_virt(esp_virt_buffer), - (void *)KSEG1ADDR(esp->slot + DEC_SCSI_SRAM + ESP_TGT_DMA_SIZE), - scsi_current_length); + (void *)CKSEG1ADDR(esp->slot + DEC_SCSI_SRAM + + ESP_TGT_DMA_SIZE), + scsi_current_length); } static void pmaz_dma_init_read(struct NCR_ESP *esp, u32 vaddress, int length) { volatile u32 *dmareg = - (volatile u32 *)KSEG1ADDR(esp->slot + DEC_SCSI_DMAREG); + (volatile u32 *)CKSEG1ADDR(esp->slot + DEC_SCSI_DMAREG); if (length > ESP_TGT_DMA_SIZE) length = ESP_TGT_DMA_SIZE; @@ -536,9 +540,10 @@ static void pmaz_dma_init_write(struct NCR_ESP *esp, u32 vaddress, int length) { volatile u32 *dmareg = - (volatile u32 *)KSEG1ADDR(esp->slot + DEC_SCSI_DMAREG); + (volatile u32 *)CKSEG1ADDR(esp->slot + DEC_SCSI_DMAREG); - memcpy((void *)KSEG1ADDR(esp->slot + DEC_SCSI_SRAM + ESP_TGT_DMA_SIZE), + memcpy((void *)CKSEG1ADDR(esp->slot + DEC_SCSI_SRAM + + ESP_TGT_DMA_SIZE), phys_to_virt(vaddress), length); wmb(); @@ -567,7 +572,7 @@ pmaz_dma_init_write(esp, addr, count); } -static void pmaz_dma_mmu_get_scsi_one(struct NCR_ESP *esp, struct scsi_cmnd * sp) +static void pmaz_dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp) { sp->SCp.ptr = (char *)virt_to_phys(sp->request_buffer); } diff -Naur linux-2.6.12.6.orig/drivers/scsi/jazz_esp.c linux-2.6.12.6/drivers/scsi/jazz_esp.c --- linux-2.6.12.6.orig/drivers/scsi/jazz_esp.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/scsi/jazz_esp.c 2005-10-02 23:47:39.000000000 +0000 @@ -28,7 +28,7 @@ #include static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count); -static int dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd *sp); +static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp); static void dma_dump_state(struct NCR_ESP *esp); static void dma_init_read(struct NCR_ESP *esp, __u32 vaddress, int length); static void dma_init_write(struct NCR_ESP *esp, __u32 vaddress, int length); @@ -37,11 +37,11 @@ static int dma_irq_p(struct NCR_ESP *esp); static int dma_ports_p(struct NCR_ESP *esp); static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write); -static void dma_mmu_get_scsi_one (struct NCR_ESP *esp, struct scsi_cmnd *sp); -static void dma_mmu_get_scsi_sgl (struct NCR_ESP *esp, struct scsi_cmnd *sp); -static void dma_mmu_release_scsi_one (struct NCR_ESP *esp, struct scsi_cmnd *sp); -static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, struct scsi_cmnd *sp); -static void dma_advance_sg (struct scsi_cmnd *sp); +static void dma_mmu_get_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp); +static void dma_mmu_get_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp); +static void dma_mmu_release_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp); +static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp); +static void dma_advance_sg (Scsi_Cmnd *sp); static void dma_led_off(struct NCR_ESP *); static void dma_led_on(struct NCR_ESP *); @@ -87,7 +87,7 @@ #include "scsi_module.c" /***************************************************************** Detection */ -static int jazz_esp_detect(struct scsi_host_template *tpnt) +int jazz_esp_detect(Scsi_Host_Template *tpnt) { struct NCR_ESP *esp; struct ConfigDev *esp_dev; @@ -180,7 +180,7 @@ return fifo_count; } -static int dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd *sp) +static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp) { /* * maximum DMA size is 1MB @@ -253,13 +253,13 @@ } } -static void dma_mmu_get_scsi_one (struct NCR_ESP *esp, struct scsi_cmnd *sp) +static void dma_mmu_get_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp) { sp->SCp.have_data_in = vdma_alloc(CPHYSADDR(sp->SCp.buffer), sp->SCp.this_residual); sp->SCp.ptr = (char *)((unsigned long)sp->SCp.have_data_in); } -static void dma_mmu_get_scsi_sgl (struct NCR_ESP *esp, struct scsi_cmnd *sp) +static void dma_mmu_get_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp) { int sz = sp->SCp.buffers_residual; struct scatterlist *sg = (struct scatterlist *) sp->SCp.buffer; @@ -271,12 +271,12 @@ sp->SCp.ptr=(char *)(sp->SCp.buffer->dma_address); } -static void dma_mmu_release_scsi_one (struct NCR_ESP *esp, struct scsi_cmnd *sp) +static void dma_mmu_release_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp) { vdma_free(sp->SCp.have_data_in); } -static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, struct scsi_cmnd *sp) +static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp) { int sz = sp->use_sg - 1; struct scatterlist *sg = (struct scatterlist *)sp->buffer; @@ -287,7 +287,7 @@ } } -static void dma_advance_sg (struct scsi_cmnd *sp) +static void dma_advance_sg (Scsi_Cmnd *sp) { sp->SCp.ptr = (char *)(sp->SCp.buffer->dma_address); } @@ -308,22 +308,3 @@ #endif } -static struct scsi_host_template driver_template = { - .proc_name = "jazz_esp", - .proc_info = esp_proc_info, - .name = "ESP 100/100a/200", - .detect = jazz_esp_detect, - .slave_alloc = esp_slave_alloc, - .slave_destroy = esp_slave_destroy, - .release = jazz_esp_release, - .info = esp_info, - .queuecommand = esp_queue, - .eh_abort_handler = esp_abort, - .eh_bus_reset_handler = esp_reset, - .can_queue = 7, - .this_id = 7, - .sg_tablesize = SG_ALL, - .cmd_per_lun = 1, - .use_clustering = DISABLE_CLUSTERING, -}; -#include "scsi_module.c" diff -Naur linux-2.6.12.6.orig/drivers/scsi/qla1280.c linux-2.6.12.6/drivers/scsi/qla1280.c --- linux-2.6.12.6.orig/drivers/scsi/qla1280.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/scsi/qla1280.c 2005-10-02 23:47:39.000000000 +0000 @@ -996,7 +996,6 @@ break; case ABORT_DEVICE: - ha->flags.in_reset = 1; if (qla1280_verbose) printk(KERN_INFO "scsi(%ld:%d:%d:%d): Queueing abort device " @@ -1010,7 +1009,6 @@ printk(KERN_INFO "scsi(%ld:%d:%d:%d): Queueing device reset " "command.\n", ha->host_no, bus, target, lun); - ha->flags.in_reset = 1; if (qla1280_device_reset(ha, bus, target) == 0) result = SUCCESS; break; @@ -1019,7 +1017,6 @@ if (qla1280_verbose) printk(KERN_INFO "qla1280(%ld:%d): Issuing BUS " "DEVICE RESET\n", ha->host_no, bus); - ha->flags.in_reset = 1; if (qla1280_bus_reset(ha, bus == 0)) result = SUCCESS; @@ -1047,7 +1044,6 @@ if (!list_empty(&ha->done_q)) qla1280_done(ha); - ha->flags.in_reset = 0; /* If we didn't manage to issue the action, or we have no * command to wait for, exit here */ @@ -1245,6 +1241,22 @@ return qla1280_biosparam(disk->device, NULL, disk->capacity, geom); } #endif + +/* disable risc and host interrupts */ +static inline void +qla1280_disable_intrs(struct scsi_qla_host *ha) +{ + WRT_REG_WORD(&ha->iobase->ictrl, 0); + RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ +} + +/* enable risc and host interrupts */ +static inline void +qla1280_enable_intrs(struct scsi_qla_host *ha) +{ + WRT_REG_WORD(&ha->iobase->ictrl, (ISP_EN_INT | ISP_EN_RISC)); + RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ +} /************************************************************************** * qla1280_intr_handler @@ -1266,7 +1278,7 @@ ha->isr_count++; reg = ha->iobase; - WRT_REG_WORD(®->ictrl, 0); /* disable our interrupt. */ + qla1280_disable_intrs(ha); data = qla1280_debounce_register(®->istatus); /* Check for pending interrupts. */ @@ -1279,8 +1291,7 @@ spin_unlock(HOST_LOCK); - /* enable our interrupt. */ - WRT_REG_WORD(®->ictrl, (ISP_EN_INT | ISP_EN_RISC)); + qla1280_enable_intrs(ha); LEAVE_INTR("qla1280_intr_handler"); return IRQ_RETVAL(handled); @@ -1293,7 +1304,7 @@ uint8_t mr; uint16_t mb[MAILBOX_REGISTER_COUNT]; struct nvram *nv; - int status; + int status, lun; nv = &ha->nvram; @@ -1301,24 +1312,38 @@ /* Set Target Parameters. */ mb[0] = MBC_SET_TARGET_PARAMETERS; - mb[1] = (uint16_t) (bus ? target | BIT_7 : target); - mb[1] <<= 8; - - mb[2] = (nv->bus[bus].target[target].parameter.c << 8); + mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8); + mb[2] = nv->bus[bus].target[target].parameter.renegotiate_on_error << 8; + mb[2] |= nv->bus[bus].target[target].parameter.stop_queue_on_check << 9; + mb[2] |= nv->bus[bus].target[target].parameter.auto_request_sense << 10; + mb[2] |= nv->bus[bus].target[target].parameter.tag_queuing << 11; + mb[2] |= nv->bus[bus].target[target].parameter.enable_sync << 12; + mb[2] |= nv->bus[bus].target[target].parameter.enable_wide << 13; + mb[2] |= nv->bus[bus].target[target].parameter.parity_checking << 14; + mb[2] |= nv->bus[bus].target[target].parameter.disconnect_allowed << 15; if (IS_ISP1x160(ha)) { mb[2] |= nv->bus[bus].target[target].ppr_1x160.flags.enable_ppr << 5; - mb[3] = (nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8) | - nv->bus[bus].target[target].sync_period; + mb[3] = (nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8); mb[6] = (nv->bus[bus].target[target].ppr_1x160.flags.ppr_options << 8) | nv->bus[bus].target[target].ppr_1x160.flags.ppr_bus_width; mr |= BIT_6; } else { - mb[3] = (nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8) | - nv->bus[bus].target[target].sync_period; + mb[3] = (nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8); } + mb[3] |= nv->bus[bus].target[target].sync_period; - status = qla1280_mailbox_command(ha, mr, &mb[0]); + status = qla1280_mailbox_command(ha, mr, mb); + + /* Set Device Queue Parameters. */ + for (lun = 0; lun < MAX_LUNS; lun++) { + mb[0] = MBC_SET_DEVICE_QUEUE; + mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8); + mb[1] |= lun; + mb[2] = nv->bus[bus].max_queue_depth; + mb[3] = nv->bus[bus].target[target].execution_throttle; + status |= qla1280_mailbox_command(ha, 0x0f, mb); + } if (status) printk(KERN_WARNING "scsi(%ld:%i:%i): " @@ -1365,19 +1390,19 @@ } #if LINUX_VERSION_CODE > 0x020500 - nv->bus[bus].target[target].parameter.f.enable_sync = device->sdtr; - nv->bus[bus].target[target].parameter.f.enable_wide = device->wdtr; + nv->bus[bus].target[target].parameter.enable_sync = device->sdtr; + nv->bus[bus].target[target].parameter.enable_wide = device->wdtr; nv->bus[bus].target[target].ppr_1x160.flags.enable_ppr = device->ppr; #endif if (driver_setup.no_sync || (driver_setup.sync_mask && (~driver_setup.sync_mask & (1 << target)))) - nv->bus[bus].target[target].parameter.f.enable_sync = 0; + nv->bus[bus].target[target].parameter.enable_sync = 0; if (driver_setup.no_wide || (driver_setup.wide_mask && (~driver_setup.wide_mask & (1 << target)))) - nv->bus[bus].target[target].parameter.f.enable_wide = 0; + nv->bus[bus].target[target].parameter.enable_wide = 0; if (IS_ISP1x160(ha)) { if (driver_setup.no_ppr || (driver_setup.ppr_mask && @@ -1386,7 +1411,7 @@ } spin_lock_irqsave(HOST_LOCK, flags); - if (nv->bus[bus].target[target].parameter.f.enable_sync) + if (nv->bus[bus].target[target].parameter.enable_sync) status = qla1280_set_target_parameters(ha, bus, target); qla1280_get_target_parameters(ha, device); spin_unlock_irqrestore(HOST_LOCK, flags); @@ -1424,7 +1449,6 @@ * * Input: * ha = adapter block pointer. - * done_q = done queue. */ static void qla1280_done(struct scsi_qla_host *ha) @@ -1498,7 +1522,7 @@ int host_status = DID_ERROR; uint16_t comp_status = le16_to_cpu(sts->comp_status); uint16_t state_flags = le16_to_cpu(sts->state_flags); - uint16_t residual_length = le16_to_cpu(sts->residual_length); + uint16_t residual_length = le32_to_cpu(sts->residual_length); uint16_t scsi_status = le16_to_cpu(sts->scsi_status); #if DEBUG_QLA1280_INTR static char *reason[] = { @@ -1558,7 +1582,7 @@ case CS_DATA_OVERRUN: dprintk(2, "Data overrun 0x%x\n", residual_length); - dprintk(2, "qla1280_isr: response packet data\n"); + dprintk(2, "qla1280_return_status: response packet data\n"); qla1280_dump_buffer(2, (char *)sts, RESPONSE_ENTRY_SIZE); host_status = DID_ERROR; break; @@ -1593,40 +1617,6 @@ /* QLogic ISP1280 Hardware Support Functions. */ /****************************************************************************/ - /* - * qla2100_enable_intrs - * qla2100_disable_intrs - * - * Input: - * ha = adapter block pointer. - * - * Returns: - * None - */ -static inline void -qla1280_enable_intrs(struct scsi_qla_host *ha) -{ - struct device_reg __iomem *reg; - - reg = ha->iobase; - /* enable risc and host interrupts */ - WRT_REG_WORD(®->ictrl, (ISP_EN_INT | ISP_EN_RISC)); - RD_REG_WORD(®->ictrl); /* PCI Posted Write flush */ - ha->flags.ints_enabled = 1; -} - -static inline void -qla1280_disable_intrs(struct scsi_qla_host *ha) -{ - struct device_reg __iomem *reg; - - reg = ha->iobase; - /* disable risc and host interrupts */ - WRT_REG_WORD(®->ictrl, 0); - RD_REG_WORD(®->ictrl); /* PCI Posted Write flush */ - ha->flags.ints_enabled = 0; -} - /* * qla1280_initialize_adapter * Initialize board. @@ -1655,7 +1645,6 @@ ha->flags.reset_active = 0; ha->flags.abort_isp_active = 0; - ha->flags.ints_enabled = 0; #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) if (ia64_platform_is("sn2")) { printk(KERN_INFO "scsi(%li): Enabling SN2 PCI DMA " @@ -1734,69 +1723,6 @@ return status; } - -/* - * ISP Firmware Test - * Checks if present version of RISC firmware is older than - * driver firmware. - * - * Input: - * ha = adapter block pointer. - * - * Returns: - * 0 = firmware does not need to be loaded. - */ -static int -qla1280_isp_firmware(struct scsi_qla_host *ha) -{ - struct nvram *nv = (struct nvram *) ha->response_ring; - int status = 0; /* dg 2/27 always loads RISC */ - uint16_t mb[MAILBOX_REGISTER_COUNT]; - - ENTER("qla1280_isp_firmware"); - - dprintk(1, "scsi(%li): Determining if RISC is loaded\n", ha->host_no); - - /* Bad NVRAM data, load RISC code. */ - if (!ha->nvram_valid) { - ha->flags.disable_risc_code_load = 0; - } else - ha->flags.disable_risc_code_load = - nv->cntr_flags_1.disable_loading_risc_code; - - if (ha->flags.disable_risc_code_load) { - dprintk(3, "qla1280_isp_firmware: Telling RISC to verify " - "checksum of loaded BIOS code.\n"); - - /* Verify checksum of loaded RISC code. */ - mb[0] = MBC_VERIFY_CHECKSUM; - /* mb[1] = ql12_risc_code_addr01; */ - mb[1] = *ql1280_board_tbl[ha->devnum].fwstart; - - if (!(status = - qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]))) { - /* Start firmware execution. */ - dprintk(3, "qla1280_isp_firmware: Startng F/W " - "execution.\n"); - - mb[0] = MBC_EXECUTE_FIRMWARE; - /* mb[1] = ql12_risc_code_addr01; */ - mb[1] = *ql1280_board_tbl[ha->devnum].fwstart; - qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); - } else - printk(KERN_INFO "qla1280: RISC checksum failed.\n"); - } else { - dprintk(1, "qla1280: NVRAM configured to load RISC load.\n"); - status = 1; - } - - if (status) - dprintk(2, "qla1280_isp_firmware: **** Load RISC code ****\n"); - - LEAVE("qla1280_isp_firmware"); - return status; -} - /* * Chip diagnostics * Test chip for proper operation. @@ -1982,7 +1908,7 @@ "%d,%d(0x%x)\n", risc_code_address, cnt, num, risc_address); for(i = 0; i < cnt; i++) - ((uint16_t *)ha->request_ring)[i] = + ((__le16 *)ha->request_ring)[i] = cpu_to_le16(risc_code_address[i]); mb[0] = MBC_LOAD_RAM; @@ -2061,7 +1987,7 @@ mb[1] = *ql1280_board_tbl[ha->devnum].fwstart; err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); if (err) { - printk(KERN_ERR "scsi(%li): Failed checksum\n", ha->host_no); + printk(KERN_ERR "scsi(%li): RISC checksum failed.\n", ha->host_no); return err; } @@ -2081,14 +2007,7 @@ static int qla1280_load_firmware(struct scsi_qla_host *ha) { - int err = -ENODEV; - - /* If firmware needs to be loaded */ - if (!qla1280_isp_firmware(ha)) { - printk(KERN_ERR "scsi(%li): isp_firmware() failed!\n", - ha->host_no); - goto out; - } + int err; err = qla1280_chip_diag(ha); if (err) @@ -2222,17 +2141,17 @@ { struct nvram *nv = &ha->nvram; - nv->bus[bus].target[target].parameter.f.renegotiate_on_error = 1; - nv->bus[bus].target[target].parameter.f.auto_request_sense = 1; - nv->bus[bus].target[target].parameter.f.tag_queuing = 1; - nv->bus[bus].target[target].parameter.f.enable_sync = 1; + nv->bus[bus].target[target].parameter.renegotiate_on_error = 1; + nv->bus[bus].target[target].parameter.auto_request_sense = 1; + nv->bus[bus].target[target].parameter.tag_queuing = 1; + nv->bus[bus].target[target].parameter.enable_sync = 1; #if 1 /* Some SCSI Processors do not seem to like this */ - nv->bus[bus].target[target].parameter.f.enable_wide = 1; + nv->bus[bus].target[target].parameter.enable_wide = 1; #endif - nv->bus[bus].target[target].parameter.f.parity_checking = 1; - nv->bus[bus].target[target].parameter.f.disconnect_allowed = 1; nv->bus[bus].target[target].execution_throttle = nv->bus[bus].max_queue_depth - 1; + nv->bus[bus].target[target].parameter.parity_checking = 1; + nv->bus[bus].target[target].parameter.disconnect_allowed = 1; if (IS_ISP1x160(ha)) { nv->bus[bus].target[target].flags.flags1x160.device_enable = 1; @@ -2260,9 +2179,9 @@ /* nv->cntr_flags_1.disable_loading_risc_code = 1; */ nv->firmware_feature.f.enable_fast_posting = 1; nv->firmware_feature.f.disable_synchronous_backoff = 1; - nv->termination.f.scsi_bus_0_control = 3; - nv->termination.f.scsi_bus_1_control = 3; - nv->termination.f.auto_term_support = 1; + nv->termination.scsi_bus_0_control = 3; + nv->termination.scsi_bus_1_control = 3; + nv->termination.auto_term_support = 1; /* * Set default FIFO magic - What appropriate values would be here @@ -2272,7 +2191,12 @@ * header file provided by QLogic seems to be bogus or incomplete * at best. */ - nv->isp_config.c = ISP_CFG1_BENAB|ISP_CFG1_F128; + nv->isp_config.burst_enable = 1; + if (IS_ISP1040(ha)) + nv->isp_config.fifo_threshold |= 3; + else + nv->isp_config.fifo_threshold |= 4; + if (IS_ISP1x160(ha)) nv->isp_parameter = 0x01; /* fast memory enable */ @@ -2303,66 +2227,53 @@ struct nvram *nv = &ha->nvram; uint16_t mb[MAILBOX_REGISTER_COUNT]; int status, lun; + uint16_t flag; /* Set Target Parameters. */ mb[0] = MBC_SET_TARGET_PARAMETERS; - mb[1] = (uint16_t) (bus ? target | BIT_7 : target); - mb[1] <<= 8; - - /* - * Do not enable wide, sync, and ppr for the initial - * INQUIRY run. We enable this later if we determine - * the target actually supports it. - */ - nv->bus[bus].target[target].parameter.f. - auto_request_sense = 1; - nv->bus[bus].target[target].parameter.f. - stop_queue_on_check = 0; - - if (IS_ISP1x160(ha)) - nv->bus[bus].target[target].ppr_1x160. - flags.enable_ppr = 0; + mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8); /* - * No sync, wide, etc. while probing + * Do not enable sync and ppr for the initial INQUIRY run. We + * enable this later if we determine the target actually + * supports it. */ - mb[2] = (nv->bus[bus].target[target].parameter.c << 8) & - ~(TP_SYNC /*| TP_WIDE | TP_PPR*/); + mb[2] = (TP_RENEGOTIATE | TP_AUTO_REQUEST_SENSE | TP_TAGGED_QUEUE + | TP_WIDE | TP_PARITY | TP_DISCONNECT); if (IS_ISP1x160(ha)) mb[3] = nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8; else mb[3] = nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8; mb[3] |= nv->bus[bus].target[target].sync_period; - - status = qla1280_mailbox_command(ha, BIT_3 | BIT_2 | BIT_1 | BIT_0, &mb[0]); + status = qla1280_mailbox_command(ha, 0x0f, mb); /* Save Tag queuing enable flag. */ - mb[0] = BIT_0 << target; - if (nv->bus[bus].target[target].parameter.f.tag_queuing) - ha->bus_settings[bus].qtag_enables |= mb[0]; + flag = (BIT_0 << target) & mb[0]; + if (nv->bus[bus].target[target].parameter.tag_queuing) + ha->bus_settings[bus].qtag_enables |= flag; /* Save Device enable flag. */ if (IS_ISP1x160(ha)) { if (nv->bus[bus].target[target].flags.flags1x160.device_enable) - ha->bus_settings[bus].device_enables |= mb[0]; + ha->bus_settings[bus].device_enables |= flag; ha->bus_settings[bus].lun_disables |= 0; } else { if (nv->bus[bus].target[target].flags.flags1x80.device_enable) - ha->bus_settings[bus].device_enables |= mb[0]; + ha->bus_settings[bus].device_enables |= flag; /* Save LUN disable flag. */ if (nv->bus[bus].target[target].flags.flags1x80.lun_disable) - ha->bus_settings[bus].lun_disables |= mb[0]; + ha->bus_settings[bus].lun_disables |= flag; } /* Set Device Queue Parameters. */ for (lun = 0; lun < MAX_LUNS; lun++) { mb[0] = MBC_SET_DEVICE_QUEUE; - mb[1] = (uint16_t)(bus ? target | BIT_7 : target); - mb[1] = mb[1] << 8 | lun; + mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8); + mb[1] |= lun; mb[2] = nv->bus[bus].max_queue_depth; mb[3] = nv->bus[bus].target[target].execution_throttle; - status |= qla1280_mailbox_command(ha, 0x0f, &mb[0]); + status |= qla1280_mailbox_command(ha, 0x0f, mb); } return status; @@ -2407,7 +2318,6 @@ struct nvram *nv = &ha->nvram; int bus, target, status = 0; uint16_t mb[MAILBOX_REGISTER_COUNT]; - uint16_t mask; ENTER("qla1280_nvram_config"); @@ -2415,7 +2325,7 @@ /* Always force AUTO sense for LINUX SCSI */ for (bus = 0; bus < MAX_BUSES; bus++) for (target = 0; target < MAX_TARGETS; target++) { - nv->bus[bus].target[target].parameter.f. + nv->bus[bus].target[target].parameter. auto_request_sense = 1; } } else { @@ -2433,31 +2343,40 @@ hwrev = RD_REG_WORD(®->cfg_0) & ISP_CFG0_HWMSK; - cfg1 = RD_REG_WORD(®->cfg_1); + cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); cdma_conf = RD_REG_WORD(®->cdma_cfg); ddma_conf = RD_REG_WORD(®->ddma_cfg); /* Busted fifo, says mjacob. */ - if (hwrev == ISP_CFG0_1040A) - WRT_REG_WORD(®->cfg_1, cfg1 | ISP_CFG1_F64); - else - WRT_REG_WORD(®->cfg_1, cfg1 | ISP_CFG1_F64 | ISP_CFG1_BENAB); + if (hwrev != ISP_CFG0_1040A) + cfg1 |= nv->isp_config.fifo_threshold << 4; + + cfg1 |= nv->isp_config.burst_enable << 2; + WRT_REG_WORD(®->cfg_1, cfg1); WRT_REG_WORD(®->cdma_cfg, cdma_conf | CDMA_CONF_BENAB); WRT_REG_WORD(®->ddma_cfg, cdma_conf | DDMA_CONF_BENAB); } else { + uint16_t cfg1, term; + /* Set ISP hardware DMA burst */ - mb[0] = nv->isp_config.c; + cfg1 = nv->isp_config.fifo_threshold << 4; + cfg1 |= nv->isp_config.burst_enable << 2; /* Enable DMA arbitration on dual channel controllers */ if (ha->ports > 1) - mb[0] |= BIT_13; - WRT_REG_WORD(®->cfg_1, mb[0]); + cfg1 |= BIT_13; + WRT_REG_WORD(®->cfg_1, cfg1); /* Set SCSI termination. */ - WRT_REG_WORD(®->gpio_enable, (BIT_3 + BIT_2 + BIT_1 + BIT_0)); - mb[0] = nv->termination.c & (BIT_3 + BIT_2 + BIT_1 + BIT_0); - WRT_REG_WORD(®->gpio_data, mb[0]); + WRT_REG_WORD(®->gpio_enable, + BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); + term = nv->termination.scsi_bus_1_control; + term |= nv->termination.scsi_bus_0_control << 2; + term |= nv->termination.auto_term_support << 7; + RD_REG_WORD(®->id_l); /* Flush PCI write */ + WRT_REG_WORD(®->gpio_data, term); } + RD_REG_WORD(®->id_l); /* Flush PCI write */ /* ISP parameter word. */ mb[0] = MBC_SET_SYSTEM_PARAMETER; @@ -2473,16 +2392,17 @@ /* Firmware feature word. */ mb[0] = MBC_SET_FIRMWARE_FEATURES; - mask = BIT_5 | BIT_1 | BIT_0; - mb[1] = le16_to_cpu(nv->firmware_feature.w) & (mask); + mb[1] = nv->firmware_feature.f.enable_fast_posting; + mb[1] |= nv->firmware_feature.f.report_lvd_bus_transition << 1; + mb[1] |= nv->firmware_feature.f.disable_synchronous_backoff << 5; #if defined(CONFIG_IA64_GENERIC) || defined (CONFIG_IA64_SGI_SN2) if (ia64_platform_is("sn2")) { printk(KERN_INFO "scsi(%li): Enabling SN2 PCI DMA " "workaround\n", ha->host_no); - mb[1] |= BIT_9; + mb[1] |= nv->firmware_feature.f.unused_9 << 9; /* XXX */ } #endif - status |= qla1280_mailbox_command(ha, mask, &mb[0]); + status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); /* Retry count and delay. */ mb[0] = MBC_SET_RETRY_COUNT; @@ -2511,27 +2431,27 @@ mb[2] |= BIT_5; if (nv->bus[1].config_2.data_line_active_negation) mb[2] |= BIT_4; - status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]); + status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb); mb[0] = MBC_SET_DATA_OVERRUN_RECOVERY; mb[1] = 2; /* Reset SCSI bus and return all outstanding IO */ - status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); + status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); /* thingy */ mb[0] = MBC_SET_PCI_CONTROL; - mb[1] = 2; /* Data DMA Channel Burst Enable */ - mb[2] = 2; /* Command DMA Channel Burst Enable */ - status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]); + mb[1] = BIT_1; /* Data DMA Channel Burst Enable */ + mb[2] = BIT_1; /* Command DMA Channel Burst Enable */ + status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb); mb[0] = MBC_SET_TAG_AGE_LIMIT; mb[1] = 8; - status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); + status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); /* Selection timeout. */ mb[0] = MBC_SET_SELECTION_TIMEOUT; mb[1] = nv->bus[0].selection_timeout; mb[2] = nv->bus[1].selection_timeout; - status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]); + status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb); for (bus = 0; bus < ha->ports; bus++) status |= qla1280_config_bus(ha, bus); @@ -3042,7 +2962,7 @@ struct scsi_cmnd *cmd = sp->cmd; cmd_a64_entry_t *pkt; struct scatterlist *sg = NULL; - u32 *dword_ptr; + __le32 *dword_ptr; dma_addr_t dma_handle; int status = 0; int cnt; @@ -3080,10 +3000,13 @@ REQUEST_ENTRY_CNT - (ha->req_ring_index - cnt); } + dprintk(3, "Number of free entries=(%d) seg_cnt=0x%x\n", + ha->req_q_cnt, seg_cnt); + /* If room for request in request ring. */ if ((req_cnt + 2) >= ha->req_q_cnt) { status = 1; - dprintk(2, "qla1280_64bit_start_scsi: in-ptr=0x%x req_q_cnt=" + dprintk(2, "qla1280_start_scsi: in-ptr=0x%x req_q_cnt=" "0x%xreq_cnt=0x%x", ha->req_ring_index, ha->req_q_cnt, req_cnt); goto out; @@ -3095,7 +3018,7 @@ if (cnt >= MAX_OUTSTANDING_COMMANDS) { status = 1; - dprintk(2, "qla1280_64bit_start_scsi: NO ROOM IN " + dprintk(2, "qla1280_start_scsi: NO ROOM IN " "OUTSTANDING ARRAY, req_q_cnt=0x%x", ha->req_q_cnt); goto out; } @@ -3104,7 +3027,7 @@ ha->req_q_cnt -= req_cnt; CMD_HANDLE(sp->cmd) = (unsigned char *)(unsigned long)(cnt + 1); - dprintk(2, "64bit_start: cmd=%p sp=%p CDB=%xm, handle %lx\n", cmd, sp, + dprintk(2, "start: cmd=%p sp=%p CDB=%xm, handle %lx\n", cmd, sp, cmd->cmnd[0], (long)CMD_HANDLE(sp->cmd)); dprintk(2, " bus %i, target %i, lun %i\n", SCSI_BUS_32(cmd), SCSI_TCN_32(cmd), SCSI_LUN_32(cmd)); @@ -3326,7 +3249,7 @@ struct scsi_cmnd *cmd = sp->cmd; struct cmd_entry *pkt; struct scatterlist *sg = NULL; - uint32_t *dword_ptr; + __le32 *dword_ptr; int status = 0; int cnt; int req_cnt; @@ -3969,21 +3892,21 @@ result = cmd->request_buffer; n = &ha->nvram; - n->bus[bus].target[target].parameter.f.enable_wide = 0; - n->bus[bus].target[target].parameter.f.enable_sync = 0; + n->bus[bus].target[target].parameter.enable_wide = 0; + n->bus[bus].target[target].parameter.enable_sync = 0; n->bus[bus].target[target].ppr_1x160.flags.enable_ppr = 0; if (result[7] & 0x60) - n->bus[bus].target[target].parameter.f.enable_wide = 1; + n->bus[bus].target[target].parameter.enable_wide = 1; if (result[7] & 0x10) - n->bus[bus].target[target].parameter.f.enable_sync = 1; + n->bus[bus].target[target].parameter.enable_sync = 1; if ((result[2] >= 3) && (result[4] + 5 > 56) && (result[56] & 0x4)) n->bus[bus].target[target].ppr_1x160.flags.enable_ppr = 1; dprintk(2, "get_target_options(): wide %i, sync %i, ppr %i\n", - n->bus[bus].target[target].parameter.f.enable_wide, - n->bus[bus].target[target].parameter.f.enable_sync, + n->bus[bus].target[target].parameter.enable_wide, + n->bus[bus].target[target].parameter.enable_sync, n->bus[bus].target[target].ppr_1x160.flags.enable_ppr); } #endif @@ -4039,8 +3962,8 @@ } /* Target busy */ - if (scsi_status & SS_BUSY_CONDITION && - scsi_status != SS_RESERVE_CONFLICT) { + if (scsi_status & SAM_STAT_BUSY && + scsi_status != SAM_STAT_RESERVATION_CONFLICT) { CMD_RESULT(cmd) = DID_BUS_BUSY << 16 | (scsi_status & 0xff); } else { @@ -4048,7 +3971,7 @@ /* Save ISP completion status */ CMD_RESULT(cmd) = qla1280_return_status(pkt, cmd); - if (scsi_status & SS_CHECK_CONDITION) { + if (scsi_status & SAM_STAT_CHECK_CONDITION) { if (comp_status != CS_ARS_FAILED) { uint16_t req_sense_length = le16_to_cpu(pkt->req_sense_length); @@ -4627,7 +4550,7 @@ if (pci_set_dma_mask(ha->pdev, (dma_addr_t) ~ 0ULL)) { if (pci_set_dma_mask(ha->pdev, 0xffffffff)) { printk(KERN_WARNING "scsi(%li): Unable to set a " - " suitable DMA mask - aboring\n", ha->host_no); + "suitable DMA mask - aborting\n", ha->host_no); error = -ENODEV; goto error_free_irq; } @@ -4637,14 +4560,14 @@ #else if (pci_set_dma_mask(ha->pdev, 0xffffffff)) { printk(KERN_WARNING "scsi(%li): Unable to set a " - " suitable DMA mask - aboring\n", ha->host_no); + "suitable DMA mask - aborting\n", ha->host_no); error = -ENODEV; goto error_free_irq; } #endif ha->request_ring = pci_alloc_consistent(ha->pdev, - ((REQUEST_ENTRY_CNT + 1) * (sizeof(request_t))), + ((REQUEST_ENTRY_CNT + 1) * sizeof(request_t)), &ha->request_dma); if (!ha->request_ring) { printk(KERN_INFO "qla1280: Failed to get request memory\n"); @@ -4652,7 +4575,7 @@ } ha->response_ring = pci_alloc_consistent(ha->pdev, - ((RESPONSE_ENTRY_CNT + 1) * (sizeof(struct response))), + ((RESPONSE_ENTRY_CNT + 1) * sizeof(struct response)), &ha->response_dma); if (!ha->response_ring) { printk(KERN_INFO "qla1280: Failed to get response memory\n"); @@ -4735,7 +4658,7 @@ #if LINUX_VERSION_CODE >= 0x020600 error_disable_adapter: - WRT_REG_WORD(&ha->iobase->ictrl, 0); + qla1280_disable_intrs(ha); #endif error_free_irq: free_irq(pdev->irq, ha); @@ -4747,11 +4670,11 @@ #endif error_free_response_ring: pci_free_consistent(ha->pdev, - ((RESPONSE_ENTRY_CNT + 1) * (sizeof(struct response))), + ((RESPONSE_ENTRY_CNT + 1) * sizeof(struct response)), ha->response_ring, ha->response_dma); error_free_request_ring: pci_free_consistent(ha->pdev, - ((REQUEST_ENTRY_CNT + 1) * (sizeof(request_t))), + ((REQUEST_ENTRY_CNT + 1) * sizeof(request_t)), ha->request_ring, ha->request_dma); error_put_host: scsi_host_put(host); @@ -4772,7 +4695,7 @@ scsi_remove_host(host); #endif - WRT_REG_WORD(&ha->iobase->ictrl, 0); + qla1280_disable_intrs(ha); free_irq(pdev->irq, ha); diff -Naur linux-2.6.12.6.orig/drivers/scsi/qla1280.h linux-2.6.12.6/drivers/scsi/qla1280.h --- linux-2.6.12.6.orig/drivers/scsi/qla1280.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/scsi/qla1280.h 2005-10-02 23:47:39.000000000 +0000 @@ -94,9 +94,6 @@ #define REQUEST_ENTRY_CNT 256 /* Number of request entries. */ #define RESPONSE_ENTRY_CNT 16 /* Number of response entries. */ -/* Number of segments 1 - 65535 */ -#define SG_SEGMENTS 32 /* Cmd entry + 6 continuations */ - /* * SCSI Request Block structure (sp) that is placed * on cmd->SCp location of every I/O @@ -378,29 +375,23 @@ uint16_t unused_12; /* 12, 13 */ uint16_t unused_14; /* 14, 15 */ - union { - uint8_t c; - struct { - uint8_t reserved:2; - uint8_t burst_enable:1; - uint8_t reserved_1:1; - uint8_t fifo_threshold:4; - } f; + struct { + uint8_t reserved:2; + uint8_t burst_enable:1; + uint8_t reserved_1:1; + uint8_t fifo_threshold:4; } isp_config; /* 16 */ /* Termination * 0 = Disable, 1 = high only, 3 = Auto term */ - union { - uint8_t c; - struct { - uint8_t scsi_bus_1_control:2; - uint8_t scsi_bus_0_control:2; - uint8_t unused_0:1; - uint8_t unused_1:1; - uint8_t unused_2:1; - uint8_t auto_term_support:1; - } f; + struct { + uint8_t scsi_bus_1_control:2; + uint8_t scsi_bus_0_control:2; + uint8_t unused_0:1; + uint8_t unused_1:1; + uint8_t unused_2:1; + uint8_t auto_term_support:1; } termination; /* 17 */ uint16_t isp_parameter; /* 18, 19 */ @@ -460,18 +451,15 @@ uint16_t unused_38; /* 38, 39 */ struct { - union { - uint8_t c; - struct { - uint8_t renegotiate_on_error:1; - uint8_t stop_queue_on_check:1; - uint8_t auto_request_sense:1; - uint8_t tag_queuing:1; - uint8_t enable_sync:1; - uint8_t enable_wide:1; - uint8_t parity_checking:1; - uint8_t disconnect_allowed:1; - } f; + struct { + uint8_t renegotiate_on_error:1; + uint8_t stop_queue_on_check:1; + uint8_t auto_request_sense:1; + uint8_t tag_queuing:1; + uint8_t enable_sync:1; + uint8_t enable_wide:1; + uint8_t parity_checking:1; + uint8_t disconnect_allowed:1; } parameter; /* 40 */ uint8_t execution_throttle; /* 41 */ @@ -528,23 +516,23 @@ uint8_t entry_count; /* Entry count. */ uint8_t sys_define; /* System defined. */ uint8_t entry_status; /* Entry Status. */ - uint32_t handle; /* System handle. */ + __le32 handle; /* System handle. */ uint8_t lun; /* SCSI LUN */ uint8_t target; /* SCSI ID */ - uint16_t cdb_len; /* SCSI command length. */ - uint16_t control_flags; /* Control flags. */ - uint16_t reserved; - uint16_t timeout; /* Command timeout. */ - uint16_t dseg_count; /* Data segment count. */ + __le16 cdb_len; /* SCSI command length. */ + __le16 control_flags; /* Control flags. */ + __le16 reserved; + __le16 timeout; /* Command timeout. */ + __le16 dseg_count; /* Data segment count. */ uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ - uint32_t dseg_0_address; /* Data segment 0 address. */ - uint32_t dseg_0_length; /* Data segment 0 length. */ - uint32_t dseg_1_address; /* Data segment 1 address. */ - uint32_t dseg_1_length; /* Data segment 1 length. */ - uint32_t dseg_2_address; /* Data segment 2 address. */ - uint32_t dseg_2_length; /* Data segment 2 length. */ - uint32_t dseg_3_address; /* Data segment 3 address. */ - uint32_t dseg_3_length; /* Data segment 3 length. */ + __le32 dseg_0_address; /* Data segment 0 address. */ + __le32 dseg_0_length; /* Data segment 0 length. */ + __le32 dseg_1_address; /* Data segment 1 address. */ + __le32 dseg_1_length; /* Data segment 1 length. */ + __le32 dseg_2_address; /* Data segment 2 address. */ + __le32 dseg_2_length; /* Data segment 2 length. */ + __le32 dseg_3_address; /* Data segment 3 address. */ + __le32 dseg_3_length; /* Data segment 3 length. */ }; /* @@ -556,21 +544,21 @@ uint8_t entry_count; /* Entry count. */ uint8_t sys_define; /* System defined. */ uint8_t entry_status; /* Entry Status. */ - uint32_t reserved; /* Reserved */ - uint32_t dseg_0_address; /* Data segment 0 address. */ - uint32_t dseg_0_length; /* Data segment 0 length. */ - uint32_t dseg_1_address; /* Data segment 1 address. */ - uint32_t dseg_1_length; /* Data segment 1 length. */ - uint32_t dseg_2_address; /* Data segment 2 address. */ - uint32_t dseg_2_length; /* Data segment 2 length. */ - uint32_t dseg_3_address; /* Data segment 3 address. */ - uint32_t dseg_3_length; /* Data segment 3 length. */ - uint32_t dseg_4_address; /* Data segment 4 address. */ - uint32_t dseg_4_length; /* Data segment 4 length. */ - uint32_t dseg_5_address; /* Data segment 5 address. */ - uint32_t dseg_5_length; /* Data segment 5 length. */ - uint32_t dseg_6_address; /* Data segment 6 address. */ - uint32_t dseg_6_length; /* Data segment 6 length. */ + __le32 reserved; /* Reserved */ + __le32 dseg_0_address; /* Data segment 0 address. */ + __le32 dseg_0_length; /* Data segment 0 length. */ + __le32 dseg_1_address; /* Data segment 1 address. */ + __le32 dseg_1_length; /* Data segment 1 length. */ + __le32 dseg_2_address; /* Data segment 2 address. */ + __le32 dseg_2_length; /* Data segment 2 length. */ + __le32 dseg_3_address; /* Data segment 3 address. */ + __le32 dseg_3_length; /* Data segment 3 length. */ + __le32 dseg_4_address; /* Data segment 4 address. */ + __le32 dseg_4_length; /* Data segment 4 length. */ + __le32 dseg_5_address; /* Data segment 5 address. */ + __le32 dseg_5_length; /* Data segment 5 length. */ + __le32 dseg_6_address; /* Data segment 6 address. */ + __le32 dseg_6_length; /* Data segment 6 length. */ }; /* @@ -586,22 +574,22 @@ #define RF_FULL BIT_1 /* Full */ #define RF_BAD_HEADER BIT_2 /* Bad header. */ #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */ - uint32_t handle; /* System handle. */ - uint16_t scsi_status; /* SCSI status. */ - uint16_t comp_status; /* Completion status. */ - uint16_t state_flags; /* State flags. */ -#define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */ -#define SF_GOT_SENSE BIT_13 /* Got Sense */ -#define SF_GOT_STATUS BIT_12 /* Got Status */ -#define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */ -#define SF_SENT_CDB BIT_10 /* Send CDB */ -#define SF_GOT_TARGET BIT_9 /* */ -#define SF_GOT_BUS BIT_8 /* */ - uint16_t status_flags; /* Status flags. */ - uint16_t time; /* Time. */ - uint16_t req_sense_length; /* Request sense data length. */ - uint32_t residual_length; /* Residual transfer length. */ - uint16_t reserved[4]; + __le32 handle; /* System handle. */ + __le16 scsi_status; /* SCSI status. */ + __le16 comp_status; /* Completion status. */ + __le16 state_flags; /* State flags. */ +#define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */ +#define SF_GOT_SENSE BIT_13 /* Got Sense */ +#define SF_GOT_STATUS BIT_12 /* Got Status */ +#define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */ +#define SF_SENT_CDB BIT_10 /* Send CDB */ +#define SF_GOT_TARGET BIT_9 /* */ +#define SF_GOT_BUS BIT_8 /* */ + __le16 status_flags; /* Status flags. */ + __le16 time; /* Time. */ + __le16 req_sense_length;/* Request sense data length. */ + __le32 residual_length; /* Residual transfer length. */ + __le16 reserved[4]; uint8_t req_sense_data[32]; /* Request sense data. */ }; @@ -614,7 +602,7 @@ uint8_t entry_count; /* Entry count. */ uint8_t sys_define; /* System defined. */ uint8_t entry_status; /* Entry Status. */ - uint32_t reserved; + __le32 reserved; uint8_t lun; /* SCSI LUN */ uint8_t target; /* SCSI ID */ uint8_t modifier; /* Modifier (7-0). */ @@ -638,11 +626,11 @@ uint32_t handle; /* System handle. */ uint8_t lun; /* SCSI LUN */ uint8_t target; /* SCSI ID */ - uint16_t cdb_len; /* SCSI command length. */ - uint16_t control_flags; /* Control flags. */ - uint16_t reserved; - uint16_t timeout; /* Command timeout. */ - uint16_t dseg_count; /* Data segment count. */ + __le16 cdb_len; /* SCSI command length. */ + __le16 control_flags; /* Control flags. */ + __le16 reserved; + __le16 timeout; /* Command timeout. */ + __le16 dseg_count; /* Data segment count. */ uint8_t scsi_cdb[88]; /* SCSI command words. */ }; @@ -655,20 +643,20 @@ uint8_t entry_count; /* Entry count. */ uint8_t sys_define; /* System defined. */ uint8_t entry_status; /* Entry Status. */ - uint32_t handle; /* System handle. */ + __le32 handle; /* System handle. */ uint8_t lun; /* SCSI LUN */ uint8_t target; /* SCSI ID */ - uint16_t cdb_len; /* SCSI command length. */ - uint16_t control_flags; /* Control flags. */ - uint16_t reserved; - uint16_t timeout; /* Command timeout. */ - uint16_t dseg_count; /* Data segment count. */ + __le16 cdb_len; /* SCSI command length. */ + __le16 control_flags; /* Control flags. */ + __le16 reserved; + __le16 timeout; /* Command timeout. */ + __le16 dseg_count; /* Data segment count. */ uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ - uint32_t reserved_1[2]; /* unused */ - uint32_t dseg_0_address[2]; /* Data segment 0 address. */ - uint32_t dseg_0_length; /* Data segment 0 length. */ - uint32_t dseg_1_address[2]; /* Data segment 1 address. */ - uint32_t dseg_1_length; /* Data segment 1 length. */ + __le32 reserved_1[2]; /* unused */ + __le32 dseg_0_address[2]; /* Data segment 0 address. */ + __le32 dseg_0_length; /* Data segment 0 length. */ + __le32 dseg_1_address[2]; /* Data segment 1 address. */ + __le32 dseg_1_length; /* Data segment 1 length. */ } cmd_a64_entry_t, request_t; /* @@ -680,16 +668,16 @@ uint8_t entry_count; /* Entry count. */ uint8_t sys_define; /* System defined. */ uint8_t entry_status; /* Entry Status. */ - uint32_t dseg_0_address[2]; /* Data segment 0 address. */ - uint32_t dseg_0_length; /* Data segment 0 length. */ - uint32_t dseg_1_address[2]; /* Data segment 1 address. */ - uint32_t dseg_1_length; /* Data segment 1 length. */ - uint32_t dseg_2_address[2]; /* Data segment 2 address. */ - uint32_t dseg_2_length; /* Data segment 2 length. */ - uint32_t dseg_3_address[2]; /* Data segment 3 address. */ - uint32_t dseg_3_length; /* Data segment 3 length. */ - uint32_t dseg_4_address[2]; /* Data segment 4 address. */ - uint32_t dseg_4_length; /* Data segment 4 length. */ + __le32 dseg_0_address[2]; /* Data segment 0 address. */ + __le32 dseg_0_length; /* Data segment 0 length. */ + __le32 dseg_1_address[2]; /* Data segment 1 address. */ + __le32 dseg_1_length; /* Data segment 1 length. */ + __le32 dseg_2_address[2]; /* Data segment 2 address. */ + __le32 dseg_2_length; /* Data segment 2 length. */ + __le32 dseg_3_address[2]; /* Data segment 3 address. */ + __le32 dseg_3_length; /* Data segment 3 length. */ + __le32 dseg_4_address[2]; /* Data segment 4 address. */ + __le32 dseg_4_length; /* Data segment 4 length. */ }; /* @@ -701,10 +689,10 @@ uint8_t entry_count; /* Entry count. */ uint8_t reserved_1; uint8_t entry_status; /* Entry Status not used. */ - uint32_t reserved_2; - uint16_t lun; /* Bit 15 is bus number. */ - uint16_t reserved_4; - uint32_t option_flags; + __le32 reserved_2; + __le16 lun; /* Bit 15 is bus number. */ + __le16 reserved_4; + __le32 option_flags; uint8_t status; uint8_t reserved_5; uint8_t command_count; /* Number of ATIOs allocated. */ @@ -714,8 +702,8 @@ /* commands (2-26). */ uint8_t group_7_length; /* SCSI CDB length for group 7 */ /* commands (2-26). */ - uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ - uint16_t reserved_6[20]; + __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ + __le16 reserved_6[20]; }; /* @@ -729,20 +717,20 @@ uint8_t entry_count; /* Entry count. */ uint8_t reserved_1; uint8_t entry_status; /* Entry Status. */ - uint32_t reserved_2; + __le32 reserved_2; uint8_t lun; /* SCSI LUN */ uint8_t reserved_3; uint8_t operators; uint8_t reserved_4; - uint32_t option_flags; + __le32 option_flags; uint8_t status; uint8_t reserved_5; uint8_t command_count; /* Number of ATIOs allocated. */ uint8_t immed_notify_count; /* Number of Immediate Notify */ /* entries allocated. */ - uint16_t reserved_6; - uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ - uint16_t reserved_7[20]; + __le16 reserved_6; + __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ + __le16 reserved_7[20]; }; /* @@ -754,20 +742,20 @@ uint8_t entry_count; /* Entry count. */ uint8_t reserved_1; uint8_t entry_status; /* Entry Status. */ - uint32_t reserved_2; + __le32 reserved_2; uint8_t lun; uint8_t initiator_id; uint8_t reserved_3; uint8_t target_id; - uint32_t option_flags; + __le32 option_flags; uint8_t status; uint8_t reserved_4; uint8_t tag_value; /* Received queue tag message value */ uint8_t tag_type; /* Received queue tag message type */ /* entries allocated. */ - uint16_t seq_id; + __le16 seq_id; uint8_t scsi_msg[8]; /* SCSI message not handled by ISP */ - uint16_t reserved_5[8]; + __le16 reserved_5[8]; uint8_t sense_data[18]; }; @@ -780,16 +768,16 @@ uint8_t entry_count; /* Entry count. */ uint8_t reserved_1; uint8_t entry_status; /* Entry Status. */ - uint32_t reserved_2; + __le32 reserved_2; uint8_t lun; uint8_t initiator_id; uint8_t reserved_3; uint8_t target_id; - uint32_t option_flags; + __le32 option_flags; uint8_t status; uint8_t event; - uint16_t seq_id; - uint16_t reserved_4[22]; + __le16 seq_id; + __le16 reserved_4[22]; }; /* @@ -801,12 +789,12 @@ uint8_t entry_count; /* Entry count. */ uint8_t reserved_1; uint8_t entry_status; /* Entry Status. */ - uint32_t reserved_2; + __le32 reserved_2; uint8_t lun; uint8_t initiator_id; uint8_t cdb_len; uint8_t target_id; - uint32_t option_flags; + __le32 option_flags; uint8_t status; uint8_t scsi_status; uint8_t tag_value; /* Received queue tag message value */ @@ -824,28 +812,28 @@ uint8_t entry_count; /* Entry count. */ uint8_t reserved_1; uint8_t entry_status; /* Entry Status. */ - uint32_t reserved_2; + __le32 reserved_2; uint8_t lun; /* SCSI LUN */ uint8_t initiator_id; uint8_t reserved_3; uint8_t target_id; - uint32_t option_flags; + __le32 option_flags; uint8_t status; uint8_t scsi_status; uint8_t tag_value; /* Received queue tag message value */ uint8_t tag_type; /* Received queue tag message type */ - uint32_t transfer_length; - uint32_t residual; - uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ - uint16_t dseg_count; /* Data segment count. */ - uint32_t dseg_0_address; /* Data segment 0 address. */ - uint32_t dseg_0_length; /* Data segment 0 length. */ - uint32_t dseg_1_address; /* Data segment 1 address. */ - uint32_t dseg_1_length; /* Data segment 1 length. */ - uint32_t dseg_2_address; /* Data segment 2 address. */ - uint32_t dseg_2_length; /* Data segment 2 length. */ - uint32_t dseg_3_address; /* Data segment 3 address. */ - uint32_t dseg_3_length; /* Data segment 3 length. */ + __le32 transfer_length; + __le32 residual; + __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ + __le16 dseg_count; /* Data segment count. */ + __le32 dseg_0_address; /* Data segment 0 address. */ + __le32 dseg_0_length; /* Data segment 0 length. */ + __le32 dseg_1_address; /* Data segment 1 address. */ + __le32 dseg_1_length; /* Data segment 1 length. */ + __le32 dseg_2_address; /* Data segment 2 address. */ + __le32 dseg_2_length; /* Data segment 2 length. */ + __le32 dseg_3_address; /* Data segment 3 address. */ + __le32 dseg_3_length; /* Data segment 3 length. */ }; /* @@ -857,24 +845,24 @@ uint8_t entry_count; /* Entry count. */ uint8_t reserved_1; uint8_t entry_status; /* Entry Status. */ - uint32_t reserved_2; + __le32 reserved_2; uint8_t lun; /* SCSI LUN */ uint8_t initiator_id; uint8_t reserved_3; uint8_t target_id; - uint32_t option_flags; + __le32 option_flags; uint8_t status; uint8_t scsi_status; uint8_t tag_value; /* Received queue tag message value */ uint8_t tag_type; /* Received queue tag message type */ - uint32_t transfer_length; - uint32_t residual; - uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ - uint16_t dseg_count; /* Data segment count. */ - uint32_t dseg_0_address; /* Data segment 0 address. */ - uint32_t dseg_0_length; /* Data segment 0 length. */ - uint32_t dseg_1_address; /* Data segment 1 address. */ - uint16_t dseg_1_length; /* Data segment 1 length. */ + __le32 transfer_length; + __le32 residual; + __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ + __le16 dseg_count; /* Data segment count. */ + __le32 dseg_0_address; /* Data segment 0 address. */ + __le32 dseg_0_length; /* Data segment 0 length. */ + __le32 dseg_1_address; /* Data segment 1 address. */ + __le16 dseg_1_length; /* Data segment 1 length. */ uint8_t sense_data[18]; }; @@ -887,25 +875,25 @@ uint8_t entry_count; /* Entry count. */ uint8_t reserved_1; uint8_t entry_status; /* Entry Status. */ - uint32_t reserved_2; + __le32 reserved_2; uint8_t lun; /* SCSI LUN */ uint8_t initiator_id; uint8_t reserved_3; uint8_t target_id; - uint32_t option_flags; + __le32 option_flags; uint8_t status; uint8_t scsi_status; uint8_t tag_value; /* Received queue tag message value */ uint8_t tag_type; /* Received queue tag message type */ - uint32_t transfer_length; - uint32_t residual; - uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ - uint16_t dseg_count; /* Data segment count. */ - uint32_t reserved_4[2]; - uint32_t dseg_0_address[2]; /* Data segment 0 address. */ - uint32_t dseg_0_length; /* Data segment 0 length. */ - uint32_t dseg_1_address[2]; /* Data segment 1 address. */ - uint32_t dseg_1_length; /* Data segment 1 length. */ + __le32 transfer_length; + __le32 residual; + __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ + __le16 dseg_count; /* Data segment count. */ + __le32 reserved_4[2]; + __le32 dseg_0_address[2];/* Data segment 0 address. */ + __le32 dseg_0_length; /* Data segment 0 length. */ + __le32 dseg_1_address[2];/* Data segment 1 address. */ + __le32 dseg_1_length; /* Data segment 1 length. */ }; /* @@ -917,21 +905,21 @@ uint8_t entry_count; /* Entry count. */ uint8_t reserved_1; uint8_t entry_status; /* Entry Status. */ - uint32_t reserved_2; + __le32 reserved_2; uint8_t lun; /* SCSI LUN */ uint8_t initiator_id; uint8_t reserved_3; uint8_t target_id; - uint32_t option_flags; + __le32 option_flags; uint8_t status; uint8_t scsi_status; uint8_t tag_value; /* Received queue tag message value */ uint8_t tag_type; /* Received queue tag message type */ - uint32_t transfer_length; - uint32_t residual; - uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ - uint16_t dseg_count; /* Data segment count. */ - uint16_t reserved_4[7]; + __le32 transfer_length; + __le32 residual; + __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ + __le16 dseg_count; /* Data segment count. */ + __le16 reserved_4[7]; uint8_t sense_data[18]; }; @@ -979,14 +967,6 @@ #define CS_RETRY 0x82 /* Driver defined */ /* - * ISP status entry - SCSI status byte bit definitions. - */ -#define SS_CHECK_CONDITION BIT_1 -#define SS_CONDITION_MET BIT_2 -#define SS_BUSY_CONDITION BIT_3 -#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) - -/* * ISP target entries - Option flags bit definitions. */ #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */ @@ -1082,10 +1062,6 @@ uint32_t reset_active:1; /* 3 */ uint32_t abort_isp_active:1; /* 4 */ uint32_t disable_risc_code_load:1; /* 5 */ - uint32_t enable_64bit_addressing:1; /* 6 */ - uint32_t in_reset:1; /* 7 */ - uint32_t ints_enabled:1; - uint32_t ignore_nvram:1; #ifdef __ia64__ uint32_t use_pci_vchannel:1; #endif diff -Naur linux-2.6.12.6.orig/drivers/scsi/qlogicisp.c linux-2.6.12.6/drivers/scsi/qlogicisp.c --- linux-2.6.12.6.orig/drivers/scsi/qlogicisp.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/scsi/qlogicisp.c 2005-10-02 23:47:39.000000000 +0000 @@ -1058,28 +1058,31 @@ DEBUG_INTR(isp1020_print_status_entry(sts)); - if (sts->hdr.entry_type == ENTRY_STATUS) - Cmnd->result = isp1020_return_status(sts); - else - Cmnd->result = DID_ERROR << 16; - - if (Cmnd->use_sg) - pci_unmap_sg(hostdata->pci_dev, - (struct scatterlist *)Cmnd->buffer, - Cmnd->use_sg, - Cmnd->sc_data_direction); - else if (Cmnd->request_bufflen) - pci_unmap_single(hostdata->pci_dev, + if (Cmnd) { + if (sts->hdr.entry_type == ENTRY_STATUS) + Cmnd->result = isp1020_return_status(sts); + else + Cmnd->result = DID_ERROR << 16; + + if (Cmnd->use_sg) + pci_unmap_sg(hostdata->pci_dev, + (struct scatterlist *)Cmnd->buffer, + Cmnd->use_sg, + Cmnd->sc_data_direction); + else if (Cmnd->request_bufflen) + pci_unmap_single(hostdata->pci_dev, #ifdef CONFIG_QL_ISP_A64 - (dma_addr_t)((long)Cmnd->SCp.ptr), + (dma_addr_t)((long)Cmnd->SCp.ptr), #else - (u32)((long)Cmnd->SCp.ptr), + (u32)((long)Cmnd->SCp.ptr), #endif - Cmnd->request_bufflen, - Cmnd->sc_data_direction); + Cmnd->request_bufflen, + Cmnd->sc_data_direction); - isp_outw(out_ptr, host, MBOX5); - (*Cmnd->scsi_done)(Cmnd); + isp_outw(out_ptr, host, MBOX5); + (*Cmnd->scsi_done)(Cmnd); + } else + printk(KERN_CRIT "qlogic: Cmnd == NULL\n"); } hostdata->res_out_ptr = out_ptr; @@ -1200,6 +1203,13 @@ return 0; } +static int +isp1020_eh_abort(struct scsi_cmnd * cmd) +{ + printk(KERN_WARNING "ISP1020 is toast\n"); + return -ENODEV; +} + static int isp1020_reset_hardware(struct Scsi_Host *host) { @@ -1925,6 +1935,7 @@ .release = isp1020_release, .info = isp1020_info, .queuecommand = isp1020_queuecommand, + .eh_abort_handler = isp1020_eh_abort, .bios_param = isp1020_biosparam, .can_queue = QLOGICISP_REQ_QUEUE_LEN, .this_id = -1, diff -Naur linux-2.6.12.6.orig/drivers/scsi/sgiwd93.c linux-2.6.12.6/drivers/scsi/sgiwd93.c --- linux-2.6.12.6.orig/drivers/scsi/sgiwd93.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/scsi/sgiwd93.c 2005-10-02 23:47:39.000000000 +0000 @@ -33,7 +33,6 @@ #include "scsi.h" #include #include "wd33c93.h" -#include "sgiwd93.h" #include @@ -320,7 +319,6 @@ * on 64-bit systems with memory outside the compat address spaces. */ static Scsi_Host_Template driver_template = { - .proc_name = "SGIWD93", .name = "SGI WD93", .detect = sgiwd93_detect, .release = sgiwd93_release, @@ -328,10 +326,12 @@ .eh_abort_handler = wd33c93_abort, .eh_bus_reset_handler = sgiwd93_bus_reset, .eh_host_reset_handler = wd33c93_host_reset, - .can_queue = CAN_QUEUE, + .proc_info = wd33c93_proc_info, + .proc_name = "SGIWD93", + .can_queue = 16, .this_id = 7, .sg_tablesize = SG_ALL, - .cmd_per_lun = CMD_PER_LUN, + .cmd_per_lun = 8, .use_clustering = DISABLE_CLUSTERING, }; #include "scsi_module.c" diff -Naur linux-2.6.12.6.orig/drivers/scsi/sgiwd93.h linux-2.6.12.6/drivers/scsi/sgiwd93.h --- linux-2.6.12.6.orig/drivers/scsi/sgiwd93.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/scsi/sgiwd93.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,24 +0,0 @@ -/* $Id: sgiwd93.h,v 1.5 1998/08/25 09:18:50 ralf Exp $ - * sgiwd93.h: SGI WD93 scsi definitions. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#ifndef _SGIWD93_H -#define _SGIWD93_H - -#ifndef CMD_PER_LUN -#define CMD_PER_LUN 8 -#endif - -#ifndef CAN_QUEUE -#define CAN_QUEUE 16 -#endif - -int sgiwd93_detect(Scsi_Host_Template *); -int sgiwd93_release(struct Scsi_Host *instance); -const char *wd33c93_info(void); -int wd33c93_queuecommand(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *)); -int wd33c93_abort(Scsi_Cmnd *); -int wd33c93_host_reset(Scsi_Cmnd * SCpnt); - -#endif /* !(_SGIWD93_H) */ diff -Naur linux-2.6.12.6.orig/drivers/scsi/sym53c8xx_defs.h linux-2.6.12.6/drivers/scsi/sym53c8xx_defs.h --- linux-2.6.12.6.orig/drivers/scsi/sym53c8xx_defs.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/scsi/sym53c8xx_defs.h 2005-10-02 23:47:39.000000000 +0000 @@ -314,9 +314,19 @@ #define writew_b2l __raw_writew #define writel_b2l __raw_writel #define readw_raw __raw_readw -#define readl_raw __raw_readl +#define readl_raw(a) __raw_readl((unsigned long)(a)) #define writew_raw __raw_writew -#define writel_raw __raw_writel +#define writel_raw(v,a) __raw_writel(v,(unsigned long)(a)) +#else /* Other big-endian */ +#elif defined(__mips__) +#define readw_l2b readw +#define readl_l2b readl +#define writew_b2l writew +#define writel_b2l writel +#define inw_l2b inw +#define inl_l2b inl +#define outw_b2l outw +#define outl_b2l outl #else /* Other big-endian */ #define readw_l2b readw #define readl_l2b readl diff -Naur linux-2.6.12.6.orig/drivers/serial/Makefile linux-2.6.12.6/drivers/serial/Makefile --- linux-2.6.12.6.orig/drivers/serial/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/serial/Makefile 2005-10-02 23:47:39.000000000 +0000 @@ -50,5 +50,4 @@ obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o obj-$(CONFIG_SERIAL_JSM) += jsm/ obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o -obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o obj-$(CONFIG_BLK_DEV_SGIIOC4) += ioc4_serial.o diff -Naur linux-2.6.12.6.orig/drivers/serial/au1x00_uart.c linux-2.6.12.6/drivers/serial/au1x00_uart.c --- linux-2.6.12.6.orig/drivers/serial/au1x00_uart.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/serial/au1x00_uart.c 2005-10-02 23:47:39.000000000 +0000 @@ -67,30 +67,7 @@ #define is_real_interrupt(irq) ((irq) != 0) static struct old_serial_port old_serial_port[] = { - { .baud_base = 0, - .iomem_base = (u8 *)UART0_ADDR, - .irq = AU1000_UART0_INT, - .flags = STD_COM_FLAGS, - .iomem_reg_shift = 2, - }, { - .baud_base = 0, - .iomem_base = (u8 *)UART1_ADDR, - .irq = AU1000_UART1_INT, - .flags = STD_COM_FLAGS, - .iomem_reg_shift = 2 - }, { - .baud_base = 0, - .iomem_base = (u8 *)UART2_ADDR, - .irq = AU1000_UART2_INT, - .flags = STD_COM_FLAGS, - .iomem_reg_shift = 2 - }, { - .baud_base = 0, - .iomem_base = (u8 *)UART3_ADDR, - .irq = AU1000_UART3_INT, - .flags = STD_COM_FLAGS, - .iomem_reg_shift = 2 - } + SERIAL_PORT_DFNS }; #define UART_NR ARRAY_SIZE(old_serial_port) @@ -803,7 +780,6 @@ */ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); quot = serial8250_get_divisor(port, baud); - quot = 0x35; /* FIXME */ /* * Work around a bug in the Oxford Semiconductor 952 rev B @@ -869,6 +845,7 @@ serial_out(up, UART_IER, up->ier); serial_outp(up, 0x28, quot & 0xffff); + serial_out(up, UART_LCR, cval); /* reset DLAB */ up->lcr = cval; /* Save LCR */ if (up->port.type != PORT_16750) { if (fcr & UART_FCR_ENABLE_FIFO) { @@ -1071,7 +1048,7 @@ i++, up++) { up->port.iobase = old_serial_port[i].port; up->port.irq = old_serial_port[i].irq; - up->port.uartclk = get_au1x00_uart_baud_base(); + up->port.uartclk = get_au1x00_uart_baud_base() * 16; up->port.flags = old_serial_port[i].flags; up->port.hub6 = old_serial_port[i].hub6; up->port.membase = old_serial_port[i].iomem_base; @@ -1209,7 +1186,7 @@ return uart_set_options(port, co, baud, parity, bits, flow); } -extern struct uart_driver serial8250_reg; +static struct uart_driver serial8250_reg; static struct console serial8250_console = { .name = "ttyS", .write = serial8250_console_write, diff -Naur linux-2.6.12.6.orig/drivers/serial/dz.c linux-2.6.12.6/drivers/serial/dz.c --- linux-2.6.12.6.orig/drivers/serial/dz.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/serial/dz.c 2005-10-02 23:47:39.000000000 +0000 @@ -645,9 +645,9 @@ if (mips_machtype == MACH_DS23100 || mips_machtype == MACH_DS5100) - base = (unsigned long) KN01_DZ11_BASE; + base = CKSEG1ADDR(KN01_SLOT_BASE + KN01_DZ11); else - base = (unsigned long) KN02_DZ11_BASE; + base = CKSEG1ADDR(KN02_SLOT_BASE + KN02_DZ11); for (i = 0, dport = dz_ports; i < DZ_NB_PORT; i++, dport++) { spin_lock_init(&dport->port.lock); diff -Naur linux-2.6.12.6.orig/drivers/serial/ip22zilog.c linux-2.6.12.6/drivers/serial/ip22zilog.c --- linux-2.6.12.6.orig/drivers/serial/ip22zilog.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/serial/ip22zilog.c 2005-10-02 23:47:39.000000000 +0000 @@ -881,6 +881,7 @@ up->cflag = termios->c_cflag; ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port)); + uart_update_timeout(port, termios->c_cflag, baud); spin_unlock_irqrestore(&up->port.lock, flags); } @@ -1047,6 +1048,8 @@ } con->cflag = cflag | CS8; /* 8N1 */ + + uart_update_timeout(&ip22zilog_port_table[con->index].port, cflag, baud); } static int __init ip22zilog_console_setup(struct console *con, char *options) diff -Naur linux-2.6.12.6.orig/drivers/serial/serial_txx9.c linux-2.6.12.6/drivers/serial/serial_txx9.c --- linux-2.6.12.6.orig/drivers/serial/serial_txx9.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/serial/serial_txx9.c 2005-10-02 23:47:39.000000000 +0000 @@ -31,6 +31,7 @@ * 1.01 Set fifosize to make tx_empry called properly. * Use standard uart_get_divisor. * 1.02 Cleanup. (import 8250.c changes) + * 1.03 Fix low-latency mode. (import 8250.c changes) */ #include @@ -54,7 +55,7 @@ #include #include -static char *serial_version = "1.02"; +static char *serial_version = "1.03"; static char *serial_name = "TX39/49 Serial driver"; #define PASS_LIMIT 256 @@ -304,8 +305,11 @@ /* The following is not allowed by the tty layer and unsafe. It should be fixed ASAP */ if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) { - if(tty->low_latency) + if (tty->low_latency) { + spin_unlock(&up->port.lock); tty_flip_buffer_push(tty); + spin_lock(&up->port.lock); + } /* If this failed then we will throw away the bytes but must do so to clear interrupts */ } @@ -356,7 +360,9 @@ ignore_char: disr = sio_in(up, TXX9_SIDISR); } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0)); + spin_unlock(&up->port.lock); tty_flip_buffer_push(tty); + spin_lock(&up->port.lock); *status = disr; } diff -Naur linux-2.6.12.6.orig/drivers/serial/vr41xx_siu.c linux-2.6.12.6/drivers/serial/vr41xx_siu.c --- linux-2.6.12.6.orig/drivers/serial/vr41xx_siu.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/serial/vr41xx_siu.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,1050 +0,0 @@ -/* - * Driver for NEC VR4100 series Serial Interface Unit. - * - * Copyright (C) 2004-2005 Yoichi Yuasa - * - * Based on drivers/serial/8250.c, by Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include - -#if defined(CONFIG_SERIAL_VR41XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) -#define SUPPORT_SYSRQ -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#define SIU_PORTS_MAX 2 -#define SIU_BAUD_BASE 1152000 -#define SIU_MAJOR 204 -#define SIU_MINOR_BASE 82 - -#define RX_MAX_COUNT 256 -#define TX_MAX_COUNT 15 - -#define SIUIRSEL 0x08 - #define TMICMODE 0x20 - #define TMICTX 0x10 - #define IRMSEL 0x0c - #define IRMSEL_HP 0x08 - #define IRMSEL_TEMIC 0x04 - #define IRMSEL_SHARP 0x00 - #define IRUSESEL 0x02 - #define SIRSEL 0x01 - -struct siu_port { - unsigned int type; - unsigned int irq; - unsigned long start; -}; - -static const struct siu_port siu_type1_ports[] = { - { .type = PORT_VR41XX_SIU, - .irq = SIU_IRQ, - .start = 0x0c000000UL, }, -}; - -#define SIU_TYPE1_NR_PORTS (sizeof(siu_type1_ports) / sizeof(struct siu_port)) - -static const struct siu_port siu_type2_ports[] = { - { .type = PORT_VR41XX_SIU, - .irq = SIU_IRQ, - .start = 0x0f000800UL, }, - { .type = PORT_VR41XX_DSIU, - .irq = DSIU_IRQ, - .start = 0x0f000820UL, }, -}; - -#define SIU_TYPE2_NR_PORTS (sizeof(siu_type2_ports) / sizeof(struct siu_port)) - -static struct uart_port siu_uart_ports[SIU_PORTS_MAX]; -static uint8_t lsr_break_flag[SIU_PORTS_MAX]; - -#define siu_read(port, offset) readb((port)->membase + (offset)) -#define siu_write(port, offset, value) writeb((value), (port)->membase + (offset)) - -void vr41xx_select_siu_interface(siu_interface_t interface) -{ - struct uart_port *port; - unsigned long flags; - uint8_t irsel; - - port = &siu_uart_ports[0]; - - spin_lock_irqsave(&port->lock, flags); - - irsel = siu_read(port, SIUIRSEL); - if (interface == SIU_INTERFACE_IRDA) - irsel |= SIRSEL; - else - irsel &= ~SIRSEL; - siu_write(port, SIUIRSEL, irsel); - - spin_unlock_irqrestore(&port->lock, flags); -} - -EXPORT_SYMBOL_GPL(vr41xx_select_siu_interface); - -void vr41xx_use_irda(irda_use_t use) -{ - struct uart_port *port; - unsigned long flags; - uint8_t irsel; - - port = &siu_uart_ports[0]; - - spin_lock_irqsave(&port->lock, flags); - - irsel = siu_read(port, SIUIRSEL); - if (use == FIR_USE_IRDA) - irsel |= IRUSESEL; - else - irsel &= ~IRUSESEL; - siu_write(port, SIUIRSEL, irsel); - - spin_unlock_irqrestore(&port->lock, flags); -} - -EXPORT_SYMBOL_GPL(vr41xx_use_irda); - -void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed) -{ - struct uart_port *port; - unsigned long flags; - uint8_t irsel; - - port = &siu_uart_ports[0]; - - spin_lock_irqsave(&port->lock, flags); - - irsel = siu_read(port, SIUIRSEL); - irsel &= ~(IRMSEL | TMICTX | TMICMODE); - switch (module) { - case SHARP_IRDA: - irsel |= IRMSEL_SHARP; - break; - case TEMIC_IRDA: - irsel |= IRMSEL_TEMIC | TMICMODE; - if (speed == IRDA_TX_4MBPS) - irsel |= TMICTX; - break; - case HP_IRDA: - irsel |= IRMSEL_HP; - break; - default: - break; - } - siu_write(port, SIUIRSEL, irsel); - - spin_unlock_irqrestore(&port->lock, flags); -} - -EXPORT_SYMBOL_GPL(vr41xx_select_irda_module); - -static inline void siu_clear_fifo(struct uart_port *port) -{ - siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO); - siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | - UART_FCR_CLEAR_XMIT); - siu_write(port, UART_FCR, 0); -} - -static inline int siu_probe_ports(void) -{ - switch (current_cpu_data.cputype) { - case CPU_VR4111: - case CPU_VR4121: - return SIU_TYPE1_NR_PORTS; - case CPU_VR4122: - case CPU_VR4131: - case CPU_VR4133: - return SIU_TYPE2_NR_PORTS; - } - - return 0; -} - -static inline unsigned long siu_port_size(struct uart_port *port) -{ - switch (port->type) { - case PORT_VR41XX_SIU: - return 11UL; - case PORT_VR41XX_DSIU: - return 8UL; - } - - return 0; -} - -static inline unsigned int siu_check_type(struct uart_port *port) -{ - switch (current_cpu_data.cputype) { - case CPU_VR4111: - case CPU_VR4121: - if (port->line == 0) - return PORT_VR41XX_SIU; - break; - case CPU_VR4122: - case CPU_VR4131: - case CPU_VR4133: - if (port->line == 0) - return PORT_VR41XX_SIU; - else if (port->line == 1) - return PORT_VR41XX_DSIU; - break; - } - - return PORT_UNKNOWN; -} - -static inline const char *siu_type_name(struct uart_port *port) -{ - switch (port->type) { - case PORT_VR41XX_SIU: - return "SIU"; - case PORT_VR41XX_DSIU: - return "DSIU"; - } - - return NULL; -} - -static unsigned int siu_tx_empty(struct uart_port *port) -{ - uint8_t lsr; - - lsr = siu_read(port, UART_LSR); - if (lsr & UART_LSR_TEMT) - return TIOCSER_TEMT; - - return 0; -} - -static void siu_set_mctrl(struct uart_port *port, unsigned int mctrl) -{ - uint8_t mcr = 0; - - if (mctrl & TIOCM_DTR) - mcr |= UART_MCR_DTR; - if (mctrl & TIOCM_RTS) - mcr |= UART_MCR_RTS; - if (mctrl & TIOCM_OUT1) - mcr |= UART_MCR_OUT1; - if (mctrl & TIOCM_OUT2) - mcr |= UART_MCR_OUT2; - if (mctrl & TIOCM_LOOP) - mcr |= UART_MCR_LOOP; - - siu_write(port, UART_MCR, mcr); -} - -static unsigned int siu_get_mctrl(struct uart_port *port) -{ - uint8_t msr; - unsigned int mctrl = 0; - - msr = siu_read(port, UART_MSR); - if (msr & UART_MSR_DCD) - mctrl |= TIOCM_CAR; - if (msr & UART_MSR_RI) - mctrl |= TIOCM_RNG; - if (msr & UART_MSR_DSR) - mctrl |= TIOCM_DSR; - if (msr & UART_MSR_CTS) - mctrl |= TIOCM_CTS; - - return mctrl; -} - -static void siu_stop_tx(struct uart_port *port, unsigned int tty_stop) -{ - unsigned long flags; - uint8_t ier; - - spin_lock_irqsave(&port->lock, flags); - - ier = siu_read(port, UART_IER); - ier &= ~UART_IER_THRI; - siu_write(port, UART_IER, ier); - - spin_unlock_irqrestore(&port->lock, flags); -} - -static void siu_start_tx(struct uart_port *port, unsigned int tty_start) -{ - unsigned long flags; - uint8_t ier; - - spin_lock_irqsave(&port->lock, flags); - - ier = siu_read(port, UART_IER); - ier |= UART_IER_THRI; - siu_write(port, UART_IER, ier); - - spin_unlock_irqrestore(&port->lock, flags); -} - -static void siu_stop_rx(struct uart_port *port) -{ - unsigned long flags; - uint8_t ier; - - spin_lock_irqsave(&port->lock, flags); - - ier = siu_read(port, UART_IER); - ier &= ~UART_IER_RLSI; - siu_write(port, UART_IER, ier); - - port->read_status_mask &= ~UART_LSR_DR; - - spin_unlock_irqrestore(&port->lock, flags); -} - -static void siu_enable_ms(struct uart_port *port) -{ - unsigned long flags; - uint8_t ier; - - spin_lock_irqsave(&port->lock, flags); - - ier = siu_read(port, UART_IER); - ier |= UART_IER_MSI; - siu_write(port, UART_IER, ier); - - spin_unlock_irqrestore(&port->lock, flags); -} - -static void siu_break_ctl(struct uart_port *port, int ctl) -{ - unsigned long flags; - uint8_t lcr; - - spin_lock_irqsave(&port->lock, flags); - - lcr = siu_read(port, UART_LCR); - if (ctl == -1) - lcr |= UART_LCR_SBC; - else - lcr &= ~UART_LCR_SBC; - siu_write(port, UART_LCR, lcr); - - spin_unlock_irqrestore(&port->lock, flags); -} - -static inline void receive_chars(struct uart_port *port, uint8_t *status, - struct pt_regs *regs) -{ - struct tty_struct *tty; - uint8_t lsr, ch; - char flag; - int max_count = RX_MAX_COUNT; - - tty = port->info->tty; - lsr = *status; - - do { - if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) { - if (tty->low_latency) - tty_flip_buffer_push(tty); - } - - ch = siu_read(port, UART_RX); - port->icount.rx++; - flag = TTY_NORMAL; - -#ifdef CONFIG_SERIAL_VR41XX_CONSOLE - lsr |= lsr_break_flag[port->line]; - lsr_break_flag[port->line] = 0; -#endif - if (unlikely(lsr & (UART_LSR_BI | UART_LSR_FE | - UART_LSR_PE | UART_LSR_OE))) { - if (lsr & UART_LSR_BI) { - lsr &= ~(UART_LSR_FE | UART_LSR_PE); - port->icount.brk++; - - if (uart_handle_break(port)) - goto ignore_char; - } - - if (lsr & UART_LSR_FE) - port->icount.frame++; - if (lsr & UART_LSR_PE) - port->icount.parity++; - if (lsr & UART_LSR_OE) - port->icount.overrun++; - - lsr &= port->read_status_mask; - if (lsr & UART_LSR_BI) - flag = TTY_BREAK; - if (lsr & UART_LSR_FE) - flag = TTY_FRAME; - if (lsr & UART_LSR_PE) - flag = TTY_PARITY; - } - - if (uart_handle_sysrq_char(port, ch, regs)) - goto ignore_char; - - uart_insert_char(port, lsr, UART_LSR_OE, ch, flag); - - ignore_char: - lsr = siu_read(port, UART_LSR); - } while ((lsr & UART_LSR_DR) && (max_count-- > 0)); - - tty_flip_buffer_push(tty); - - *status = lsr; -} - -static inline void check_modem_status(struct uart_port *port) -{ - uint8_t msr; - - msr = siu_read(port, UART_MSR); - if ((msr & UART_MSR_ANY_DELTA) == 0) - return; - if (msr & UART_MSR_DDCD) - uart_handle_dcd_change(port, msr & UART_MSR_DCD); - if (msr & UART_MSR_TERI) - port->icount.rng++; - if (msr & UART_MSR_DDSR) - port->icount.dsr++; - if (msr & UART_MSR_DCTS) - uart_handle_cts_change(port, msr & UART_MSR_CTS); - - wake_up_interruptible(&port->info->delta_msr_wait); -} - -static inline void transmit_chars(struct uart_port *port) -{ - struct circ_buf *xmit; - int max_count = TX_MAX_COUNT; - - xmit = &port->info->xmit; - - if (port->x_char) { - siu_write(port, UART_TX, port->x_char); - port->icount.tx++; - port->x_char = 0; - return; - } - - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { - siu_stop_tx(port, 0); - return; - } - - do { - siu_write(port, UART_TX, xmit->buf[xmit->tail]); - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); - port->icount.tx++; - if (uart_circ_empty(xmit)) - break; - } while (max_count-- > 0); - - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) - uart_write_wakeup(port); - - if (uart_circ_empty(xmit)) - siu_stop_tx(port, 0); -} - -static irqreturn_t siu_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - struct uart_port *port; - uint8_t iir, lsr; - - port = (struct uart_port *)dev_id; - - iir = siu_read(port, UART_IIR); - if (iir & UART_IIR_NO_INT) - return IRQ_NONE; - - lsr = siu_read(port, UART_LSR); - if (lsr & UART_LSR_DR) - receive_chars(port, &lsr, regs); - - check_modem_status(port); - - if (lsr & UART_LSR_THRE) - transmit_chars(port); - - return IRQ_HANDLED; -} - -static int siu_startup(struct uart_port *port) -{ - int retval; - - if (port->membase == NULL) - return -ENODEV; - - siu_clear_fifo(port); - - (void)siu_read(port, UART_LSR); - (void)siu_read(port, UART_RX); - (void)siu_read(port, UART_IIR); - (void)siu_read(port, UART_MSR); - - if (siu_read(port, UART_LSR) == 0xff) - return -ENODEV; - - retval = request_irq(port->irq, siu_interrupt, 0, siu_type_name(port), port); - if (retval) - return retval; - - if (port->type == PORT_VR41XX_DSIU) - vr41xx_enable_dsiuint(DSIUINT_ALL); - - siu_write(port, UART_LCR, UART_LCR_WLEN8); - - spin_lock_irq(&port->lock); - siu_set_mctrl(port, port->mctrl); - spin_unlock_irq(&port->lock); - - siu_write(port, UART_IER, UART_IER_RLSI | UART_IER_RDI); - - (void)siu_read(port, UART_LSR); - (void)siu_read(port, UART_RX); - (void)siu_read(port, UART_IIR); - (void)siu_read(port, UART_MSR); - - return 0; -} - -static void siu_shutdown(struct uart_port *port) -{ - unsigned long flags; - uint8_t lcr; - - siu_write(port, UART_IER, 0); - - spin_lock_irqsave(&port->lock, flags); - - port->mctrl &= ~TIOCM_OUT2; - siu_set_mctrl(port, port->mctrl); - - spin_unlock_irqrestore(&port->lock, flags); - - lcr = siu_read(port, UART_LCR); - lcr &= ~UART_LCR_SBC; - siu_write(port, UART_LCR, lcr); - - siu_clear_fifo(port); - - (void)siu_read(port, UART_RX); - - if (port->type == PORT_VR41XX_DSIU) - vr41xx_disable_dsiuint(DSIUINT_ALL); - - free_irq(port->irq, port); -} - -static void siu_set_termios(struct uart_port *port, struct termios *new, - struct termios *old) -{ - tcflag_t c_cflag, c_iflag; - uint8_t lcr, fcr, ier; - unsigned int baud, quot; - unsigned long flags; - - c_cflag = new->c_cflag; - switch (c_cflag & CSIZE) { - case CS5: - lcr = UART_LCR_WLEN5; - break; - case CS6: - lcr = UART_LCR_WLEN6; - break; - case CS7: - lcr = UART_LCR_WLEN7; - break; - default: - lcr = UART_LCR_WLEN8; - break; - } - - if (c_cflag & CSTOPB) - lcr |= UART_LCR_STOP; - if (c_cflag & PARENB) - lcr |= UART_LCR_PARITY; - if ((c_cflag & PARODD) != PARODD) - lcr |= UART_LCR_EPAR; - if (c_cflag & CMSPAR) - lcr |= UART_LCR_SPAR; - - baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16); - quot = uart_get_divisor(port, baud); - - fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10; - - spin_lock_irqsave(&port->lock, flags); - - uart_update_timeout(port, c_cflag, baud); - - c_iflag = new->c_iflag; - - port->read_status_mask = UART_LSR_THRE | UART_LSR_OE | UART_LSR_DR; - if (c_iflag & INPCK) - port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; - if (c_iflag & (BRKINT | PARMRK)) - port->read_status_mask |= UART_LSR_BI; - - port->ignore_status_mask = 0; - if (c_iflag & IGNPAR) - port->ignore_status_mask |= UART_LSR_FE | UART_LSR_PE; - if (c_iflag & IGNBRK) { - port->ignore_status_mask |= UART_LSR_BI; - if (c_iflag & IGNPAR) - port->ignore_status_mask |= UART_LSR_OE; - } - - if ((c_cflag & CREAD) == 0) - port->ignore_status_mask |= UART_LSR_DR; - - ier = siu_read(port, UART_IER); - ier &= ~UART_IER_MSI; - if (UART_ENABLE_MS(port, c_cflag)) - ier |= UART_IER_MSI; - siu_write(port, UART_IER, ier); - - siu_write(port, UART_LCR, lcr | UART_LCR_DLAB); - - siu_write(port, UART_DLL, (uint8_t)quot); - siu_write(port, UART_DLM, (uint8_t)(quot >> 8)); - - siu_write(port, UART_LCR, lcr); - - siu_write(port, UART_FCR, fcr); - - siu_set_mctrl(port, port->mctrl); - - spin_unlock_irqrestore(&port->lock, flags); -} - -static void siu_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) -{ - switch (state) { - case 0: - switch (port->type) { - case PORT_VR41XX_SIU: - vr41xx_supply_clock(SIU_CLOCK); - break; - case PORT_VR41XX_DSIU: - vr41xx_supply_clock(DSIU_CLOCK); - break; - } - break; - case 3: - switch (port->type) { - case PORT_VR41XX_SIU: - vr41xx_mask_clock(SIU_CLOCK); - break; - case PORT_VR41XX_DSIU: - vr41xx_mask_clock(DSIU_CLOCK); - break; - } - break; - } -} - -static const char *siu_type(struct uart_port *port) -{ - return siu_type_name(port); -} - -static void siu_release_port(struct uart_port *port) -{ - unsigned long size; - - if (port->flags & UPF_IOREMAP) { - iounmap(port->membase); - port->membase = NULL; - } - - size = siu_port_size(port); - release_mem_region(port->mapbase, size); -} - -static int siu_request_port(struct uart_port *port) -{ - unsigned long size; - struct resource *res; - - size = siu_port_size(port); - res = request_mem_region(port->mapbase, size, siu_type_name(port)); - if (res == NULL) - return -EBUSY; - - if (port->flags & UPF_IOREMAP) { - port->membase = ioremap(port->mapbase, size); - if (port->membase == NULL) { - release_resource(res); - return -ENOMEM; - } - } - - return 0; -} - -static void siu_config_port(struct uart_port *port, int flags) -{ - if (flags & UART_CONFIG_TYPE) { - port->type = siu_check_type(port); - (void)siu_request_port(port); - } -} - -static int siu_verify_port(struct uart_port *port, struct serial_struct *serial) -{ - if (port->type != PORT_VR41XX_SIU && port->type != PORT_VR41XX_DSIU) - return -EINVAL; - if (port->irq != serial->irq) - return -EINVAL; - if (port->iotype != serial->io_type) - return -EINVAL; - if (port->mapbase != (unsigned long)serial->iomem_base) - return -EINVAL; - - return 0; -} - -static struct uart_ops siu_uart_ops = { - .tx_empty = siu_tx_empty, - .set_mctrl = siu_set_mctrl, - .get_mctrl = siu_get_mctrl, - .stop_tx = siu_stop_tx, - .start_tx = siu_start_tx, - .stop_rx = siu_stop_rx, - .enable_ms = siu_enable_ms, - .break_ctl = siu_break_ctl, - .startup = siu_startup, - .shutdown = siu_shutdown, - .set_termios = siu_set_termios, - .pm = siu_pm, - .type = siu_type, - .release_port = siu_release_port, - .request_port = siu_request_port, - .config_port = siu_config_port, - .verify_port = siu_verify_port, -}; - -static int siu_init_ports(void) -{ - const struct siu_port *siu; - struct uart_port *port; - int i, num; - - switch (current_cpu_data.cputype) { - case CPU_VR4111: - case CPU_VR4121: - siu = siu_type1_ports; - break; - case CPU_VR4122: - case CPU_VR4131: - case CPU_VR4133: - siu = siu_type2_ports; - break; - default: - return 0; - } - - port = siu_uart_ports; - num = siu_probe_ports(); - for (i = 0; i < num; i++) { - spin_lock_init(&port->lock); - port->irq = siu->irq; - port->uartclk = SIU_BAUD_BASE * 16; - port->fifosize = 16; - port->regshift = 0; - port->iotype = UPIO_MEM; - port->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; - port->type = siu->type; - port->line = i; - port->mapbase = siu->start; - siu++; - port++; - } - - return num; -} - -#ifdef CONFIG_SERIAL_VR41XX_CONSOLE - -#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) - -static void wait_for_xmitr(struct uart_port *port) -{ - int timeout = 10000; - uint8_t lsr, msr; - - do { - lsr = siu_read(port, UART_LSR); - if (lsr & UART_LSR_BI) - lsr_break_flag[port->line] = UART_LSR_BI; - - if ((lsr & BOTH_EMPTY) == BOTH_EMPTY) - break; - } while (timeout-- > 0); - - if (port->flags & UPF_CONS_FLOW) { - timeout = 1000000; - - do { - msr = siu_read(port, UART_MSR); - if ((msr & UART_MSR_CTS) != 0) - break; - } while (timeout-- > 0); - } -} - -static void siu_console_write(struct console *con, const char *s, unsigned count) -{ - struct uart_port *port; - uint8_t ier; - unsigned i; - - port = &siu_uart_ports[con->index]; - - ier = siu_read(port, UART_IER); - siu_write(port, UART_IER, 0); - - for (i = 0; i < count && *s != '\0'; i++, s++) { - wait_for_xmitr(port); - siu_write(port, UART_TX, *s); - if (*s == '\n') { - wait_for_xmitr(port); - siu_write(port, UART_TX, '\r'); - } - } - - wait_for_xmitr(port); - siu_write(port, UART_IER, ier); -} - -static int siu_console_setup(struct console *con, char *options) -{ - struct uart_port *port; - int baud = 9600; - int parity = 'n'; - int bits = 8; - int flow = 'n'; - - if (con->index >= SIU_PORTS_MAX) - con->index = 0; - - port = &siu_uart_ports[con->index]; - if (port->membase == NULL) { - if (port->mapbase == 0) - return -ENODEV; - port->membase = ioremap(port->mapbase, siu_port_size(port)); - } - - vr41xx_select_siu_interface(SIU_INTERFACE_RS232C); - - if (options != NULL) - uart_parse_options(options, &baud, &parity, &bits, &flow); - - return uart_set_options(port, con, baud, parity, bits, flow); -} - -static struct uart_driver siu_uart_driver; - -static struct console siu_console = { - .name = "ttyVR", - .write = siu_console_write, - .device = uart_console_device, - .setup = siu_console_setup, - .flags = CON_PRINTBUFFER, - .index = -1, - .data = &siu_uart_driver, -}; - -static int __devinit siu_console_init(void) -{ - struct uart_port *port; - int num, i; - - num = siu_init_ports(); - if (num <= 0) - return -ENODEV; - - for (i = 0; i < num; i++) { - port = &siu_uart_ports[i]; - port->ops = &siu_uart_ops; - } - - register_console(&siu_console); - - return 0; -} - -console_initcall(siu_console_init); - -#define SERIAL_VR41XX_CONSOLE &siu_console -#else -#define SERIAL_VR41XX_CONSOLE NULL -#endif - -static struct uart_driver siu_uart_driver = { - .owner = THIS_MODULE, - .driver_name = "SIU", - .dev_name = "ttyVR", - .devfs_name = "ttvr/", - .major = SIU_MAJOR, - .minor = SIU_MINOR_BASE, - .cons = SERIAL_VR41XX_CONSOLE, -}; - -static int siu_probe(struct device *dev) -{ - struct uart_port *port; - int num, i, retval; - - num = siu_init_ports(); - if (num <= 0) - return -ENODEV; - - siu_uart_driver.nr = num; - retval = uart_register_driver(&siu_uart_driver); - if (retval) - return retval; - - for (i = 0; i < num; i++) { - port = &siu_uart_ports[i]; - port->ops = &siu_uart_ops; - port->dev = dev; - - retval = uart_add_one_port(&siu_uart_driver, port); - if (retval < 0) { - port->dev = NULL; - break; - } - } - - if (i == 0 && retval < 0) { - uart_unregister_driver(&siu_uart_driver); - return retval; - } - - return 0; -} - -static int siu_remove(struct device *dev) -{ - struct uart_port *port; - int i; - - for (i = 0; i < siu_uart_driver.nr; i++) { - port = &siu_uart_ports[i]; - if (port->dev == dev) { - uart_remove_one_port(&siu_uart_driver, port); - port->dev = NULL; - } - } - - uart_unregister_driver(&siu_uart_driver); - - return 0; -} - -static int siu_suspend(struct device *dev, pm_message_t state, u32 level) -{ - struct uart_port *port; - int i; - - if (level != SUSPEND_DISABLE) - return 0; - - for (i = 0; i < siu_uart_driver.nr; i++) { - port = &siu_uart_ports[i]; - if ((port->type == PORT_VR41XX_SIU || - port->type == PORT_VR41XX_DSIU) && port->dev == dev) - uart_suspend_port(&siu_uart_driver, port); - - } - - return 0; -} - -static int siu_resume(struct device *dev, u32 level) -{ - struct uart_port *port; - int i; - - if (level != RESUME_ENABLE) - return 0; - - for (i = 0; i < siu_uart_driver.nr; i++) { - port = &siu_uart_ports[i]; - if ((port->type == PORT_VR41XX_SIU || - port->type == PORT_VR41XX_DSIU) && port->dev == dev) - uart_resume_port(&siu_uart_driver, port); - } - - return 0; -} - -static struct platform_device *siu_platform_device; - -static struct device_driver siu_device_driver = { - .name = "SIU", - .bus = &platform_bus_type, - .probe = siu_probe, - .remove = siu_remove, - .suspend = siu_suspend, - .resume = siu_resume, -}; - -static int __devinit vr41xx_siu_init(void) -{ - int retval; - - siu_platform_device = platform_device_register_simple("SIU", -1, NULL, 0); - if (IS_ERR(siu_platform_device)) - return PTR_ERR(siu_platform_device); - - retval = driver_register(&siu_device_driver); - if (retval < 0) - platform_device_unregister(siu_platform_device); - - return retval; -} - -static void __devexit vr41xx_siu_exit(void) -{ - driver_unregister(&siu_device_driver); - - platform_device_unregister(siu_platform_device); -} - -module_init(vr41xx_siu_init); -module_exit(vr41xx_siu_exit); diff -Naur linux-2.6.12.6.orig/drivers/tc/tc.c linux-2.6.12.6/drivers/tc/tc.c --- linux-2.6.12.6.orig/drivers/tc/tc.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/tc/tc.c 2005-10-02 23:47:39.000000000 +0000 @@ -8,33 +8,31 @@ * for more details. * * Copyright (c) Harald Koerfgen, 1998 - * Copyright (c) 2001, 2003 Maciej W. Rozycki + * Copyright (c) 2001, 2003, 2005 Maciej W. Rozycki */ -#include #include -#include #include #include +#include +#include #include +#include #include +#include +#include + #include #include #include #include #include -#include -#include - -#define TC_DEBUG MODULE_LICENSE("GPL"); slot_info tc_bus[MAX_SLOT]; static int num_tcslots; static tcinfo *info; -unsigned long system_base; - /* * Interface to the world. Read comment in include/asm-mips/tc.h. */ @@ -97,13 +95,16 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size, int slots) { + unsigned long slotaddr; int i, slot, err; long offset; - unsigned char pattern[4]; - unsigned char *module; + u8 pattern[4]; + volatile u8 *module; for (slot = 0; slot < slots; slot++) { - module = (char *)(startaddr + slot * size); + slotaddr = startaddr + slot * size; + module = ioremap_nocache(slotaddr, size); + BUG_ON(!module); offset = OLDCARD; @@ -112,8 +113,10 @@ err |= get_dbe(pattern[1], module + OLDCARD + TC_PATTERN1); err |= get_dbe(pattern[2], module + OLDCARD + TC_PATTERN2); err |= get_dbe(pattern[3], module + OLDCARD + TC_PATTERN3); - if (err) + if (err) { + iounmap(module); continue; + } if (pattern[0] != 0x55 || pattern[1] != 0x00 || pattern[2] != 0xaa || pattern[3] != 0xff) { @@ -124,16 +127,20 @@ err |= get_dbe(pattern[1], module + TC_PATTERN1); err |= get_dbe(pattern[2], module + TC_PATTERN2); err |= get_dbe(pattern[3], module + TC_PATTERN3); - if (err) + if (err) { + iounmap(module); continue; + } } if (pattern[0] != 0x55 || pattern[1] != 0x00 || - pattern[2] != 0xaa || pattern[3] != 0xff) + pattern[2] != 0xaa || pattern[3] != 0xff) { + iounmap(module); continue; + } - tc_bus[slot].base_addr = (unsigned long)module; - for(i = 0; i < 8; i++) { + tc_bus[slot].base_addr = slotaddr; + for (i = 0; i < 8; i++) { tc_bus[slot].firmware[i] = module[TC_FIRM_VER + offset + 4 * i]; tc_bus[slot].vendor[i] = @@ -171,13 +178,15 @@ tc_bus[slot].interrupt = -1; break; } + + iounmap(module); } } /* * the main entry */ -void __init tc_init(void) +static int __init tc_init(void) { int tc_clock; int i; @@ -185,7 +194,7 @@ unsigned long slot_size; if (!TURBOCHANNEL) - return; + return 0; for (i = 0; i < MAX_SLOT; i++) { tc_bus[i].base_addr = 0; @@ -196,8 +205,8 @@ tc_bus[i].flags = FREE; } - info = (tcinfo *) rex_gettcinfo(); - slot0addr = (unsigned long)KSEG1ADDR(rex_slot_address(0)); + info = rex_gettcinfo(); + slot0addr = CPHYSADDR((long)rex_slot_address(0)); switch (mips_machtype) { case MACH_DS5000_200: @@ -216,37 +225,24 @@ tc_clock = 10000 / info->clk_period; - if (TURBOCHANNEL && info->slot_size && slot0addr) { - printk("TURBOchannel rev. %1d at %2d.%1d MHz ", info->revision, - tc_clock / 10, tc_clock % 10); - printk("(with%s parity)\n", info->parity ? "" : "out"); + if (info->slot_size && slot0addr) { + pr_info("TURBOchannel rev. %d at %d.%d MHz (with%s parity)\n", + info->revision, tc_clock / 10, tc_clock % 10, + info->parity ? "" : "out"); slot_size = info->slot_size << 20; tc_probe(slot0addr, slot_size, num_tcslots); - /* - * All TURBOchannel DECstations have the onboard devices - * where the (num_tcslots + 0 or 1 on DS5k/xx) Option Module - * would be. - */ - if(mips_machtype == MACH_DS5000_XX) - i = 1; - else - i = 0; - - system_base = slot0addr + slot_size * (num_tcslots + i); - -#ifdef TC_DEBUG - for (i = 0; i < num_tcslots; i++) - if (tc_bus[i].base_addr) { - printk(" slot %d: ", i); - printk("%s %s %s\n", tc_bus[i].vendor, - tc_bus[i].name, tc_bus[i].firmware); - } -#endif - ioport_resource.end = KSEG2 - 1; + for (i = 0; i < num_tcslots; i++) { + if (!tc_bus[i].base_addr) + continue; + pr_info(" slot %d: %s %s %s\n", i, tc_bus[i].vendor, + tc_bus[i].name, tc_bus[i].firmware); + } } + + return 0; } subsys_initcall(tc_init); @@ -257,4 +253,3 @@ EXPORT_SYMBOL(get_tc_base_addr); EXPORT_SYMBOL(get_tc_irq_nr); EXPORT_SYMBOL(get_tc_speed); -EXPORT_SYMBOL(system_base); diff -Naur linux-2.6.12.6.orig/drivers/tc/zs.c linux-2.6.12.6/drivers/tc/zs.c --- linux-2.6.12.6.orig/drivers/tc/zs.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/tc/zs.c 2005-10-02 23:47:39.000000000 +0000 @@ -6,7 +6,7 @@ * * DECstation changes * Copyright (C) 1998-2000 Harald Koerfgen - * Copyright (C) 2000, 2001, 2002, 2003, 2004 Maciej W. Rozycki + * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005 Maciej W. Rozycki * * For the rest of the code the original Copyright applies: * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au) @@ -55,6 +55,7 @@ #include #include #include +#include #ifdef CONFIG_SERIAL_DEC_CONSOLE #include #endif @@ -63,16 +64,15 @@ #include #include #include -#include #include -#include -#ifdef CONFIG_MACH_DECSTATION #include +#include #include +#include +#include #include -#include -#endif + #ifdef CONFIG_KGDB #include #endif @@ -128,6 +128,8 @@ #define BUS_PRESENT (DS_BUS_PRESENT) +DEFINE_SPINLOCK(zs_lock); + struct dec_zschannel zs_channels[NUM_CHANNELS]; struct dec_serial zs_soft[NUM_CHANNELS]; int zs_channels_found; @@ -159,8 +161,6 @@ 0 /* write 15 */ }; -DECLARE_TASK_QUEUE(tq_zs_serial); - static struct tty_driver *serial_driver; /* serial subtype definitions */ @@ -192,18 +192,6 @@ static void change_speed(struct dec_serial *info); static void rs_wait_until_sent(struct tty_struct *tty, int timeout); -/* - * tmp_buf is used as a temporary buffer by serial_write. We need to - * lock it in case the copy_from_user blocks while swapping in a page, - * and some other program tries to do a serial write at the same time. - * Since the lock will only come under contention when the system is - * swapping and available memory is low, it makes sense to share one - * buffer across all the serial ports, since it significantly saves - * memory if large numbers of serial ports are open. - */ -static unsigned char tmp_buf[4096]; /* This is cheating */ -static DECLARE_MUTEX(tmp_buf_sem); - static inline int serial_paranoia_check(struct dec_serial *info, char *name, const char *routine) { @@ -306,8 +294,7 @@ { unsigned long flags; - - save_flags(flags); cli(); + spin_lock_irqsave(&zs_lock, flags); if (info->zs_channel != info->zs_chan_a) { if (set) { info->zs_chan_a->curregs[5] |= (which & (RTS | DTR)); @@ -316,7 +303,7 @@ } write_zsreg(info->zs_chan_a, 5, info->zs_chan_a->curregs[5]); } - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); } /* Utility routines for the Zilog */ @@ -357,12 +344,10 @@ * This routine is used by the interrupt handler to schedule * processing in the software interrupt portion of the driver. */ -static _INLINE_ void rs_sched_event(struct dec_serial *info, - int event) +static _INLINE_ void rs_sched_event(struct dec_serial *info, int event) { info->event |= 1 << event; - queue_task(&info->tqueue, &tq_zs_serial); - mark_bh(SERIAL_BH); + tasklet_schedule(&info->tlet); } static _INLINE_ void receive_chars(struct dec_serial *info, @@ -509,9 +494,10 @@ /* * This is the serial driver's generic interrupt routine */ -void rs_interrupt(int irq, void *dev_id, struct pt_regs * regs) +static irqreturn_t rs_interrupt(int irq, void *dev_id, struct pt_regs *regs) { struct dec_serial *info = (struct dec_serial *) dev_id; + irqreturn_t status = IRQ_NONE; unsigned char zs_intreg; int shift; @@ -533,6 +519,8 @@ if ((zs_intreg & CHAN_IRQMASK) == 0) break; + status = IRQ_HANDLED; + if (zs_intreg & CHBRxIP) { receive_chars(info, regs); } @@ -546,6 +534,8 @@ /* Why do we need this ? */ write_zsreg(info->zs_channel, 0, RES_H_IUS); + + return status; } #ifdef ZS_DEBUG_REGS @@ -590,12 +580,12 @@ return; #if 1 - save_flags(flags); cli(); + spin_lock_irqsave(&zs_lock, flags); if (info->zs_channel->curregs[5] & TxENAB) { info->zs_channel->curregs[5] &= ~TxENAB; write_zsreg(info->zs_channel, 5, info->zs_channel->curregs[5]); } - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); #endif } @@ -607,7 +597,7 @@ if (serial_paranoia_check(info, tty->name, "rs_start")) return; - save_flags(flags); cli(); + spin_lock_irqsave(&zs_lock, flags); #if 1 if (info->xmit_cnt && info->xmit_buf && !(info->zs_channel->curregs[5] & TxENAB)) { info->zs_channel->curregs[5] |= TxENAB; @@ -618,7 +608,7 @@ transmit_chars(info); } #endif - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); } /* @@ -630,12 +620,8 @@ * interrupt driver proper are done; the interrupt driver schedules * them using rs_sched_event(), and they get done here. */ -static void do_serial_bh(void) -{ - run_task_queue(&tq_zs_serial); -} -static void do_softint(void *private_) +static void do_softint(unsigned long private_) { struct dec_serial *info = (struct dec_serial *) private_; struct tty_struct *tty; @@ -646,10 +632,11 @@ if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event)) { tty_wakeup(tty); + wake_up_interruptible(&tty->write_wait); } } -int zs_startup(struct dec_serial * info) +static int zs_startup(struct dec_serial * info) { unsigned long flags; @@ -662,7 +649,7 @@ return -ENOMEM; } - save_flags(flags); cli(); + spin_lock_irqsave(&zs_lock, flags); #ifdef SERIAL_DEBUG_OPEN printk("starting up ttyS%d (irq %d)...", info->line, info->irq); @@ -718,7 +705,7 @@ info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; info->flags |= ZILOG_INITIALIZED; - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); return 0; } @@ -738,7 +725,7 @@ info->irq); #endif - save_flags(flags); cli(); /* Disable interrupts */ + spin_lock_irqsave(&zs_lock, flags); if (info->xmit_buf) { free_page((unsigned long) info->xmit_buf); @@ -761,7 +748,7 @@ set_bit(TTY_IO_ERROR, &info->tty->flags); info->flags &= ~ZILOG_INITIALIZED; - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); } /* @@ -797,7 +784,7 @@ i += 15; } - save_flags(flags); cli(); + spin_lock_irqsave(&zs_lock, flags); info->zs_baud = baud_table[i]; if (info->zs_baud) { brg = BPS_TO_BRG(info->zs_baud, zs_parms->clock/info->clk_divisor); @@ -870,7 +857,7 @@ /* Load up the new values */ load_zsregs(info->zs_channel, info->zs_channel->curregs); - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); } static void rs_flush_chars(struct tty_struct *tty) @@ -886,9 +873,9 @@ return; /* Enable transmitter */ - save_flags(flags); cli(); + spin_lock_irqsave(&zs_lock, flags); transmit_chars(info); - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); } static int rs_write(struct tty_struct * tty, @@ -904,26 +891,17 @@ if (!tty || !info->xmit_buf) return 0; - save_flags(flags); while (1) { - cli(); + spin_lock_irqsave(&zs_lock, flags); c = min(count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, SERIAL_XMIT_SIZE - info->xmit_head)); if (c <= 0) break; - if (from_user) { - down(&tmp_buf_sem); - copy_from_user(tmp_buf, buf, c); - c = min(c, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, - SERIAL_XMIT_SIZE - info->xmit_head)); - memcpy(info->xmit_buf + info->xmit_head, tmp_buf, c); - up(&tmp_buf_sem); - } else - memcpy(info->xmit_buf + info->xmit_head, buf, c); + memcpy(info->xmit_buf + info->xmit_head, buf, c); info->xmit_head = (info->xmit_head + c) & (SERIAL_XMIT_SIZE-1); info->xmit_cnt += c; - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); buf += c; count -= c; total += c; @@ -932,7 +910,7 @@ if (info->xmit_cnt && !tty->stopped && !info->tx_stopped && !info->tx_active) transmit_chars(info); - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); return total; } @@ -964,9 +942,9 @@ if (serial_paranoia_check(info, tty->name, "rs_flush_buffer")) return; - cli(); + spin_lock_irq(&zs_lock); info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; - sti(); + spin_unlock_irq(&zs_lock); tty_wakeup(tty); } @@ -994,11 +972,11 @@ return; if (I_IXOFF(tty)) { - save_flags(flags); cli(); + spin_lock_irqsave(&zs_lock, flags); info->x_char = STOP_CHAR(tty); if (!info->tx_active) transmit_chars(info); - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); } if (C_CRTSCTS(tty)) { @@ -1022,7 +1000,7 @@ return; if (I_IXOFF(tty)) { - save_flags(flags); cli(); + spin_lock_irqsave(&zs_lock, flags); if (info->x_char) info->x_char = 0; else { @@ -1030,7 +1008,7 @@ if (!info->tx_active) transmit_chars(info); } - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); } if (C_CRTSCTS(tty)) { @@ -1123,9 +1101,9 @@ { unsigned char status; - cli(); + spin_lock(&zs_lock); status = read_zsreg(info->zs_channel, 0); - sti(); + spin_unlock_irq(&zs_lock); put_user(status,value); return 0; } @@ -1148,11 +1126,11 @@ if (info->zs_channel == info->zs_chan_a) result = 0; else { - cli(); + spin_lock(&zs_lock); control = info->zs_chan_a->curregs[5]; status_a = read_zsreg(info->zs_chan_a, 0); status_b = read_zsreg(info->zs_channel, 0); - sti(); + spin_unlock_irq(&zs_lock); result = ((control & RTS) ? TIOCM_RTS: 0) | ((control & DTR) ? TIOCM_DTR: 0) | ((status_b & DCD) ? TIOCM_CAR: 0) @@ -1167,8 +1145,6 @@ unsigned int set, unsigned int clear) { struct dec_serial * info = (struct dec_serial *)tty->driver_data; - int error; - unsigned int arg, bits; if (info->hook) return -ENODEV; @@ -1182,8 +1158,7 @@ if (info->zs_channel == info->zs_chan_a) return 0; - get_user(arg, value); - cli(); + spin_lock(&zs_lock); if (set & TIOCM_RTS) info->zs_chan_a->curregs[5] |= RTS; if (set & TIOCM_DTR) @@ -1193,7 +1168,7 @@ if (clear & TIOCM_DTR) info->zs_chan_a->curregs[5] &= ~DTR; write_zsreg(info->zs_chan_a, 5, info->zs_chan_a->curregs[5]); - sti(); + spin_unlock_irq(&zs_lock); return 0; } @@ -1210,19 +1185,18 @@ if (!info->port) return; - save_flags(flags); cli(); + spin_lock_irqsave(&zs_lock, flags); if (break_state == -1) info->zs_channel->curregs[5] |= SND_BRK; else info->zs_channel->curregs[5] &= ~SND_BRK; write_zsreg(info->zs_channel, 5, info->zs_channel->curregs[5]); - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); } static int rs_ioctl(struct tty_struct *tty, struct file * file, unsigned int cmd, unsigned long arg) { - int error; struct dec_serial * info = (struct dec_serial *)tty->driver_data; if (info->hook) @@ -1299,10 +1273,10 @@ if (!info || serial_paranoia_check(info, tty->name, "rs_close")) return; - save_flags(flags); cli(); + spin_lock_irqsave(&zs_lock, flags); if (tty_hung_up_p(filp)) { - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); return; } @@ -1327,7 +1301,7 @@ info->count = 0; } if (info->count) { - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); return; } info->flags |= ZILOG_CLOSING; @@ -1370,7 +1344,7 @@ } info->flags &= ~(ZILOG_NORMAL_ACTIVE|ZILOG_CLOSING); wake_up_interruptible(&info->close_wait); - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); } /* @@ -1410,7 +1384,7 @@ /* * rs_hangup() --- called by tty_hangup() when a hangup is signaled. */ -void rs_hangup(struct tty_struct *tty) +static void rs_hangup(struct tty_struct *tty) { struct dec_serial * info = (struct dec_serial *)tty->driver_data; @@ -1478,16 +1452,16 @@ printk("block_til_ready before block: ttyS%d, count = %d\n", info->line, info->count); #endif - cli(); + spin_lock(&zs_lock); if (!tty_hung_up_p(filp)) info->count--; - sti(); + spin_unlock_irq(&zs_lock); info->blocked_open++; while (1) { - cli(); + spin_lock(&zs_lock); if (tty->termios->c_cflag & CBAUD) zs_rtsdtr(info, RTS | DTR, 1); - sti(); + spin_unlock_irq(&zs_lock); set_current_state(TASK_INTERRUPTIBLE); if (tty_hung_up_p(filp) || !(info->flags & ZILOG_INITIALIZED)) { @@ -1535,7 +1509,7 @@ * the IRQ chain. It also performs the serial-specific * initialization for the tty structure. */ -int rs_open(struct tty_struct *tty, struct file * filp) +static int rs_open(struct tty_struct *tty, struct file * filp) { struct dec_serial *info; int retval, line; @@ -1628,30 +1602,22 @@ return; } - /* - * When serial console is activated, tc_init has not been called yet - * and system_base is undefined. Unfortunately we have to hardcode - * system_base for this case :-(. HK - */ switch(mips_machtype) { #ifdef CONFIG_MACH_DECSTATION case MACH_DS5000_2X0: case MACH_DS5900: - system_base = KSEG1ADDR(0x1f800000); n_chips = 2; zs_parms = &ds_parms; zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0]; zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1]; break; case MACH_DS5000_1XX: - system_base = KSEG1ADDR(0x1c000000); n_chips = 2; zs_parms = &ds_parms; zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0]; zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1]; break; case MACH_DS5000_XX: - system_base = KSEG1ADDR(0x1c000000); n_chips = 1; zs_parms = &ds_parms; zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0]; @@ -1673,10 +1639,10 @@ * The sccs reside on the high byte of the 16 bit IOBUS */ zs_channels[n_channels].control = - (volatile unsigned char *)system_base + + (volatile void *)CKSEG1ADDR(dec_kn_slot_base + (0 == chip ? zs_parms->scc0 : zs_parms->scc1) + (0 == channel ? zs_parms->channel_a_offset : - zs_parms->channel_b_offset); + zs_parms->channel_b_offset)); zs_channels[n_channels].data = zs_channels[n_channels].control + 4; @@ -1726,7 +1692,7 @@ } } - save_and_cli(flags); + spin_lock_irqsave(&zs_lock, flags); for (n = 0; n < zs_channels_found; n++) { if (n % 2 == 0) { write_zsreg(zs_soft[n].zs_chan_a, R9, FHWRES); @@ -1736,7 +1702,7 @@ load_zsregs(zs_soft[n].zs_channel, zs_soft[n].zs_channel->curregs); } - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); } static struct tty_operations serial_ops = { @@ -1769,9 +1735,6 @@ if(!BUS_PRESENT) return -ENODEV; - /* Setup base handler, and timer table. */ - init_bh(SERIAL_BH, do_serial_bh); - /* Find out how many Z8530 SCCs we have */ if (zs_chain == 0) probe_sccs(); @@ -1820,8 +1783,7 @@ info->event = 0; info->count = 0; info->blocked_open = 0; - info->tqueue.routine = do_softint; - info->tqueue.data = info; + tasklet_init(&info->tlet, do_softint, (unsigned long)info); init_waitqueue_head(&info->open_wait); init_waitqueue_head(&info->close_wait); printk("ttyS%02d at 0x%08x (irq = %d) is a Z85C30 SCC\n", @@ -1853,8 +1815,7 @@ /* * polling I/O routines */ -static int -zs_poll_tx_char(void *handle, unsigned char ch) +static int zs_poll_tx_char(void *handle, unsigned char ch) { struct dec_serial *info = handle; struct dec_zschannel *chan = info->zs_channel; @@ -1877,8 +1838,7 @@ return -ENODEV; } -static int -zs_poll_rx_char(void *handle) +static int zs_poll_rx_char(void *handle) { struct dec_serial *info = handle; struct dec_zschannel *chan = info->zs_channel; @@ -2057,7 +2017,7 @@ } co->cflag = cflag; - save_and_cli(flags); + spin_lock_irqsave(&zs_lock, flags); /* * Set up the baud rate generator. @@ -2112,7 +2072,7 @@ zs_soft[co->index].clk_divisor = clk_divisor; zs_soft[co->index].zs_baud = get_zsbaud(&zs_soft[co->index]); - restore_flags(flags); + spin_unlock_irqrestore(&zs_lock, flags); return 0; } @@ -2249,5 +2209,3 @@ set_debug_traps(); /* init stub */ } #endif /* ifdef CONFIG_KGDB */ - - diff -Naur linux-2.6.12.6.orig/drivers/tc/zs.h linux-2.6.12.6/drivers/tc/zs.h --- linux-2.6.12.6.orig/drivers/tc/zs.h 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/tc/zs.h 2005-10-02 23:47:39.000000000 +0000 @@ -6,14 +6,14 @@ * * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au) * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) - * Copyright (C) 2004 Maciej W. Rozycki + * Copyright (C) 2004, 2005 Maciej W. Rozycki */ #ifndef _DECSERIAL_H #define _DECSERIAL_H #include -#define NUM_ZSREGS 16 +#define NUM_ZSREGS 16 struct serial_struct { int type; @@ -44,24 +44,24 @@ */ #define ZILOG_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes on the callout port */ -#define ZILOG_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */ +#define ZILOG_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */ #define ZILOG_SAK 0x0004 /* Secure Attention Key (Orange book) */ #define ZILOG_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */ #define ZILOG_SPD_MASK 0x0030 #define ZILOG_SPD_HI 0x0010 /* Use 56000 instead of 38400 bps */ -#define ZILOG_SPD_VHI 0x0020 /* Use 115200 instead of 38400 bps */ -#define ZILOG_SPD_CUST 0x0030 /* Use user-specified divisor */ +#define ZILOG_SPD_VHI 0x0020 /* Use 115200 instead of 38400 bps */ +#define ZILOG_SPD_CUST 0x0030 /* Use user-specified divisor */ #define ZILOG_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */ -#define ZILOG_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */ +#define ZILOG_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */ #define ZILOG_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */ #define ZILOG_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */ #define ZILOG_CALLOUT_NOHUP 0x0400 /* Don't do hangups for cua device */ #define ZILOG_FLAGS 0x0FFF /* Possible legal ZILOG flags */ -#define ZILOG_USR_MASK 0x0430 /* Legal flags that non-privileged +#define ZILOG_USR_MASK 0x0430 /* Legal flags that non-privileged * users can set or reset */ /* Internal flags used only by kernel/chr_drv/serial.c */ @@ -139,8 +139,7 @@ int xmit_head; int xmit_tail; int xmit_cnt; - struct tq_struct tqueue; - struct tq_struct tqueue_hangup; + struct tasklet_struct tlet; wait_queue_head_t open_wait; wait_queue_head_t close_wait; }; @@ -282,7 +281,7 @@ #define DLC 4 /* Disable Lower Chain */ #define MIE 8 /* Master Interrupt Enable */ #define STATHI 0x10 /* Status high */ -#define SOFTACK 0x20 /* Software Interrupt Acknowledge */ +#define SOFTACK 0x20 /* Software Interrupt Acknowledge */ #define NORESET 0 /* No reset on write to R9 */ #define CHRB 0x40 /* Reset channel B */ #define CHRA 0x80 /* Reset channel A */ @@ -395,8 +394,8 @@ /* Read Register 15 (value of WR 15) */ /* Misc macros */ -#define ZS_CLEARERR(channel) (write_zsreg(channel, 0, ERR_RES)) -#define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \ +#define ZS_CLEARERR(channel) (write_zsreg(channel, 0, ERR_RES)) +#define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \ garbage = read_zsdata(channel); \ garbage = read_zsdata(channel); \ garbage = read_zsdata(channel); \ diff -Naur linux-2.6.12.6.orig/drivers/usb/gadget/net2280.c linux-2.6.12.6/drivers/usb/gadget/net2280.c --- linux-2.6.12.6.orig/drivers/usb/gadget/net2280.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/usb/gadget/net2280.c 2005-10-02 23:47:39.000000000 +0000 @@ -448,7 +448,8 @@ #elif defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE) #define USE_KMALLOC -#elif defined(CONFIG_MIPS) && !defined(CONFIG_NONCOHERENT_IO) +#elif defined(CONFIG_MIPS) && \ + (defined(CONFIG_DMA_COHERENT) || defined(CONFIG_DMA_IP27)) #define USE_KMALLOC /* FIXME there are other cases, including an x86-64 one ... */ diff -Naur linux-2.6.12.6.orig/drivers/usb/host/ohci-au1xxx.c linux-2.6.12.6/drivers/usb/host/ohci-au1xxx.c --- linux-2.6.12.6.orig/drivers/usb/host/ohci-au1xxx.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/usb/host/ohci-au1xxx.c 2005-10-02 23:47:39.000000000 +0000 @@ -51,7 +51,7 @@ /* wait for reset complete (read register twice; see au1500 errata) */ while (au_readl(USB_HOST_CONFIG), - !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD)) + !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD)) udelay(1000); printk(KERN_DEBUG __FILE__ @@ -89,12 +89,12 @@ int retval; struct usb_hcd *hcd; - if(dev->resource[1].flags != IORESOURCE_IRQ) { + if (dev->resource[1].flags != IORESOURCE_IRQ) { pr_debug ("resource[1] is not IORESOURCE_IRQ"); - return -ENOMEM; + retval = -ENOMEM; } - hcd = usb_create_hcd(driver, &dev->dev, "au1xxx"); + hcd = usb_create_hcd(driver, &dev->dev, "Au1xxx"); if (!hcd) return -ENOMEM; hcd->rsrc_start = dev->resource[0].start; @@ -161,7 +161,7 @@ int ret; ohci_dbg (ohci, "ohci_au1xxx_start, ohci:%p", ohci); - + if ((ret = ohci_init (ohci)) < 0) return ret; diff -Naur linux-2.6.12.6.orig/drivers/usb/host/ohci-hcd.c linux-2.6.12.6/drivers/usb/host/ohci-hcd.c --- linux-2.6.12.6.orig/drivers/usb/host/ohci-hcd.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/usb/host/ohci-hcd.c 2005-10-02 23:47:39.000000000 +0000 @@ -901,10 +901,6 @@ #include "ohci-lh7a404.c" #endif -#ifdef CONFIG_PXA27x -#include "ohci-pxa27x.c" -#endif - #ifdef CONFIG_SOC_AU1X00 #include "ohci-au1xxx.c" #endif diff -Naur linux-2.6.12.6.orig/drivers/video/Kconfig linux-2.6.12.6/drivers/video/Kconfig --- linux-2.6.12.6.orig/drivers/video/Kconfig 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/video/Kconfig 2005-10-02 23:47:39.000000000 +0000 @@ -1164,6 +1164,19 @@ Please read the for supported options and other important info support. +config FB_SMIVGX + tristate "Silicon Motion VoyagerGX support" + depends on FB && PCI && (MIPS || EXPERIMENTAL) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FB_SOFT_CURSOR + ---help--- + This drivers supports SMI VoyagerGX 501 based PCI boards + The default settings drive both a CRT and LCD. The CRT + can be turned off by passing in the no_crt option + + config FB_TRIDENT tristate "Trident support" depends on FB && PCI @@ -1233,7 +1246,15 @@ config FB_AU1100 bool "Au1100 LCD Driver" - depends on (FB = y) && EXPERIMENTAL && PCI && MIPS && MIPS_PB1100=y + depends on FB && MIPS && SOC_AU1100 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FB_SOFT_CURSOR + help + This is the framebuffer driver for the AMD Au1100 SOC. It can drive + various panels and CRTs by passing in kernel cmd line option + au1100fb:panel=. source "drivers/video/geode/Kconfig" @@ -1325,7 +1346,7 @@ config FB_PMAG_AA bool "PMAG-AA TURBOchannel framebuffer support" - depends on (FB = y) && MACH_DECSTATION && TC + depends on (FB = y) && TC select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT @@ -1336,7 +1357,7 @@ config FB_PMAG_BA bool "PMAG-BA TURBOchannel framebuffer support" - depends on (FB = y) && MACH_DECSTATION && TC + depends on (FB = y) && TC select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT @@ -1347,19 +1368,19 @@ config FB_PMAGB_B bool "PMAGB-B TURBOchannel framebuffer support" - depends on (FB = y) && MACH_DECSTATION && TC + depends on (FB = y) && TC select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT select FB_SOFT_CURSOR help Support for the PMAGB-B TURBOchannel framebuffer card used mainly - in the MIPS-based DECstation series. The card is currently only - supported in 1280x1024x8 mode. + in the MIPS-based DECstation series. The card is currently only + supported in 1280x1024x8 mode. config FB_MAXINE bool "Maxine (Personal DECstation) onboard framebuffer support" - depends on (FB = y) && MACH_DECSTATION && TC + depends on (FB = y) && MACH_DECSTATION select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT diff -Naur linux-2.6.12.6.orig/drivers/video/Makefile linux-2.6.12.6/drivers/video/Makefile --- linux-2.6.12.6.orig/drivers/video/Makefile 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/video/Makefile 2005-10-02 23:47:39.000000000 +0000 @@ -83,7 +83,7 @@ obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o obj-$(CONFIG_FB_PXA) += pxafb.o obj-$(CONFIG_FB_W100) += w100fb.o -obj-$(CONFIG_FB_AU1100) += au1100fb.o fbgen.o +obj-$(CONFIG_FB_AU1100) += au1100fb.o obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o @@ -91,6 +91,7 @@ obj-$(CONFIG_FB_TX3912) += tx3912fb.o obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o obj-$(CONFIG_FB_IMX) += imxfb.o +obj-$(CONFIG_FB_SMIVGX) += smivgxfb.o # Platform or fallback drivers go here obj-$(CONFIG_FB_VESA) += vesafb.o diff -Naur linux-2.6.12.6.orig/drivers/video/au1100fb.c linux-2.6.12.6/drivers/video/au1100fb.c --- linux-2.6.12.6.orig/drivers/video/au1100fb.c 2005-08-29 16:55:27.000000000 +0000 +++ linux-2.6.12.6/drivers/video/au1100fb.c 2005-10-02 23:47:39.000000000 +0000 @@ -2,6 +2,11 @@ * BRIEF MODULE DESCRIPTION * Au1100 LCD Driver. * + * Rewritten for 2.6 by Embedded Alley Solutions + * , based on submissions by + * Karl Lessard + * + * * Copyright 2002 MontaVista Software * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com @@ -34,297 +39,253 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ +#include #include #include #include #include #include -#include -#include -#include #include #include -#include +#include +#include +#include -#include -#include -#include "au1100fb.h" +#include -#include